1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include "mtk_mipi_tx.h"
7
8inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
9{
10	return container_of(hw, struct mtk_mipi_tx, pll_hw);
11}
12
13void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
14			    u32 bits)
15{
16	u32 temp = readl(mipi_tx->regs + offset);
17
18	writel(temp & ~bits, mipi_tx->regs + offset);
19}
20
21void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
22			  u32 bits)
23{
24	u32 temp = readl(mipi_tx->regs + offset);
25
26	writel(temp | bits, mipi_tx->regs + offset);
27}
28
29void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
30			     u32 mask, u32 data)
31{
32	u32 temp = readl(mipi_tx->regs + offset);
33
34	writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
35}
36
37int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
38			     unsigned long parent_rate)
39{
40	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
41
42	dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate);
43
44	mipi_tx->data_rate = rate;
45
46	return 0;
47}
48
49unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
50					  unsigned long parent_rate)
51{
52	struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
53
54	return mipi_tx->data_rate;
55}
56
57static int mtk_mipi_tx_power_on(struct phy *phy)
58{
59	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
60	int ret;
61
62	/* Power up core and enable PLL */
63	ret = clk_prepare_enable(mipi_tx->pll);
64	if (ret < 0)
65		return ret;
66
67	/* Enable DSI Lane LDO outputs, disable pad tie low */
68	mipi_tx->driver_data->mipi_tx_enable_signal(phy);
69	return 0;
70}
71
72static int mtk_mipi_tx_power_off(struct phy *phy)
73{
74	struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
75
76	/* Enable pad tie low, disable DSI Lane LDO outputs */
77	mipi_tx->driver_data->mipi_tx_disable_signal(phy);
78
79	/* Disable PLL and power down core */
80	clk_disable_unprepare(mipi_tx->pll);
81
82	return 0;
83}
84
85static const struct phy_ops mtk_mipi_tx_ops = {
86	.power_on = mtk_mipi_tx_power_on,
87	.power_off = mtk_mipi_tx_power_off,
88	.owner = THIS_MODULE,
89};
90
91static void mtk_mipi_tx_get_calibration_datal(struct mtk_mipi_tx *mipi_tx)
92{
93	struct nvmem_cell *cell;
94	size_t len;
95	u32 *buf;
96
97	cell = nvmem_cell_get(mipi_tx->dev, "calibration-data");
98	if (IS_ERR(cell)) {
99		dev_info(mipi_tx->dev, "can't get nvmem_cell_get, ignore it\n");
100		return;
101	}
102	buf = (u32 *)nvmem_cell_read(cell, &len);
103	nvmem_cell_put(cell);
104
105	if (IS_ERR(buf)) {
106		dev_info(mipi_tx->dev, "can't get data, ignore it\n");
107		return;
108	}
109
110	if (len < 3 * sizeof(u32)) {
111		dev_info(mipi_tx->dev, "invalid calibration data\n");
112		kfree(buf);
113		return;
114	}
115
116	mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) |
117			       (buf[0] >> 11 & 0x1f);
118	mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) |
119			       (buf[0] >> 1 & 0x1f);
120	mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) |
121			       (buf[1] >> 22 & 0x1f);
122	mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) |
123			       (buf[1] >> 12 & 0x1f);
124	mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) |
125			       (buf[1] >> 2 & 0x1f);
126	kfree(buf);
127}
128
129static int mtk_mipi_tx_probe(struct platform_device *pdev)
130{
131	struct device *dev = &pdev->dev;
132	struct mtk_mipi_tx *mipi_tx;
133	struct resource *mem;
134	const char *ref_clk_name;
135	struct clk *ref_clk;
136	struct clk_init_data clk_init = {
137		.num_parents = 1,
138		.parent_names = (const char * const *)&ref_clk_name,
139		.flags = CLK_SET_RATE_GATE,
140	};
141	struct phy *phy;
142	struct phy_provider *phy_provider;
143	int ret;
144
145	mipi_tx = devm_kzalloc(dev, sizeof(*mipi_tx), GFP_KERNEL);
146	if (!mipi_tx)
147		return -ENOMEM;
148
149	mipi_tx->driver_data = of_device_get_match_data(dev);
150	if (!mipi_tx->driver_data)
151		return -ENODEV;
152
153	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
154	mipi_tx->regs = devm_ioremap_resource(dev, mem);
155	if (IS_ERR(mipi_tx->regs)) {
156		ret = PTR_ERR(mipi_tx->regs);
157		dev_err(dev, "Failed to get memory resource: %d\n", ret);
158		return ret;
159	}
160
161	ref_clk = devm_clk_get(dev, NULL);
162	if (IS_ERR(ref_clk)) {
163		ret = PTR_ERR(ref_clk);
164		dev_err(dev, "Failed to get reference clock: %d\n", ret);
165		return ret;
166	}
167
168	ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
169				   &mipi_tx->mipitx_drive);
170	/* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
171	if (ret < 0)
172		mipi_tx->mipitx_drive = 4600;
173
174	/* check the mipitx_drive valid */
175	if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) {
176		dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
177			 mipi_tx->mipitx_drive);
178		mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
179						  6000);
180	}
181
182	ref_clk_name = __clk_get_name(ref_clk);
183
184	ret = of_property_read_string(dev->of_node, "clock-output-names",
185				      &clk_init.name);
186	if (ret < 0) {
187		dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
188		return ret;
189	}
190
191	clk_init.ops = mipi_tx->driver_data->mipi_tx_clk_ops;
192
193	mipi_tx->pll_hw.init = &clk_init;
194	mipi_tx->pll = devm_clk_register(dev, &mipi_tx->pll_hw);
195	if (IS_ERR(mipi_tx->pll)) {
196		ret = PTR_ERR(mipi_tx->pll);
197		dev_err(dev, "Failed to register PLL: %d\n", ret);
198		return ret;
199	}
200
201	phy = devm_phy_create(dev, NULL, &mtk_mipi_tx_ops);
202	if (IS_ERR(phy)) {
203		ret = PTR_ERR(phy);
204		dev_err(dev, "Failed to create MIPI D-PHY: %d\n", ret);
205		return ret;
206	}
207	phy_set_drvdata(phy, mipi_tx);
208
209	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
210	if (IS_ERR(phy_provider)) {
211		ret = PTR_ERR(phy_provider);
212		return ret;
213	}
214
215	mipi_tx->dev = dev;
216
217	mtk_mipi_tx_get_calibration_datal(mipi_tx);
218
219	return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
220				   mipi_tx->pll);
221}
222
223static int mtk_mipi_tx_remove(struct platform_device *pdev)
224{
225	of_clk_del_provider(pdev->dev.of_node);
226	return 0;
227}
228
229static const struct of_device_id mtk_mipi_tx_match[] = {
230	{ .compatible = "mediatek,mt2701-mipi-tx",
231	  .data = &mt2701_mipitx_data },
232	{ .compatible = "mediatek,mt8173-mipi-tx",
233	  .data = &mt8173_mipitx_data },
234	{ .compatible = "mediatek,mt8183-mipi-tx",
235	  .data = &mt8183_mipitx_data },
236	{ },
237};
238
239struct platform_driver mtk_mipi_tx_driver = {
240	.probe = mtk_mipi_tx_probe,
241	.remove = mtk_mipi_tx_remove,
242	.driver = {
243		.name = "mediatek-mipi-tx",
244		.of_match_table = mtk_mipi_tx_match,
245	},
246};
247
248