1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6#include <linux/clk.h> 7#include <linux/pm_runtime.h> 8#include <linux/soc/mediatek/mtk-cmdq.h> 9#include <linux/soc/mediatek/mtk-mmsys.h> 10 11#include <asm/barrier.h> 12#include <soc/mediatek/smi.h> 13 14#include <drm/drm_atomic_helper.h> 15#include <drm/drm_plane_helper.h> 16#include <drm/drm_probe_helper.h> 17#include <drm/drm_vblank.h> 18 19#include "mtk_drm_drv.h" 20#include "mtk_drm_crtc.h" 21#include "mtk_drm_ddp.h" 22#include "mtk_drm_ddp_comp.h" 23#include "mtk_drm_gem.h" 24#include "mtk_drm_plane.h" 25 26/** 27 * struct mtk_drm_crtc - MediaTek specific crtc structure. 28 * @base: crtc object. 29 * @enabled: records whether crtc_enable succeeded 30 * @planes: array of 4 drm_plane structures, one for each overlay plane 31 * @pending_planes: whether any plane has pending changes to be applied 32 * @mmsys_dev: pointer to the mmsys device for configuration registers 33 * @mutex: handle to one of the ten disp_mutex streams 34 * @ddp_comp_nr: number of components in ddp_comp 35 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 36 */ 37struct mtk_drm_crtc { 38 struct drm_crtc base; 39 bool enabled; 40 41 bool pending_needs_vblank; 42 struct drm_pending_vblank_event *event; 43 44 struct drm_plane *planes; 45 unsigned int layer_nr; 46 bool pending_planes; 47 bool pending_async_planes; 48 49#if IS_REACHABLE(CONFIG_MTK_CMDQ) 50 struct cmdq_client *cmdq_client; 51 u32 cmdq_event; 52#endif 53 54 struct device *mmsys_dev; 55 struct mtk_disp_mutex *mutex; 56 unsigned int ddp_comp_nr; 57 struct mtk_ddp_comp **ddp_comp; 58 59 /* lock for display hardware access */ 60 struct mutex hw_lock; 61}; 62 63struct mtk_crtc_state { 64 struct drm_crtc_state base; 65 66 bool pending_config; 67 unsigned int pending_width; 68 unsigned int pending_height; 69 unsigned int pending_vrefresh; 70}; 71 72static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 73{ 74 return container_of(c, struct mtk_drm_crtc, base); 75} 76 77static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 78{ 79 return container_of(s, struct mtk_crtc_state, base); 80} 81 82static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 83{ 84 struct drm_crtc *crtc = &mtk_crtc->base; 85 unsigned long flags; 86 87 spin_lock_irqsave(&crtc->dev->event_lock, flags); 88 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 89 drm_crtc_vblank_put(crtc); 90 mtk_crtc->event = NULL; 91 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 92} 93 94static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 95{ 96 drm_crtc_handle_vblank(&mtk_crtc->base); 97 if (mtk_crtc->pending_needs_vblank) { 98 mtk_drm_crtc_finish_page_flip(mtk_crtc); 99 mtk_crtc->pending_needs_vblank = false; 100 } 101} 102 103static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 104{ 105 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 106 107 mtk_disp_mutex_put(mtk_crtc->mutex); 108 109 drm_crtc_cleanup(crtc); 110} 111 112static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 113{ 114 struct mtk_crtc_state *state; 115 116 if (crtc->state) 117 __drm_atomic_helper_crtc_destroy_state(crtc->state); 118 119 kfree(to_mtk_crtc_state(crtc->state)); 120 crtc->state = NULL; 121 122 state = kzalloc(sizeof(*state), GFP_KERNEL); 123 if (state) 124 __drm_atomic_helper_crtc_reset(crtc, &state->base); 125} 126 127static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 128{ 129 struct mtk_crtc_state *state; 130 131 state = kzalloc(sizeof(*state), GFP_KERNEL); 132 if (!state) 133 return NULL; 134 135 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 136 137 WARN_ON(state->base.crtc != crtc); 138 state->base.crtc = crtc; 139 140 return &state->base; 141} 142 143static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 144 struct drm_crtc_state *state) 145{ 146 __drm_atomic_helper_crtc_destroy_state(state); 147 kfree(to_mtk_crtc_state(state)); 148} 149 150static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 151 const struct drm_display_mode *mode, 152 struct drm_display_mode *adjusted_mode) 153{ 154 /* Nothing to do here, but this callback is mandatory. */ 155 return true; 156} 157 158static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 159{ 160 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 161 162 state->pending_width = crtc->mode.hdisplay; 163 state->pending_height = crtc->mode.vdisplay; 164 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode); 165 wmb(); /* Make sure the above parameters are set before update */ 166 state->pending_config = true; 167} 168 169static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 170{ 171 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 172 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 173 174 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 175 176 return 0; 177} 178 179static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 180{ 181 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 182 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 183 184 mtk_ddp_comp_disable_vblank(comp); 185} 186 187static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 188{ 189 int ret; 190 int i; 191 192 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 193 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 194 if (ret) { 195 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 196 goto err; 197 } 198 } 199 200 return 0; 201err: 202 while (--i >= 0) 203 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 204 return ret; 205} 206 207static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 208{ 209 int i; 210 211 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 212 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 213} 214 215static 216struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 217 struct drm_plane *plane, 218 unsigned int *local_layer) 219{ 220 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 221 struct mtk_ddp_comp *comp; 222 int i, count = 0; 223 unsigned int local_index = plane - mtk_crtc->planes; 224 225 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 226 comp = mtk_crtc->ddp_comp[i]; 227 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 228 *local_layer = local_index - count; 229 return comp; 230 } 231 count += mtk_ddp_comp_layer_nr(comp); 232 } 233 234 WARN(1, "Failed to find component for plane %d\n", plane->index); 235 return NULL; 236} 237 238#if IS_REACHABLE(CONFIG_MTK_CMDQ) 239static void ddp_cmdq_cb(struct cmdq_cb_data data) 240{ 241 cmdq_pkt_destroy(data.data); 242} 243#endif 244 245static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 246{ 247 struct drm_crtc *crtc = &mtk_crtc->base; 248 struct drm_connector *connector; 249 struct drm_encoder *encoder; 250 struct drm_connector_list_iter conn_iter; 251 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 252 int ret; 253 int i; 254 255 if (WARN_ON(!crtc->state)) 256 return -EINVAL; 257 258 width = crtc->state->adjusted_mode.hdisplay; 259 height = crtc->state->adjusted_mode.vdisplay; 260 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode); 261 262 drm_for_each_encoder(encoder, crtc->dev) { 263 if (encoder->crtc != crtc) 264 continue; 265 266 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 267 drm_for_each_connector_iter(connector, &conn_iter) { 268 if (connector->encoder != encoder) 269 continue; 270 if (connector->display_info.bpc != 0 && 271 bpc > connector->display_info.bpc) 272 bpc = connector->display_info.bpc; 273 } 274 drm_connector_list_iter_end(&conn_iter); 275 } 276 277 ret = pm_runtime_resume_and_get(crtc->dev->dev); 278 if (ret < 0) { 279 DRM_ERROR("Failed to enable power domain: %d\n", ret); 280 return ret; 281 } 282 283 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 284 if (ret < 0) { 285 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 286 goto err_pm_runtime_put; 287 } 288 289 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 290 if (ret < 0) { 291 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 292 goto err_mutex_unprepare; 293 } 294 295 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 296 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, 297 mtk_crtc->ddp_comp[i]->id, 298 mtk_crtc->ddp_comp[i + 1]->id); 299 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 300 mtk_crtc->ddp_comp[i]->id); 301 } 302 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 303 mtk_disp_mutex_enable(mtk_crtc->mutex); 304 305 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 306 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 307 308 if (i == 1) 309 mtk_ddp_comp_bgclr_in_on(comp); 310 311 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 312 mtk_ddp_comp_start(comp); 313 } 314 315 /* Initially configure all planes */ 316 for (i = 0; i < mtk_crtc->layer_nr; i++) { 317 struct drm_plane *plane = &mtk_crtc->planes[i]; 318 struct mtk_plane_state *plane_state; 319 struct mtk_ddp_comp *comp; 320 unsigned int local_layer; 321 322 plane_state = to_mtk_plane_state(plane->state); 323 324 /* should not enable layer before crtc enabled */ 325 plane_state->pending.enable = false; 326 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 327 if (comp) 328 mtk_ddp_comp_layer_config(comp, local_layer, 329 plane_state, NULL); 330 } 331 332 return 0; 333 334err_mutex_unprepare: 335 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 336err_pm_runtime_put: 337 pm_runtime_put(crtc->dev->dev); 338 return ret; 339} 340 341static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 342{ 343 struct drm_device *drm = mtk_crtc->base.dev; 344 struct drm_crtc *crtc = &mtk_crtc->base; 345 int i; 346 347 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 348 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 349 if (i == 1) 350 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 351 } 352 353 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 354 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 355 mtk_crtc->ddp_comp[i]->id); 356 mtk_disp_mutex_disable(mtk_crtc->mutex); 357 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 358 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, 359 mtk_crtc->ddp_comp[i]->id, 360 mtk_crtc->ddp_comp[i + 1]->id); 361 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 362 mtk_crtc->ddp_comp[i]->id); 363 } 364 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 365 mtk_crtc_ddp_clk_disable(mtk_crtc); 366 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 367 368 pm_runtime_put(drm->dev); 369 370 if (crtc->state->event && !crtc->state->active) { 371 spin_lock_irq(&crtc->dev->event_lock); 372 drm_crtc_send_vblank_event(crtc, crtc->state->event); 373 crtc->state->event = NULL; 374 spin_unlock_irq(&crtc->dev->event_lock); 375 } 376} 377 378static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 379 struct cmdq_pkt *cmdq_handle) 380{ 381 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 382 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 383 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 384 unsigned int i; 385 unsigned int local_layer; 386 387 /* 388 * TODO: instead of updating the registers here, we should prepare 389 * working registers in atomic_commit and let the hardware command 390 * queue update module registers on vblank. 391 */ 392 if (state->pending_config) { 393 mtk_ddp_comp_config(comp, state->pending_width, 394 state->pending_height, 395 state->pending_vrefresh, 0, 396 cmdq_handle); 397 398 state->pending_config = false; 399 } 400 401 if (mtk_crtc->pending_planes) { 402 for (i = 0; i < mtk_crtc->layer_nr; i++) { 403 struct drm_plane *plane = &mtk_crtc->planes[i]; 404 struct mtk_plane_state *plane_state; 405 406 plane_state = to_mtk_plane_state(plane->state); 407 408 if (!plane_state->pending.config) 409 continue; 410 411 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 412 &local_layer); 413 414 if (comp) 415 mtk_ddp_comp_layer_config(comp, local_layer, 416 plane_state, 417 cmdq_handle); 418 plane_state->pending.config = false; 419 } 420 mtk_crtc->pending_planes = false; 421 } 422 423 if (mtk_crtc->pending_async_planes) { 424 for (i = 0; i < mtk_crtc->layer_nr; i++) { 425 struct drm_plane *plane = &mtk_crtc->planes[i]; 426 struct mtk_plane_state *plane_state; 427 428 plane_state = to_mtk_plane_state(plane->state); 429 430 if (!plane_state->pending.async_config) 431 continue; 432 433 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 434 &local_layer); 435 436 if (comp) 437 mtk_ddp_comp_layer_config(comp, local_layer, 438 plane_state, 439 cmdq_handle); 440 plane_state->pending.async_config = false; 441 } 442 mtk_crtc->pending_async_planes = false; 443 } 444} 445 446static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 447{ 448#if IS_REACHABLE(CONFIG_MTK_CMDQ) 449 struct cmdq_pkt *cmdq_handle; 450#endif 451 struct drm_crtc *crtc = &mtk_crtc->base; 452 struct mtk_drm_private *priv = crtc->dev->dev_private; 453 unsigned int pending_planes = 0, pending_async_planes = 0; 454 int i; 455 456 mutex_lock(&mtk_crtc->hw_lock); 457 for (i = 0; i < mtk_crtc->layer_nr; i++) { 458 struct drm_plane *plane = &mtk_crtc->planes[i]; 459 struct mtk_plane_state *plane_state; 460 461 plane_state = to_mtk_plane_state(plane->state); 462 if (plane_state->pending.dirty) { 463 plane_state->pending.config = true; 464 plane_state->pending.dirty = false; 465 pending_planes |= BIT(i); 466 } else if (plane_state->pending.async_dirty) { 467 plane_state->pending.async_config = true; 468 plane_state->pending.async_dirty = false; 469 pending_async_planes |= BIT(i); 470 } 471 } 472 if (pending_planes) 473 mtk_crtc->pending_planes = true; 474 if (pending_async_planes) 475 mtk_crtc->pending_async_planes = true; 476 477 if (priv->data->shadow_register) { 478 mtk_disp_mutex_acquire(mtk_crtc->mutex); 479 mtk_crtc_ddp_config(crtc, NULL); 480 mtk_disp_mutex_release(mtk_crtc->mutex); 481 } 482#if IS_REACHABLE(CONFIG_MTK_CMDQ) 483 if (mtk_crtc->cmdq_client) { 484 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 485 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 486 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 487 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); 488 mtk_crtc_ddp_config(crtc, cmdq_handle); 489 cmdq_pkt_finalize(cmdq_handle); 490 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 491 } 492#endif 493 mutex_unlock(&mtk_crtc->hw_lock); 494} 495 496int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 497 struct mtk_plane_state *state) 498{ 499 unsigned int local_layer; 500 struct mtk_ddp_comp *comp; 501 502 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 503 if (comp) 504 return mtk_ddp_comp_layer_check(comp, local_layer, state); 505 return 0; 506} 507 508void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 509 struct drm_plane_state *new_state) 510{ 511 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 512 const struct drm_plane_helper_funcs *plane_helper_funcs = 513 plane->helper_private; 514 515 if (!mtk_crtc->enabled) 516 return; 517 518 plane_helper_funcs->atomic_update(plane, new_state); 519 mtk_drm_crtc_hw_config(mtk_crtc); 520} 521 522static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 523 struct drm_crtc_state *old_state) 524{ 525 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 526 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 527 int ret; 528 529 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 530 531 ret = mtk_smi_larb_get(comp->larb_dev); 532 if (ret) { 533 DRM_ERROR("Failed to get larb: %d\n", ret); 534 return; 535 } 536 537 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 538 if (ret) { 539 mtk_smi_larb_put(comp->larb_dev); 540 return; 541 } 542 543 drm_crtc_vblank_on(crtc); 544 mtk_crtc->enabled = true; 545} 546 547static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 548 struct drm_crtc_state *old_state) 549{ 550 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 551 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 552 int i; 553 554 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 555 if (!mtk_crtc->enabled) 556 return; 557 558 /* Set all pending plane state to disabled */ 559 for (i = 0; i < mtk_crtc->layer_nr; i++) { 560 struct drm_plane *plane = &mtk_crtc->planes[i]; 561 struct mtk_plane_state *plane_state; 562 563 plane_state = to_mtk_plane_state(plane->state); 564 plane_state->pending.enable = false; 565 plane_state->pending.config = true; 566 } 567 mtk_crtc->pending_planes = true; 568 569 mtk_drm_crtc_hw_config(mtk_crtc); 570 /* Wait for planes to be disabled */ 571 drm_crtc_wait_one_vblank(crtc); 572 573 drm_crtc_vblank_off(crtc); 574 mtk_crtc_ddp_hw_fini(mtk_crtc); 575 mtk_smi_larb_put(comp->larb_dev); 576 577 mtk_crtc->enabled = false; 578} 579 580static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 581 struct drm_crtc_state *old_crtc_state) 582{ 583 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 584 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 585 unsigned long flags; 586 587 if (mtk_crtc->event && state->base.event) 588 DRM_ERROR("new event while there is still a pending event\n"); 589 590 if (state->base.event) { 591 state->base.event->pipe = drm_crtc_index(crtc); 592 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 593 594 spin_lock_irqsave(&crtc->dev->event_lock, flags); 595 mtk_crtc->event = state->base.event; 596 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 597 598 state->base.event = NULL; 599 } 600} 601 602static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 603 struct drm_crtc_state *old_crtc_state) 604{ 605 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 606 int i; 607 608 if (mtk_crtc->event) 609 mtk_crtc->pending_needs_vblank = true; 610 if (crtc->state->color_mgmt_changed) 611 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 612 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 613 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 614 } 615 mtk_drm_crtc_hw_config(mtk_crtc); 616} 617 618static const struct drm_crtc_funcs mtk_crtc_funcs = { 619 .set_config = drm_atomic_helper_set_config, 620 .page_flip = drm_atomic_helper_page_flip, 621 .destroy = mtk_drm_crtc_destroy, 622 .reset = mtk_drm_crtc_reset, 623 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 624 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 625 .gamma_set = drm_atomic_helper_legacy_gamma_set, 626 .enable_vblank = mtk_drm_crtc_enable_vblank, 627 .disable_vblank = mtk_drm_crtc_disable_vblank, 628}; 629 630static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 631 .mode_fixup = mtk_drm_crtc_mode_fixup, 632 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 633 .atomic_begin = mtk_drm_crtc_atomic_begin, 634 .atomic_flush = mtk_drm_crtc_atomic_flush, 635 .atomic_enable = mtk_drm_crtc_atomic_enable, 636 .atomic_disable = mtk_drm_crtc_atomic_disable, 637}; 638 639static int mtk_drm_crtc_init(struct drm_device *drm, 640 struct mtk_drm_crtc *mtk_crtc, 641 unsigned int pipe) 642{ 643 struct drm_plane *primary = NULL; 644 struct drm_plane *cursor = NULL; 645 int i, ret; 646 647 for (i = 0; i < mtk_crtc->layer_nr; i++) { 648 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 649 primary = &mtk_crtc->planes[i]; 650 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 651 cursor = &mtk_crtc->planes[i]; 652 } 653 654 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 655 &mtk_crtc_funcs, NULL); 656 if (ret) 657 goto err_cleanup_crtc; 658 659 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 660 661 return 0; 662 663err_cleanup_crtc: 664 drm_crtc_cleanup(&mtk_crtc->base); 665 return ret; 666} 667 668void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 669{ 670 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 671 struct mtk_drm_private *priv = crtc->dev->dev_private; 672 673#if IS_REACHABLE(CONFIG_MTK_CMDQ) 674 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 675#else 676 if (!priv->data->shadow_register) 677#endif 678 mtk_crtc_ddp_config(crtc, NULL); 679 680 mtk_drm_finish_page_flip(mtk_crtc); 681} 682 683static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 684 int comp_idx) 685{ 686 struct mtk_ddp_comp *comp; 687 688 if (comp_idx > 1) 689 return 0; 690 691 comp = mtk_crtc->ddp_comp[comp_idx]; 692 if (!comp->funcs) 693 return 0; 694 695 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 696 return 0; 697 698 return mtk_ddp_comp_layer_nr(comp); 699} 700 701static inline 702enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 703 unsigned int num_planes) 704{ 705 if (plane_idx == 0) 706 return DRM_PLANE_TYPE_PRIMARY; 707 else if (plane_idx == (num_planes - 1)) 708 return DRM_PLANE_TYPE_CURSOR; 709 else 710 return DRM_PLANE_TYPE_OVERLAY; 711 712} 713 714static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 715 struct mtk_drm_crtc *mtk_crtc, 716 int comp_idx, int pipe) 717{ 718 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 719 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 720 int i, ret; 721 722 for (i = 0; i < num_planes; i++) { 723 ret = mtk_plane_init(drm_dev, 724 &mtk_crtc->planes[mtk_crtc->layer_nr], 725 BIT(pipe), 726 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 727 num_planes), 728 mtk_ddp_comp_supported_rotations(comp)); 729 if (ret) 730 return ret; 731 732 mtk_crtc->layer_nr++; 733 } 734 return 0; 735} 736 737int mtk_drm_crtc_create(struct drm_device *drm_dev, 738 const enum mtk_ddp_comp_id *path, unsigned int path_len) 739{ 740 struct mtk_drm_private *priv = drm_dev->dev_private; 741 struct device *dev = drm_dev->dev; 742 struct mtk_drm_crtc *mtk_crtc; 743 unsigned int num_comp_planes = 0; 744 int pipe = priv->num_pipes; 745 int ret; 746 int i; 747 bool has_ctm = false; 748 uint gamma_lut_size = 0; 749 750 if (!path) 751 return 0; 752 753 for (i = 0; i < path_len; i++) { 754 enum mtk_ddp_comp_id comp_id = path[i]; 755 struct device_node *node; 756 757 node = priv->comp_node[comp_id]; 758 if (!node) { 759 dev_info(dev, 760 "Not creating crtc %d because component %d is disabled or missing\n", 761 pipe, comp_id); 762 return 0; 763 } 764 } 765 766 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 767 if (!mtk_crtc) 768 return -ENOMEM; 769 770 mtk_crtc->mmsys_dev = priv->mmsys_dev; 771 mtk_crtc->ddp_comp_nr = path_len; 772 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 773 sizeof(*mtk_crtc->ddp_comp), 774 GFP_KERNEL); 775 if (!mtk_crtc->ddp_comp) 776 return -ENOMEM; 777 778 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 779 if (IS_ERR(mtk_crtc->mutex)) { 780 ret = PTR_ERR(mtk_crtc->mutex); 781 dev_err(dev, "Failed to get mutex: %d\n", ret); 782 return ret; 783 } 784 785 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 786 enum mtk_ddp_comp_id comp_id = path[i]; 787 struct mtk_ddp_comp *comp; 788 struct device_node *node; 789 790 node = priv->comp_node[comp_id]; 791 comp = priv->ddp_comp[comp_id]; 792 if (!comp) { 793 dev_err(dev, "Component %pOF not initialized\n", node); 794 ret = -ENODEV; 795 return ret; 796 } 797 798 mtk_crtc->ddp_comp[i] = comp; 799 800 if (comp->funcs) { 801 if (comp->funcs->gamma_set) 802 gamma_lut_size = MTK_LUT_SIZE; 803 804 if (comp->funcs->ctm_set) 805 has_ctm = true; 806 } 807 } 808 809 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 810 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 811 812 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 813 sizeof(struct drm_plane), GFP_KERNEL); 814 if (!mtk_crtc->planes) 815 return -ENOMEM; 816 817 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 818 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 819 pipe); 820 if (ret) 821 return ret; 822 } 823 824 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 825 if (ret < 0) 826 return ret; 827 828 if (gamma_lut_size) 829 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 830 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 831 priv->num_pipes++; 832 mutex_init(&mtk_crtc->hw_lock); 833 834#if IS_REACHABLE(CONFIG_MTK_CMDQ) 835 mtk_crtc->cmdq_client = 836 cmdq_mbox_create(mtk_crtc->mmsys_dev, 837 drm_crtc_index(&mtk_crtc->base), 838 2000); 839 if (IS_ERR(mtk_crtc->cmdq_client)) { 840 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 841 drm_crtc_index(&mtk_crtc->base)); 842 mtk_crtc->cmdq_client = NULL; 843 } 844 845 if (mtk_crtc->cmdq_client) { 846 ret = of_property_read_u32_index(priv->mutex_node, 847 "mediatek,gce-events", 848 drm_crtc_index(&mtk_crtc->base), 849 &mtk_crtc->cmdq_event); 850 if (ret) { 851 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 852 drm_crtc_index(&mtk_crtc->base)); 853 cmdq_mbox_destroy(mtk_crtc->cmdq_client); 854 mtk_crtc->cmdq_client = NULL; 855 } 856 } 857#endif 858 return 0; 859} 860