1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Linus Walleij <linus.walleij@linaro.org> 4 * Parts of this file were based on the MCDE driver by Marcus Lorentzon 5 * (C) ST-Ericsson SA 2013 6 */ 7#include <linux/clk.h> 8#include <linux/delay.h> 9#include <linux/dma-buf.h> 10#include <linux/regulator/consumer.h> 11 12#include <drm/drm_device.h> 13#include <drm/drm_fb_cma_helper.h> 14#include <drm/drm_fourcc.h> 15#include <drm/drm_gem_cma_helper.h> 16#include <drm/drm_gem_framebuffer_helper.h> 17#include <drm/drm_mipi_dsi.h> 18#include <drm/drm_simple_kms_helper.h> 19#include <drm/drm_vblank.h> 20#include <video/mipi_display.h> 21 22#include "mcde_drm.h" 23#include "mcde_display_regs.h" 24 25enum mcde_fifo { 26 MCDE_FIFO_A, 27 MCDE_FIFO_B, 28 /* TODO: implement FIFO C0 and FIFO C1 */ 29}; 30 31enum mcde_channel { 32 MCDE_CHANNEL_0 = 0, 33 MCDE_CHANNEL_1, 34 MCDE_CHANNEL_2, 35 MCDE_CHANNEL_3, 36}; 37 38enum mcde_extsrc { 39 MCDE_EXTSRC_0 = 0, 40 MCDE_EXTSRC_1, 41 MCDE_EXTSRC_2, 42 MCDE_EXTSRC_3, 43 MCDE_EXTSRC_4, 44 MCDE_EXTSRC_5, 45 MCDE_EXTSRC_6, 46 MCDE_EXTSRC_7, 47 MCDE_EXTSRC_8, 48 MCDE_EXTSRC_9, 49}; 50 51enum mcde_overlay { 52 MCDE_OVERLAY_0 = 0, 53 MCDE_OVERLAY_1, 54 MCDE_OVERLAY_2, 55 MCDE_OVERLAY_3, 56 MCDE_OVERLAY_4, 57 MCDE_OVERLAY_5, 58}; 59 60enum mcde_dsi_formatter { 61 MCDE_DSI_FORMATTER_0 = 0, 62 MCDE_DSI_FORMATTER_1, 63 MCDE_DSI_FORMATTER_2, 64}; 65 66void mcde_display_irq(struct mcde *mcde) 67{ 68 u32 mispp, misovl, mischnl; 69 bool vblank = false; 70 71 /* Handle display IRQs */ 72 mispp = readl(mcde->regs + MCDE_MISPP); 73 misovl = readl(mcde->regs + MCDE_MISOVL); 74 mischnl = readl(mcde->regs + MCDE_MISCHNL); 75 76 /* 77 * Handle IRQs from the DSI link. All IRQs from the DSI links 78 * are just latched onto the MCDE IRQ line, so we need to traverse 79 * any active DSI masters and check if an IRQ is originating from 80 * them. 81 * 82 * TODO: Currently only one DSI link is supported. 83 */ 84 if (mcde_dsi_irq(mcde->mdsi)) { 85 u32 val; 86 87 /* 88 * In oneshot mode we do not send continuous updates 89 * to the display, instead we only push out updates when 90 * the update function is called, then we disable the 91 * flow on the channel once we get the TE IRQ. 92 */ 93 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { 94 spin_lock(&mcde->flow_lock); 95 if (--mcde->flow_active == 0) { 96 dev_dbg(mcde->dev, "TE0 IRQ\n"); 97 /* Disable FIFO A flow */ 98 val = readl(mcde->regs + MCDE_CRA0); 99 val &= ~MCDE_CRX0_FLOEN; 100 writel(val, mcde->regs + MCDE_CRA0); 101 } 102 spin_unlock(&mcde->flow_lock); 103 } 104 } 105 106 /* Vblank from one of the channels */ 107 if (mispp & MCDE_PP_VCMPA) { 108 dev_dbg(mcde->dev, "chnl A vblank IRQ\n"); 109 vblank = true; 110 } 111 if (mispp & MCDE_PP_VCMPB) { 112 dev_dbg(mcde->dev, "chnl B vblank IRQ\n"); 113 vblank = true; 114 } 115 if (mispp & MCDE_PP_VCMPC0) 116 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n"); 117 if (mispp & MCDE_PP_VCMPC1) 118 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n"); 119 if (mispp & MCDE_PP_VSCC0) 120 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n"); 121 if (mispp & MCDE_PP_VSCC1) 122 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n"); 123 writel(mispp, mcde->regs + MCDE_RISPP); 124 125 if (vblank) 126 drm_crtc_handle_vblank(&mcde->pipe.crtc); 127 128 if (misovl) 129 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl); 130 writel(misovl, mcde->regs + MCDE_RISOVL); 131 132 if (mischnl) 133 dev_info(mcde->dev, "some stray channel error IRQ %08x\n", 134 mischnl); 135 writel(mischnl, mcde->regs + MCDE_RISCHNL); 136} 137 138void mcde_display_disable_irqs(struct mcde *mcde) 139{ 140 /* Disable all IRQs */ 141 writel(0, mcde->regs + MCDE_IMSCPP); 142 writel(0, mcde->regs + MCDE_IMSCOVL); 143 writel(0, mcde->regs + MCDE_IMSCCHNL); 144 145 /* Clear any pending IRQs */ 146 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); 147 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL); 148 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL); 149} 150 151static int mcde_display_check(struct drm_simple_display_pipe *pipe, 152 struct drm_plane_state *pstate, 153 struct drm_crtc_state *cstate) 154{ 155 const struct drm_display_mode *mode = &cstate->mode; 156 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 157 struct drm_framebuffer *fb = pstate->fb; 158 159 if (fb) { 160 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0); 161 162 /* FB base address must be dword aligned. */ 163 if (offset & 3) { 164 DRM_DEBUG_KMS("FB not 32-bit aligned\n"); 165 return -EINVAL; 166 } 167 168 /* 169 * There's no pitch register, the mode's hdisplay 170 * controls this. 171 */ 172 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { 173 DRM_DEBUG_KMS("can't handle pitches\n"); 174 return -EINVAL; 175 } 176 177 /* 178 * We can't change the FB format in a flicker-free 179 * manner (and only update it during CRTC enable). 180 */ 181 if (old_fb && old_fb->format != fb->format) 182 cstate->mode_changed = true; 183 } 184 185 return 0; 186} 187 188static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src, 189 u32 format) 190{ 191 u32 val; 192 u32 conf; 193 u32 cr; 194 195 switch (src) { 196 case MCDE_EXTSRC_0: 197 conf = MCDE_EXTSRC0CONF; 198 cr = MCDE_EXTSRC0CR; 199 break; 200 case MCDE_EXTSRC_1: 201 conf = MCDE_EXTSRC1CONF; 202 cr = MCDE_EXTSRC1CR; 203 break; 204 case MCDE_EXTSRC_2: 205 conf = MCDE_EXTSRC2CONF; 206 cr = MCDE_EXTSRC2CR; 207 break; 208 case MCDE_EXTSRC_3: 209 conf = MCDE_EXTSRC3CONF; 210 cr = MCDE_EXTSRC3CR; 211 break; 212 case MCDE_EXTSRC_4: 213 conf = MCDE_EXTSRC4CONF; 214 cr = MCDE_EXTSRC4CR; 215 break; 216 case MCDE_EXTSRC_5: 217 conf = MCDE_EXTSRC5CONF; 218 cr = MCDE_EXTSRC5CR; 219 break; 220 case MCDE_EXTSRC_6: 221 conf = MCDE_EXTSRC6CONF; 222 cr = MCDE_EXTSRC6CR; 223 break; 224 case MCDE_EXTSRC_7: 225 conf = MCDE_EXTSRC7CONF; 226 cr = MCDE_EXTSRC7CR; 227 break; 228 case MCDE_EXTSRC_8: 229 conf = MCDE_EXTSRC8CONF; 230 cr = MCDE_EXTSRC8CR; 231 break; 232 case MCDE_EXTSRC_9: 233 conf = MCDE_EXTSRC9CONF; 234 cr = MCDE_EXTSRC9CR; 235 break; 236 } 237 238 /* 239 * Configure external source 0 one buffer (buffer 0) 240 * primary overlay ID 0. 241 * From mcde_hw.c ovly_update_registers() in the vendor tree 242 */ 243 val = 0 << MCDE_EXTSRCXCONF_BUF_ID_SHIFT; 244 val |= 1 << MCDE_EXTSRCXCONF_BUF_NB_SHIFT; 245 val |= 0 << MCDE_EXTSRCXCONF_PRI_OVLID_SHIFT; 246 /* 247 * MCDE has inverse semantics from DRM on RBG/BGR which is why 248 * all the modes are inversed here. 249 */ 250 switch (format) { 251 case DRM_FORMAT_ARGB8888: 252 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << 253 MCDE_EXTSRCXCONF_BPP_SHIFT; 254 val |= MCDE_EXTSRCXCONF_BGR; 255 break; 256 case DRM_FORMAT_ABGR8888: 257 val |= MCDE_EXTSRCXCONF_BPP_ARGB8888 << 258 MCDE_EXTSRCXCONF_BPP_SHIFT; 259 break; 260 case DRM_FORMAT_XRGB8888: 261 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << 262 MCDE_EXTSRCXCONF_BPP_SHIFT; 263 val |= MCDE_EXTSRCXCONF_BGR; 264 break; 265 case DRM_FORMAT_XBGR8888: 266 val |= MCDE_EXTSRCXCONF_BPP_XRGB8888 << 267 MCDE_EXTSRCXCONF_BPP_SHIFT; 268 break; 269 case DRM_FORMAT_RGB888: 270 val |= MCDE_EXTSRCXCONF_BPP_RGB888 << 271 MCDE_EXTSRCXCONF_BPP_SHIFT; 272 val |= MCDE_EXTSRCXCONF_BGR; 273 break; 274 case DRM_FORMAT_BGR888: 275 val |= MCDE_EXTSRCXCONF_BPP_RGB888 << 276 MCDE_EXTSRCXCONF_BPP_SHIFT; 277 break; 278 case DRM_FORMAT_ARGB4444: 279 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << 280 MCDE_EXTSRCXCONF_BPP_SHIFT; 281 val |= MCDE_EXTSRCXCONF_BGR; 282 break; 283 case DRM_FORMAT_ABGR4444: 284 val |= MCDE_EXTSRCXCONF_BPP_ARGB4444 << 285 MCDE_EXTSRCXCONF_BPP_SHIFT; 286 break; 287 case DRM_FORMAT_XRGB4444: 288 val |= MCDE_EXTSRCXCONF_BPP_RGB444 << 289 MCDE_EXTSRCXCONF_BPP_SHIFT; 290 val |= MCDE_EXTSRCXCONF_BGR; 291 break; 292 case DRM_FORMAT_XBGR4444: 293 val |= MCDE_EXTSRCXCONF_BPP_RGB444 << 294 MCDE_EXTSRCXCONF_BPP_SHIFT; 295 break; 296 case DRM_FORMAT_XRGB1555: 297 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << 298 MCDE_EXTSRCXCONF_BPP_SHIFT; 299 val |= MCDE_EXTSRCXCONF_BGR; 300 break; 301 case DRM_FORMAT_XBGR1555: 302 val |= MCDE_EXTSRCXCONF_BPP_IRGB1555 << 303 MCDE_EXTSRCXCONF_BPP_SHIFT; 304 break; 305 case DRM_FORMAT_RGB565: 306 val |= MCDE_EXTSRCXCONF_BPP_RGB565 << 307 MCDE_EXTSRCXCONF_BPP_SHIFT; 308 val |= MCDE_EXTSRCXCONF_BGR; 309 break; 310 case DRM_FORMAT_BGR565: 311 val |= MCDE_EXTSRCXCONF_BPP_RGB565 << 312 MCDE_EXTSRCXCONF_BPP_SHIFT; 313 break; 314 case DRM_FORMAT_YUV422: 315 val |= MCDE_EXTSRCXCONF_BPP_YCBCR422 << 316 MCDE_EXTSRCXCONF_BPP_SHIFT; 317 break; 318 default: 319 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", 320 format); 321 return -EINVAL; 322 } 323 writel(val, mcde->regs + conf); 324 325 /* Software select, primary */ 326 val = MCDE_EXTSRCXCR_SEL_MOD_SOFTWARE_SEL; 327 val |= MCDE_EXTSRCXCR_MULTIOVL_CTRL_PRIMARY; 328 writel(val, mcde->regs + cr); 329 330 return 0; 331} 332 333static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, 334 enum mcde_extsrc src, 335 enum mcde_channel ch, 336 const struct drm_display_mode *mode, 337 u32 format, int cpp) 338{ 339 u32 val; 340 u32 conf1; 341 u32 conf2; 342 u32 crop; 343 u32 ljinc; 344 u32 cr; 345 u32 comp; 346 u32 pixel_fetcher_watermark; 347 348 switch (ovl) { 349 case MCDE_OVERLAY_0: 350 conf1 = MCDE_OVL0CONF; 351 conf2 = MCDE_OVL0CONF2; 352 crop = MCDE_OVL0CROP; 353 ljinc = MCDE_OVL0LJINC; 354 cr = MCDE_OVL0CR; 355 comp = MCDE_OVL0COMP; 356 break; 357 case MCDE_OVERLAY_1: 358 conf1 = MCDE_OVL1CONF; 359 conf2 = MCDE_OVL1CONF2; 360 crop = MCDE_OVL1CROP; 361 ljinc = MCDE_OVL1LJINC; 362 cr = MCDE_OVL1CR; 363 comp = MCDE_OVL1COMP; 364 break; 365 case MCDE_OVERLAY_2: 366 conf1 = MCDE_OVL2CONF; 367 conf2 = MCDE_OVL2CONF2; 368 crop = MCDE_OVL2CROP; 369 ljinc = MCDE_OVL2LJINC; 370 cr = MCDE_OVL2CR; 371 comp = MCDE_OVL2COMP; 372 break; 373 case MCDE_OVERLAY_3: 374 conf1 = MCDE_OVL3CONF; 375 conf2 = MCDE_OVL3CONF2; 376 crop = MCDE_OVL3CROP; 377 ljinc = MCDE_OVL3LJINC; 378 cr = MCDE_OVL3CR; 379 comp = MCDE_OVL3COMP; 380 break; 381 case MCDE_OVERLAY_4: 382 conf1 = MCDE_OVL4CONF; 383 conf2 = MCDE_OVL4CONF2; 384 crop = MCDE_OVL4CROP; 385 ljinc = MCDE_OVL4LJINC; 386 cr = MCDE_OVL4CR; 387 comp = MCDE_OVL4COMP; 388 break; 389 case MCDE_OVERLAY_5: 390 conf1 = MCDE_OVL5CONF; 391 conf2 = MCDE_OVL5CONF2; 392 crop = MCDE_OVL5CROP; 393 ljinc = MCDE_OVL5LJINC; 394 cr = MCDE_OVL5CR; 395 comp = MCDE_OVL5COMP; 396 break; 397 } 398 399 val = mode->hdisplay << MCDE_OVLXCONF_PPL_SHIFT; 400 val |= mode->vdisplay << MCDE_OVLXCONF_LPF_SHIFT; 401 /* Use external source 0 that we just configured */ 402 val |= src << MCDE_OVLXCONF_EXTSRC_ID_SHIFT; 403 writel(val, mcde->regs + conf1); 404 405 val = MCDE_OVLXCONF2_BP_PER_PIXEL_ALPHA; 406 val |= 0xff << MCDE_OVLXCONF2_ALPHAVALUE_SHIFT; 407 /* OPQ: overlay is opaque */ 408 switch (format) { 409 case DRM_FORMAT_ARGB8888: 410 case DRM_FORMAT_ABGR8888: 411 case DRM_FORMAT_ARGB4444: 412 case DRM_FORMAT_ABGR4444: 413 case DRM_FORMAT_XRGB1555: 414 case DRM_FORMAT_XBGR1555: 415 /* No OPQ */ 416 break; 417 case DRM_FORMAT_XRGB8888: 418 case DRM_FORMAT_XBGR8888: 419 case DRM_FORMAT_RGB888: 420 case DRM_FORMAT_BGR888: 421 case DRM_FORMAT_RGB565: 422 case DRM_FORMAT_BGR565: 423 case DRM_FORMAT_YUV422: 424 val |= MCDE_OVLXCONF2_OPQ; 425 break; 426 default: 427 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", 428 format); 429 break; 430 } 431 432 /* 433 * Pixel fetch watermark level is max 0x1FFF pixels. 434 * Two basic rules should be followed: 435 * 1. The value should be at least 256 bits. 436 * 2. The sum of all active overlays pixelfetch watermark level 437 * multiplied with bits per pixel, should be lower than the 438 * size of input_fifo_size in bits. 439 * 3. The value should be a multiple of a line (256 bits). 440 */ 441 switch (cpp) { 442 case 2: 443 pixel_fetcher_watermark = 128; 444 break; 445 case 3: 446 pixel_fetcher_watermark = 96; 447 break; 448 case 4: 449 pixel_fetcher_watermark = 48; 450 break; 451 default: 452 pixel_fetcher_watermark = 48; 453 break; 454 } 455 dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n", 456 pixel_fetcher_watermark); 457 val |= pixel_fetcher_watermark << MCDE_OVLXCONF2_PIXELFETCHERWATERMARKLEVEL_SHIFT; 458 writel(val, mcde->regs + conf2); 459 460 /* Number of bytes to fetch per line */ 461 writel(mcde->stride, mcde->regs + ljinc); 462 /* No cropping */ 463 writel(0, mcde->regs + crop); 464 465 /* Set up overlay control register */ 466 val = MCDE_OVLXCR_OVLEN; 467 val |= MCDE_OVLXCR_COLCCTRL_DISABLED; 468 val |= MCDE_OVLXCR_BURSTSIZE_8W << 469 MCDE_OVLXCR_BURSTSIZE_SHIFT; 470 val |= MCDE_OVLXCR_MAXOUTSTANDING_8_REQ << 471 MCDE_OVLXCR_MAXOUTSTANDING_SHIFT; 472 /* Not using rotation but set it up anyways */ 473 val |= MCDE_OVLXCR_ROTBURSTSIZE_8W << 474 MCDE_OVLXCR_ROTBURSTSIZE_SHIFT; 475 writel(val, mcde->regs + cr); 476 477 /* 478 * Set up the overlay compositor to route the overlay out to 479 * the desired channel 480 */ 481 val = ch << MCDE_OVLXCOMP_CH_ID_SHIFT; 482 writel(val, mcde->regs + comp); 483} 484 485static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch, 486 enum mcde_fifo fifo, 487 const struct drm_display_mode *mode) 488{ 489 u32 val; 490 u32 conf; 491 u32 sync; 492 u32 stat; 493 u32 bgcol; 494 u32 mux; 495 496 switch (ch) { 497 case MCDE_CHANNEL_0: 498 conf = MCDE_CHNL0CONF; 499 sync = MCDE_CHNL0SYNCHMOD; 500 stat = MCDE_CHNL0STAT; 501 bgcol = MCDE_CHNL0BCKGNDCOL; 502 mux = MCDE_CHNL0MUXING; 503 break; 504 case MCDE_CHANNEL_1: 505 conf = MCDE_CHNL1CONF; 506 sync = MCDE_CHNL1SYNCHMOD; 507 stat = MCDE_CHNL1STAT; 508 bgcol = MCDE_CHNL1BCKGNDCOL; 509 mux = MCDE_CHNL1MUXING; 510 break; 511 case MCDE_CHANNEL_2: 512 conf = MCDE_CHNL2CONF; 513 sync = MCDE_CHNL2SYNCHMOD; 514 stat = MCDE_CHNL2STAT; 515 bgcol = MCDE_CHNL2BCKGNDCOL; 516 mux = MCDE_CHNL2MUXING; 517 break; 518 case MCDE_CHANNEL_3: 519 conf = MCDE_CHNL3CONF; 520 sync = MCDE_CHNL3SYNCHMOD; 521 stat = MCDE_CHNL3STAT; 522 bgcol = MCDE_CHNL3BCKGNDCOL; 523 mux = MCDE_CHNL3MUXING; 524 return; 525 } 526 527 /* Set up channel 0 sync (based on chnl_update_registers()) */ 528 switch (mcde->flow_mode) { 529 case MCDE_COMMAND_ONESHOT_FLOW: 530 /* Oneshot is achieved with software sync */ 531 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SOFTWARE 532 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT; 533 break; 534 case MCDE_COMMAND_TE_FLOW: 535 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 536 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT; 537 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 538 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT; 539 break; 540 case MCDE_COMMAND_BTA_TE_FLOW: 541 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 542 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT; 543 /* 544 * TODO: 545 * The vendor driver uses the formatter as sync source 546 * for BTA TE mode. Test to use TE if you have a panel 547 * that uses this mode. 548 */ 549 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER 550 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT; 551 break; 552 case MCDE_VIDEO_TE_FLOW: 553 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 554 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT; 555 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_TE0 556 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT; 557 break; 558 case MCDE_VIDEO_FORMATTER_FLOW: 559 val = MCDE_CHNLXSYNCHMOD_SRC_SYNCH_HARDWARE 560 << MCDE_CHNLXSYNCHMOD_SRC_SYNCH_SHIFT; 561 val |= MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_FORMATTER 562 << MCDE_CHNLXSYNCHMOD_OUT_SYNCH_SRC_SHIFT; 563 break; 564 default: 565 dev_err(mcde->dev, "unknown flow mode %d\n", 566 mcde->flow_mode); 567 break; 568 } 569 570 writel(val, mcde->regs + sync); 571 572 /* Set up pixels per line and lines per frame */ 573 val = (mode->hdisplay - 1) << MCDE_CHNLXCONF_PPL_SHIFT; 574 val |= (mode->vdisplay - 1) << MCDE_CHNLXCONF_LPF_SHIFT; 575 writel(val, mcde->regs + conf); 576 577 /* 578 * Normalize color conversion: 579 * black background, OLED conversion disable on channel 580 */ 581 val = MCDE_CHNLXSTAT_CHNLBLBCKGND_EN | 582 MCDE_CHNLXSTAT_CHNLRD; 583 writel(val, mcde->regs + stat); 584 writel(0, mcde->regs + bgcol); 585 586 /* Set up muxing: connect the channel to the desired FIFO */ 587 switch (fifo) { 588 case MCDE_FIFO_A: 589 writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_A, 590 mcde->regs + mux); 591 break; 592 case MCDE_FIFO_B: 593 writel(MCDE_CHNLXMUXING_FIFO_ID_FIFO_B, 594 mcde->regs + mux); 595 break; 596 } 597} 598 599static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo, 600 enum mcde_dsi_formatter fmt, 601 int fifo_wtrmrk) 602{ 603 u32 val; 604 u32 ctrl; 605 u32 cr0, cr1; 606 607 switch (fifo) { 608 case MCDE_FIFO_A: 609 ctrl = MCDE_CTRLA; 610 cr0 = MCDE_CRA0; 611 cr1 = MCDE_CRA1; 612 break; 613 case MCDE_FIFO_B: 614 ctrl = MCDE_CTRLB; 615 cr0 = MCDE_CRB0; 616 cr1 = MCDE_CRB1; 617 break; 618 } 619 620 val = fifo_wtrmrk << MCDE_CTRLX_FIFOWTRMRK_SHIFT; 621 /* We only support DSI formatting for now */ 622 val |= MCDE_CTRLX_FORMTYPE_DSI << 623 MCDE_CTRLX_FORMTYPE_SHIFT; 624 625 /* Select the formatter to use for this FIFO */ 626 val |= fmt << MCDE_CTRLX_FORMID_SHIFT; 627 writel(val, mcde->regs + ctrl); 628 629 /* Blend source with Alpha 0xff on FIFO */ 630 val = MCDE_CRX0_BLENDEN | 631 0xff << MCDE_CRX0_ALPHABLEND_SHIFT; 632 writel(val, mcde->regs + cr0); 633 634 /* Set-up from mcde_fmtr_dsi.c, fmtr_dsi_enable_video() */ 635 636 /* Use the MCDE clock for this FIFO */ 637 val = MCDE_CRX1_CLKSEL_MCDECLK << MCDE_CRX1_CLKSEL_SHIFT; 638 639 /* TODO: when adding DPI support add OUTBPP etc here */ 640 writel(val, mcde->regs + cr1); 641}; 642 643static void mcde_configure_dsi_formatter(struct mcde *mcde, 644 enum mcde_dsi_formatter fmt, 645 u32 formatter_frame, 646 int pkt_size) 647{ 648 u32 val; 649 u32 conf0; 650 u32 frame; 651 u32 pkt; 652 u32 sync; 653 u32 cmdw; 654 u32 delay0, delay1; 655 656 switch (fmt) { 657 case MCDE_DSI_FORMATTER_0: 658 conf0 = MCDE_DSIVID0CONF0; 659 frame = MCDE_DSIVID0FRAME; 660 pkt = MCDE_DSIVID0PKT; 661 sync = MCDE_DSIVID0SYNC; 662 cmdw = MCDE_DSIVID0CMDW; 663 delay0 = MCDE_DSIVID0DELAY0; 664 delay1 = MCDE_DSIVID0DELAY1; 665 break; 666 case MCDE_DSI_FORMATTER_1: 667 conf0 = MCDE_DSIVID1CONF0; 668 frame = MCDE_DSIVID1FRAME; 669 pkt = MCDE_DSIVID1PKT; 670 sync = MCDE_DSIVID1SYNC; 671 cmdw = MCDE_DSIVID1CMDW; 672 delay0 = MCDE_DSIVID1DELAY0; 673 delay1 = MCDE_DSIVID1DELAY1; 674 break; 675 case MCDE_DSI_FORMATTER_2: 676 conf0 = MCDE_DSIVID2CONF0; 677 frame = MCDE_DSIVID2FRAME; 678 pkt = MCDE_DSIVID2PKT; 679 sync = MCDE_DSIVID2SYNC; 680 cmdw = MCDE_DSIVID2CMDW; 681 delay0 = MCDE_DSIVID2DELAY0; 682 delay1 = MCDE_DSIVID2DELAY1; 683 break; 684 } 685 686 /* 687 * Enable formatter 688 * 8 bit commands and DCS commands (notgen = not generic) 689 */ 690 val = MCDE_DSICONF0_CMD8 | MCDE_DSICONF0_DCSVID_NOTGEN; 691 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) 692 val |= MCDE_DSICONF0_VID_MODE_VID; 693 switch (mcde->mdsi->format) { 694 case MIPI_DSI_FMT_RGB888: 695 val |= MCDE_DSICONF0_PACKING_RGB888 << 696 MCDE_DSICONF0_PACKING_SHIFT; 697 break; 698 case MIPI_DSI_FMT_RGB666: 699 val |= MCDE_DSICONF0_PACKING_RGB666 << 700 MCDE_DSICONF0_PACKING_SHIFT; 701 break; 702 case MIPI_DSI_FMT_RGB666_PACKED: 703 val |= MCDE_DSICONF0_PACKING_RGB666_PACKED << 704 MCDE_DSICONF0_PACKING_SHIFT; 705 break; 706 case MIPI_DSI_FMT_RGB565: 707 val |= MCDE_DSICONF0_PACKING_RGB565 << 708 MCDE_DSICONF0_PACKING_SHIFT; 709 break; 710 default: 711 dev_err(mcde->dev, "unknown DSI format\n"); 712 return; 713 } 714 writel(val, mcde->regs + conf0); 715 716 writel(formatter_frame, mcde->regs + frame); 717 writel(pkt_size, mcde->regs + pkt); 718 writel(0, mcde->regs + sync); 719 /* Define the MIPI command: we want to write into display memory */ 720 val = MIPI_DCS_WRITE_MEMORY_CONTINUE << 721 MCDE_DSIVIDXCMDW_CMDW_CONTINUE_SHIFT; 722 val |= MIPI_DCS_WRITE_MEMORY_START << 723 MCDE_DSIVIDXCMDW_CMDW_START_SHIFT; 724 writel(val, mcde->regs + cmdw); 725 726 /* 727 * FIXME: the vendor driver has some hack around this value in 728 * CMD mode with autotrig. 729 */ 730 writel(0, mcde->regs + delay0); 731 writel(0, mcde->regs + delay1); 732} 733 734static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo) 735{ 736 u32 val; 737 u32 cr; 738 739 switch (fifo) { 740 case MCDE_FIFO_A: 741 cr = MCDE_CRA0; 742 break; 743 case MCDE_FIFO_B: 744 cr = MCDE_CRB0; 745 break; 746 default: 747 dev_err(mcde->dev, "cannot enable FIFO %c\n", 748 'A' + fifo); 749 return; 750 } 751 752 spin_lock(&mcde->flow_lock); 753 val = readl(mcde->regs + cr); 754 val |= MCDE_CRX0_FLOEN; 755 writel(val, mcde->regs + cr); 756 mcde->flow_active++; 757 spin_unlock(&mcde->flow_lock); 758} 759 760static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo, 761 bool wait_for_drain) 762{ 763 int timeout = 100; 764 u32 val; 765 u32 cr; 766 767 switch (fifo) { 768 case MCDE_FIFO_A: 769 cr = MCDE_CRA0; 770 break; 771 case MCDE_FIFO_B: 772 cr = MCDE_CRB0; 773 break; 774 default: 775 dev_err(mcde->dev, "cannot disable FIFO %c\n", 776 'A' + fifo); 777 return; 778 } 779 780 spin_lock(&mcde->flow_lock); 781 val = readl(mcde->regs + cr); 782 val &= ~MCDE_CRX0_FLOEN; 783 writel(val, mcde->regs + cr); 784 mcde->flow_active = 0; 785 spin_unlock(&mcde->flow_lock); 786 787 if (!wait_for_drain) 788 return; 789 790 /* Check that we really drained and stopped the flow */ 791 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) { 792 usleep_range(1000, 1500); 793 if (!--timeout) { 794 dev_err(mcde->dev, 795 "FIFO timeout while clearing FIFO %c\n", 796 'A' + fifo); 797 return; 798 } 799 } 800} 801 802/* 803 * This drains a pipe i.e. a FIFO connected to a certain channel 804 */ 805static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo, 806 enum mcde_channel ch) 807{ 808 u32 val; 809 u32 ctrl; 810 u32 synsw; 811 812 switch (fifo) { 813 case MCDE_FIFO_A: 814 ctrl = MCDE_CTRLA; 815 break; 816 case MCDE_FIFO_B: 817 ctrl = MCDE_CTRLB; 818 break; 819 } 820 821 switch (ch) { 822 case MCDE_CHANNEL_0: 823 synsw = MCDE_CHNL0SYNCHSW; 824 break; 825 case MCDE_CHANNEL_1: 826 synsw = MCDE_CHNL1SYNCHSW; 827 break; 828 case MCDE_CHANNEL_2: 829 synsw = MCDE_CHNL2SYNCHSW; 830 break; 831 case MCDE_CHANNEL_3: 832 synsw = MCDE_CHNL3SYNCHSW; 833 return; 834 } 835 836 val = readl(mcde->regs + ctrl); 837 if (!(val & MCDE_CTRLX_FIFOEMPTY)) { 838 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n"); 839 /* Attempt to clear the FIFO */ 840 mcde_enable_fifo(mcde, fifo); 841 /* Trigger a software sync out on respective channel (0-3) */ 842 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw); 843 /* Disable FIFO A flow again */ 844 mcde_disable_fifo(mcde, fifo, true); 845 } 846} 847 848static int mcde_dsi_get_pkt_div(int ppl, int fifo_size) 849{ 850 /* 851 * DSI command mode line packets should be split into an even number of 852 * packets smaller than or equal to the fifo size. 853 */ 854 int div; 855 const int max_div = DIV_ROUND_UP(MCDE_MAX_WIDTH, fifo_size); 856 857 for (div = 1; div < max_div; div++) 858 if (ppl % div == 0 && ppl / div <= fifo_size) 859 return div; 860 return 1; 861} 862 863static void mcde_display_enable(struct drm_simple_display_pipe *pipe, 864 struct drm_crtc_state *cstate, 865 struct drm_plane_state *plane_state) 866{ 867 struct drm_crtc *crtc = &pipe->crtc; 868 struct drm_plane *plane = &pipe->plane; 869 struct drm_device *drm = crtc->dev; 870 struct mcde *mcde = to_mcde(drm); 871 const struct drm_display_mode *mode = &cstate->mode; 872 struct drm_framebuffer *fb = plane->state->fb; 873 u32 format = fb->format->format; 874 u32 formatter_ppl = mode->hdisplay; /* pixels per line */ 875 u32 formatter_lpf = mode->vdisplay; /* lines per frame */ 876 int pkt_size, fifo_wtrmrk; 877 int cpp = fb->format->cpp[0]; 878 int formatter_cpp; 879 struct drm_format_name_buf tmp; 880 u32 formatter_frame; 881 u32 pkt_div; 882 u32 val; 883 int ret; 884 885 /* This powers up the entire MCDE block and the DSI hardware */ 886 ret = regulator_enable(mcde->epod); 887 if (ret) { 888 dev_err(drm->dev, "can't re-enable EPOD regulator\n"); 889 return; 890 } 891 892 dev_info(drm->dev, "enable MCDE, %d x %d format %s\n", 893 mode->hdisplay, mode->vdisplay, 894 drm_get_format_name(format, &tmp)); 895 if (!mcde->mdsi) { 896 /* TODO: deal with this for non-DSI output */ 897 dev_err(drm->dev, "no DSI master attached!\n"); 898 return; 899 } 900 901 /* Set up the main control, watermark level at 7 */ 902 val = 7 << MCDE_CONF0_IFIFOCTRLWTRMRKLVL_SHIFT; 903 /* 24 bits DPI: connect LSB Ch B to D[0:7] */ 904 val |= 3 << MCDE_CONF0_OUTMUX0_SHIFT; 905 /* TV out: connect LSB Ch B to D[8:15] */ 906 val |= 3 << MCDE_CONF0_OUTMUX1_SHIFT; 907 /* Don't care about this muxing */ 908 val |= 0 << MCDE_CONF0_OUTMUX2_SHIFT; 909 /* 24 bits DPI: connect MID Ch B to D[24:31] */ 910 val |= 4 << MCDE_CONF0_OUTMUX3_SHIFT; 911 /* 5: 24 bits DPI: connect MSB Ch B to D[32:39] */ 912 val |= 5 << MCDE_CONF0_OUTMUX4_SHIFT; 913 /* Syncmux bits zero: DPI channel A and B on output pins A and B resp */ 914 writel(val, mcde->regs + MCDE_CONF0); 915 916 /* Clear any pending interrupts */ 917 mcde_display_disable_irqs(mcde); 918 writel(0, mcde->regs + MCDE_IMSCERR); 919 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR); 920 921 dev_info(drm->dev, "output in %s mode, format %dbpp\n", 922 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? 923 "VIDEO" : "CMD", 924 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format)); 925 formatter_cpp = 926 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8; 927 dev_info(drm->dev, "overlay CPP %d bytes, DSI CPP %d bytes\n", 928 cpp, 929 formatter_cpp); 930 931 /* Calculations from mcde_fmtr_dsi.c, fmtr_dsi_enable_video() */ 932 933 /* 934 * Set up FIFO A watermark level: 935 * 128 for LCD 32bpp video mode 936 * 48 for LCD 32bpp command mode 937 * 128 for LCD 16bpp video mode 938 * 64 for LCD 16bpp command mode 939 * 128 for HDMI 32bpp 940 * 192 for HDMI 16bpp 941 */ 942 fifo_wtrmrk = mode->hdisplay; 943 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 944 fifo_wtrmrk = min(fifo_wtrmrk, 128); 945 pkt_div = 1; 946 } else { 947 fifo_wtrmrk = min(fifo_wtrmrk, 48); 948 /* The FIFO is 640 entries deep on this v3 hardware */ 949 pkt_div = mcde_dsi_get_pkt_div(mode->hdisplay, 640); 950 } 951 dev_dbg(drm->dev, "FIFO watermark after flooring: %d bytes\n", 952 fifo_wtrmrk); 953 dev_dbg(drm->dev, "Packet divisor: %d bytes\n", pkt_div); 954 955 /* NOTE: pkt_div is 1 for video mode */ 956 pkt_size = (formatter_ppl * formatter_cpp) / pkt_div; 957 /* Commands CMD8 need one extra byte */ 958 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)) 959 pkt_size++; 960 961 dev_dbg(drm->dev, "DSI packet size: %d * %d bytes per line\n", 962 pkt_size, pkt_div); 963 dev_dbg(drm->dev, "Overlay frame size: %u bytes\n", 964 mode->hdisplay * mode->vdisplay * cpp); 965 mcde->stride = mode->hdisplay * cpp; 966 dev_dbg(drm->dev, "Overlay line stride: %u bytes\n", 967 mcde->stride); 968 /* NOTE: pkt_div is 1 for video mode */ 969 formatter_frame = pkt_size * pkt_div * formatter_lpf; 970 dev_dbg(drm->dev, "Formatter frame size: %u bytes\n", formatter_frame); 971 972 /* Drain the FIFO A + channel 0 pipe so we have a clean slate */ 973 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0); 974 975 /* 976 * We set up our display pipeline: 977 * EXTSRC 0 -> OVERLAY 0 -> CHANNEL 0 -> FIFO A -> DSI FORMATTER 0 978 * 979 * First configure the external source (memory) on external source 0 980 * using the desired bitstream/bitmap format 981 */ 982 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format); 983 984 /* 985 * Configure overlay 0 according to format and mode and take input 986 * from external source 0 and route the output of this overlay to 987 * channel 0 988 */ 989 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0, 990 MCDE_CHANNEL_0, mode, format, cpp); 991 992 /* 993 * Configure pixel-per-line and line-per-frame for channel 0 and then 994 * route channel 0 to FIFO A 995 */ 996 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode); 997 998 /* Configure FIFO A to use DSI formatter 0 */ 999 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0, 1000 fifo_wtrmrk); 1001 1002 /* 1003 * This brings up the DSI bridge which is tightly connected 1004 * to the MCDE DSI formatter. 1005 * 1006 * FIXME: if we want to use another formatter, such as DPI, 1007 * we need to be more elaborate here and select the appropriate 1008 * bridge. 1009 */ 1010 mcde_dsi_enable(mcde->bridge); 1011 1012 /* Configure the DSI formatter 0 for the DSI panel output */ 1013 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0, 1014 formatter_frame, pkt_size); 1015 1016 switch (mcde->flow_mode) { 1017 case MCDE_COMMAND_TE_FLOW: 1018 case MCDE_COMMAND_BTA_TE_FLOW: 1019 case MCDE_VIDEO_TE_FLOW: 1020 /* We are using TE in some comination */ 1021 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1022 val = MCDE_VSCRC_VSPOL; 1023 else 1024 val = 0; 1025 writel(val, mcde->regs + MCDE_VSCRC0); 1026 /* Enable VSYNC capture on TE0 */ 1027 val = readl(mcde->regs + MCDE_CRC); 1028 val |= MCDE_CRC_SYCEN0; 1029 writel(val, mcde->regs + MCDE_CRC); 1030 break; 1031 default: 1032 /* No TE capture */ 1033 break; 1034 } 1035 1036 drm_crtc_vblank_on(crtc); 1037 1038 /* 1039 * If we're using oneshot mode we don't start the flow 1040 * until each time the display is given an update, and 1041 * then we disable it immediately after. For all other 1042 * modes (command or video) we start the FIFO flow 1043 * right here. This is necessary for the hardware to 1044 * behave right. 1045 */ 1046 if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) { 1047 mcde_enable_fifo(mcde, MCDE_FIFO_A); 1048 dev_dbg(mcde->dev, "started MCDE video FIFO flow\n"); 1049 } 1050 1051 /* Enable MCDE with automatic clock gating */ 1052 val = readl(mcde->regs + MCDE_CR); 1053 val |= MCDE_CR_MCDEEN | MCDE_CR_AUTOCLKG_EN; 1054 writel(val, mcde->regs + MCDE_CR); 1055 1056 dev_info(drm->dev, "MCDE display is enabled\n"); 1057} 1058 1059static void mcde_display_disable(struct drm_simple_display_pipe *pipe) 1060{ 1061 struct drm_crtc *crtc = &pipe->crtc; 1062 struct drm_device *drm = crtc->dev; 1063 struct mcde *mcde = to_mcde(drm); 1064 struct drm_pending_vblank_event *event; 1065 int ret; 1066 1067 drm_crtc_vblank_off(crtc); 1068 1069 /* Disable FIFO A flow */ 1070 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); 1071 1072 /* This disables the DSI bridge */ 1073 mcde_dsi_disable(mcde->bridge); 1074 1075 event = crtc->state->event; 1076 if (event) { 1077 crtc->state->event = NULL; 1078 1079 spin_lock_irq(&crtc->dev->event_lock); 1080 drm_crtc_send_vblank_event(crtc, event); 1081 spin_unlock_irq(&crtc->dev->event_lock); 1082 } 1083 1084 ret = regulator_disable(mcde->epod); 1085 if (ret) 1086 dev_err(drm->dev, "can't disable EPOD regulator\n"); 1087 /* Make sure we are powered down (before we may power up again) */ 1088 usleep_range(50000, 70000); 1089 1090 dev_info(drm->dev, "MCDE display is disabled\n"); 1091} 1092 1093static void mcde_start_flow(struct mcde *mcde) 1094{ 1095 /* Request a TE ACK only in TE+BTA mode */ 1096 if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW) 1097 mcde_dsi_te_request(mcde->mdsi); 1098 1099 /* Enable FIFO A flow */ 1100 mcde_enable_fifo(mcde, MCDE_FIFO_A); 1101 1102 /* 1103 * If oneshot mode is enabled, the flow will be disabled 1104 * when the TE0 IRQ arrives in the interrupt handler. Otherwise 1105 * updates are continuously streamed to the display after this 1106 * point. 1107 */ 1108 1109 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) { 1110 /* Trigger a software sync out on channel 0 */ 1111 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, 1112 mcde->regs + MCDE_CHNL0SYNCHSW); 1113 1114 /* 1115 * Disable FIFO A flow again: since we are using TE sync we 1116 * need to wait for the FIFO to drain before we continue 1117 * so repeated calls to this function will not cause a mess 1118 * in the hardware by pushing updates will updates are going 1119 * on already. 1120 */ 1121 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); 1122 } 1123 1124 dev_dbg(mcde->dev, "started MCDE FIFO flow\n"); 1125} 1126 1127static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address) 1128{ 1129 /* Write bitmap base address to register */ 1130 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0); 1131 /* 1132 * Base address for next line this is probably only used 1133 * in interlace modes. 1134 */ 1135 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1); 1136} 1137 1138static void mcde_display_update(struct drm_simple_display_pipe *pipe, 1139 struct drm_plane_state *old_pstate) 1140{ 1141 struct drm_crtc *crtc = &pipe->crtc; 1142 struct drm_device *drm = crtc->dev; 1143 struct mcde *mcde = to_mcde(drm); 1144 struct drm_pending_vblank_event *event = crtc->state->event; 1145 struct drm_plane *plane = &pipe->plane; 1146 struct drm_plane_state *pstate = plane->state; 1147 struct drm_framebuffer *fb = pstate->fb; 1148 1149 /* 1150 * Handle any pending event first, we need to arm the vblank 1151 * interrupt before sending any update to the display so we don't 1152 * miss the interrupt. 1153 */ 1154 if (event) { 1155 crtc->state->event = NULL; 1156 1157 spin_lock_irq(&crtc->dev->event_lock); 1158 /* 1159 * Hardware must be on before we can arm any vblank event, 1160 * this is not a scanout controller where there is always 1161 * some periodic update going on, it is completely frozen 1162 * until we get an update. If MCDE output isn't yet enabled, 1163 * we just send a vblank dummy event back. 1164 */ 1165 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) { 1166 dev_dbg(mcde->dev, "arm vblank event\n"); 1167 drm_crtc_arm_vblank_event(crtc, event); 1168 } else { 1169 dev_dbg(mcde->dev, "insert fake vblank event\n"); 1170 drm_crtc_send_vblank_event(crtc, event); 1171 } 1172 1173 spin_unlock_irq(&crtc->dev->event_lock); 1174 } 1175 1176 /* 1177 * We do not start sending framebuffer updates before the 1178 * display is enabled. Update events will however be dispatched 1179 * from the DRM core before the display is enabled. 1180 */ 1181 if (fb) { 1182 mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0)); 1183 dev_info_once(mcde->dev, "first update of display contents\n"); 1184 /* 1185 * Usually the flow is already active, unless we are in 1186 * oneshot mode, then we need to kick the flow right here. 1187 */ 1188 if (mcde->flow_active == 0) 1189 mcde_start_flow(mcde); 1190 } else { 1191 /* 1192 * If an update is receieved before the MCDE is enabled 1193 * (before mcde_display_enable() is called) we can't really 1194 * do much with that buffer. 1195 */ 1196 dev_info(mcde->dev, "ignored a display update\n"); 1197 } 1198} 1199 1200static int mcde_display_enable_vblank(struct drm_simple_display_pipe *pipe) 1201{ 1202 struct drm_crtc *crtc = &pipe->crtc; 1203 struct drm_device *drm = crtc->dev; 1204 struct mcde *mcde = to_mcde(drm); 1205 u32 val; 1206 1207 /* Enable all VBLANK IRQs */ 1208 val = MCDE_PP_VCMPA | 1209 MCDE_PP_VCMPB | 1210 MCDE_PP_VSCC0 | 1211 MCDE_PP_VSCC1 | 1212 MCDE_PP_VCMPC0 | 1213 MCDE_PP_VCMPC1; 1214 writel(val, mcde->regs + MCDE_IMSCPP); 1215 1216 return 0; 1217} 1218 1219static void mcde_display_disable_vblank(struct drm_simple_display_pipe *pipe) 1220{ 1221 struct drm_crtc *crtc = &pipe->crtc; 1222 struct drm_device *drm = crtc->dev; 1223 struct mcde *mcde = to_mcde(drm); 1224 1225 /* Disable all VBLANK IRQs */ 1226 writel(0, mcde->regs + MCDE_IMSCPP); 1227 /* Clear any pending IRQs */ 1228 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); 1229} 1230 1231static struct drm_simple_display_pipe_funcs mcde_display_funcs = { 1232 .check = mcde_display_check, 1233 .enable = mcde_display_enable, 1234 .disable = mcde_display_disable, 1235 .update = mcde_display_update, 1236 .enable_vblank = mcde_display_enable_vblank, 1237 .disable_vblank = mcde_display_disable_vblank, 1238 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 1239}; 1240 1241int mcde_display_init(struct drm_device *drm) 1242{ 1243 struct mcde *mcde = to_mcde(drm); 1244 int ret; 1245 static const u32 formats[] = { 1246 DRM_FORMAT_ARGB8888, 1247 DRM_FORMAT_ABGR8888, 1248 DRM_FORMAT_XRGB8888, 1249 DRM_FORMAT_XBGR8888, 1250 DRM_FORMAT_RGB888, 1251 DRM_FORMAT_BGR888, 1252 DRM_FORMAT_ARGB4444, 1253 DRM_FORMAT_ABGR4444, 1254 DRM_FORMAT_XRGB4444, 1255 DRM_FORMAT_XBGR4444, 1256 /* These are actually IRGB1555 so intensity bit is lost */ 1257 DRM_FORMAT_XRGB1555, 1258 DRM_FORMAT_XBGR1555, 1259 DRM_FORMAT_RGB565, 1260 DRM_FORMAT_BGR565, 1261 DRM_FORMAT_YUV422, 1262 }; 1263 1264 ret = drm_simple_display_pipe_init(drm, &mcde->pipe, 1265 &mcde_display_funcs, 1266 formats, ARRAY_SIZE(formats), 1267 NULL, 1268 mcde->connector); 1269 if (ret) 1270 return ret; 1271 1272 return 0; 1273} 1274EXPORT_SYMBOL_GPL(mcde_display_init); 1275