1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * i.MX drm driver - Television Encoder (TVEv2) 4 * 5 * Copyright (C) 2013 Philipp Zabel, Pengutronix 6 */ 7 8#include <linux/clk-provider.h> 9#include <linux/clk.h> 10#include <linux/component.h> 11#include <linux/i2c.h> 12#include <linux/module.h> 13#include <linux/platform_device.h> 14#include <linux/regmap.h> 15#include <linux/regulator/consumer.h> 16#include <linux/videodev2.h> 17 18#include <video/imx-ipu-v3.h> 19 20#include <drm/drm_atomic_helper.h> 21#include <drm/drm_fb_helper.h> 22#include <drm/drm_probe_helper.h> 23#include <drm/drm_simple_kms_helper.h> 24 25#include "imx-drm.h" 26 27#define TVE_COM_CONF_REG 0x00 28#define TVE_TVDAC0_CONT_REG 0x28 29#define TVE_TVDAC1_CONT_REG 0x2c 30#define TVE_TVDAC2_CONT_REG 0x30 31#define TVE_CD_CONT_REG 0x34 32#define TVE_INT_CONT_REG 0x64 33#define TVE_STAT_REG 0x68 34#define TVE_TST_MODE_REG 0x6c 35#define TVE_MV_CONT_REG 0xdc 36 37/* TVE_COM_CONF_REG */ 38#define TVE_SYNC_CH_2_EN BIT(22) 39#define TVE_SYNC_CH_1_EN BIT(21) 40#define TVE_SYNC_CH_0_EN BIT(20) 41#define TVE_TV_OUT_MODE_MASK (0x7 << 12) 42#define TVE_TV_OUT_DISABLE (0x0 << 12) 43#define TVE_TV_OUT_CVBS_0 (0x1 << 12) 44#define TVE_TV_OUT_CVBS_2 (0x2 << 12) 45#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) 46#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) 47#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) 48#define TVE_TV_OUT_YPBPR (0x6 << 12) 49#define TVE_TV_OUT_RGB (0x7 << 12) 50#define TVE_TV_STAND_MASK (0xf << 8) 51#define TVE_TV_STAND_HD_1080P30 (0xc << 8) 52#define TVE_P2I_CONV_EN BIT(7) 53#define TVE_INP_VIDEO_FORM BIT(6) 54#define TVE_INP_YCBCR_422 (0x0 << 6) 55#define TVE_INP_YCBCR_444 (0x1 << 6) 56#define TVE_DATA_SOURCE_MASK (0x3 << 4) 57#define TVE_DATA_SOURCE_BUS1 (0x0 << 4) 58#define TVE_DATA_SOURCE_BUS2 (0x1 << 4) 59#define TVE_DATA_SOURCE_EXT (0x2 << 4) 60#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) 61#define TVE_IPU_CLK_EN_OFS 3 62#define TVE_IPU_CLK_EN BIT(3) 63#define TVE_DAC_SAMP_RATE_OFS 1 64#define TVE_DAC_SAMP_RATE_WIDTH 2 65#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) 66#define TVE_DAC_FULL_RATE (0x0 << 1) 67#define TVE_DAC_DIV2_RATE (0x1 << 1) 68#define TVE_DAC_DIV4_RATE (0x2 << 1) 69#define TVE_EN BIT(0) 70 71/* TVE_TVDACx_CONT_REG */ 72#define TVE_TVDAC_GAIN_MASK (0x3f << 0) 73 74/* TVE_CD_CONT_REG */ 75#define TVE_CD_CH_2_SM_EN BIT(22) 76#define TVE_CD_CH_1_SM_EN BIT(21) 77#define TVE_CD_CH_0_SM_EN BIT(20) 78#define TVE_CD_CH_2_LM_EN BIT(18) 79#define TVE_CD_CH_1_LM_EN BIT(17) 80#define TVE_CD_CH_0_LM_EN BIT(16) 81#define TVE_CD_CH_2_REF_LVL BIT(10) 82#define TVE_CD_CH_1_REF_LVL BIT(9) 83#define TVE_CD_CH_0_REF_LVL BIT(8) 84#define TVE_CD_EN BIT(0) 85 86/* TVE_INT_CONT_REG */ 87#define TVE_FRAME_END_IEN BIT(13) 88#define TVE_CD_MON_END_IEN BIT(2) 89#define TVE_CD_SM_IEN BIT(1) 90#define TVE_CD_LM_IEN BIT(0) 91 92/* TVE_TST_MODE_REG */ 93#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) 94 95#define IMX_TVE_DAC_VOLTAGE 2750000 96 97enum { 98 TVE_MODE_TVOUT, 99 TVE_MODE_VGA, 100}; 101 102struct imx_tve { 103 struct drm_connector connector; 104 struct drm_encoder encoder; 105 struct device *dev; 106 int mode; 107 int di_hsync_pin; 108 int di_vsync_pin; 109 110 struct regmap *regmap; 111 struct regulator *dac_reg; 112 struct i2c_adapter *ddc; 113 struct clk *clk; 114 struct clk *di_sel_clk; 115 struct clk_hw clk_hw_di; 116 struct clk *di_clk; 117}; 118 119static inline struct imx_tve *con_to_tve(struct drm_connector *c) 120{ 121 return container_of(c, struct imx_tve, connector); 122} 123 124static inline struct imx_tve *enc_to_tve(struct drm_encoder *e) 125{ 126 return container_of(e, struct imx_tve, encoder); 127} 128 129static void tve_enable(struct imx_tve *tve) 130{ 131 clk_prepare_enable(tve->clk); 132 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, TVE_EN); 133 134 /* clear interrupt status register */ 135 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); 136 137 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ 138 if (tve->mode == TVE_MODE_VGA) 139 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); 140 else 141 regmap_write(tve->regmap, TVE_INT_CONT_REG, 142 TVE_CD_SM_IEN | 143 TVE_CD_LM_IEN | 144 TVE_CD_MON_END_IEN); 145} 146 147static void tve_disable(struct imx_tve *tve) 148{ 149 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0); 150 clk_disable_unprepare(tve->clk); 151} 152 153static int tve_setup_tvout(struct imx_tve *tve) 154{ 155 return -ENOTSUPP; 156} 157 158static int tve_setup_vga(struct imx_tve *tve) 159{ 160 unsigned int mask; 161 unsigned int val; 162 int ret; 163 164 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ 165 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, 166 TVE_TVDAC_GAIN_MASK, 0x0a); 167 if (ret) 168 return ret; 169 170 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, 171 TVE_TVDAC_GAIN_MASK, 0x0a); 172 if (ret) 173 return ret; 174 175 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, 176 TVE_TVDAC_GAIN_MASK, 0x0a); 177 if (ret) 178 return ret; 179 180 /* set configuration register */ 181 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; 182 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; 183 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; 184 val |= TVE_TV_STAND_HD_1080P30 | 0; 185 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; 186 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; 187 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); 188 if (ret) 189 return ret; 190 191 /* set test mode (as documented) */ 192 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, 193 TVE_TVDAC_TEST_MODE_MASK, 1); 194} 195 196static int imx_tve_connector_get_modes(struct drm_connector *connector) 197{ 198 struct imx_tve *tve = con_to_tve(connector); 199 struct edid *edid; 200 int ret = 0; 201 202 if (!tve->ddc) 203 return 0; 204 205 edid = drm_get_edid(connector, tve->ddc); 206 if (edid) { 207 drm_connector_update_edid_property(connector, edid); 208 ret = drm_add_edid_modes(connector, edid); 209 kfree(edid); 210 } 211 212 return ret; 213} 214 215static enum drm_mode_status 216imx_tve_connector_mode_valid(struct drm_connector *connector, 217 struct drm_display_mode *mode) 218{ 219 struct imx_tve *tve = con_to_tve(connector); 220 unsigned long rate; 221 222 /* pixel clock with 2x oversampling */ 223 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; 224 if (rate == mode->clock) 225 return MODE_OK; 226 227 /* pixel clock without oversampling */ 228 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; 229 if (rate == mode->clock) 230 return MODE_OK; 231 232 dev_warn(tve->dev, "ignoring mode %dx%d\n", 233 mode->hdisplay, mode->vdisplay); 234 235 return MODE_BAD; 236} 237 238static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, 239 struct drm_display_mode *orig_mode, 240 struct drm_display_mode *mode) 241{ 242 struct imx_tve *tve = enc_to_tve(encoder); 243 unsigned long rounded_rate; 244 unsigned long rate; 245 int div = 1; 246 int ret; 247 248 /* 249 * FIXME 250 * we should try 4k * mode->clock first, 251 * and enable 4x oversampling for lower resolutions 252 */ 253 rate = 2000UL * mode->clock; 254 clk_set_rate(tve->clk, rate); 255 rounded_rate = clk_get_rate(tve->clk); 256 if (rounded_rate >= rate) 257 div = 2; 258 clk_set_rate(tve->di_clk, rounded_rate / div); 259 260 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); 261 if (ret < 0) { 262 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", 263 ret); 264 } 265 266 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, 267 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN); 268 269 if (tve->mode == TVE_MODE_VGA) 270 ret = tve_setup_vga(tve); 271 else 272 ret = tve_setup_tvout(tve); 273 if (ret) 274 dev_err(tve->dev, "failed to set configuration: %d\n", ret); 275} 276 277static void imx_tve_encoder_enable(struct drm_encoder *encoder) 278{ 279 struct imx_tve *tve = enc_to_tve(encoder); 280 281 tve_enable(tve); 282} 283 284static void imx_tve_encoder_disable(struct drm_encoder *encoder) 285{ 286 struct imx_tve *tve = enc_to_tve(encoder); 287 288 tve_disable(tve); 289} 290 291static int imx_tve_atomic_check(struct drm_encoder *encoder, 292 struct drm_crtc_state *crtc_state, 293 struct drm_connector_state *conn_state) 294{ 295 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state); 296 struct imx_tve *tve = enc_to_tve(encoder); 297 298 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24; 299 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin; 300 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin; 301 302 return 0; 303} 304 305static const struct drm_connector_funcs imx_tve_connector_funcs = { 306 .fill_modes = drm_helper_probe_single_connector_modes, 307 .destroy = imx_drm_connector_destroy, 308 .reset = drm_atomic_helper_connector_reset, 309 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 310 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 311}; 312 313static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { 314 .get_modes = imx_tve_connector_get_modes, 315 .mode_valid = imx_tve_connector_mode_valid, 316}; 317 318static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { 319 .mode_set = imx_tve_encoder_mode_set, 320 .enable = imx_tve_encoder_enable, 321 .disable = imx_tve_encoder_disable, 322 .atomic_check = imx_tve_atomic_check, 323}; 324 325static irqreturn_t imx_tve_irq_handler(int irq, void *data) 326{ 327 struct imx_tve *tve = data; 328 unsigned int val; 329 330 regmap_read(tve->regmap, TVE_STAT_REG, &val); 331 332 /* clear interrupt status register */ 333 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); 334 335 return IRQ_HANDLED; 336} 337 338static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, 339 unsigned long parent_rate) 340{ 341 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); 342 unsigned int val; 343 int ret; 344 345 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); 346 if (ret < 0) 347 return 0; 348 349 switch (val & TVE_DAC_SAMP_RATE_MASK) { 350 case TVE_DAC_DIV4_RATE: 351 return parent_rate / 4; 352 case TVE_DAC_DIV2_RATE: 353 return parent_rate / 2; 354 case TVE_DAC_FULL_RATE: 355 default: 356 return parent_rate; 357 } 358 359 return 0; 360} 361 362static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, 363 unsigned long *prate) 364{ 365 unsigned long div; 366 367 div = *prate / rate; 368 if (div >= 4) 369 return *prate / 4; 370 else if (div >= 2) 371 return *prate / 2; 372 return *prate; 373} 374 375static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, 376 unsigned long parent_rate) 377{ 378 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); 379 unsigned long div; 380 u32 val; 381 int ret; 382 383 div = parent_rate / rate; 384 if (div >= 4) 385 val = TVE_DAC_DIV4_RATE; 386 else if (div >= 2) 387 val = TVE_DAC_DIV2_RATE; 388 else 389 val = TVE_DAC_FULL_RATE; 390 391 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, 392 TVE_DAC_SAMP_RATE_MASK, val); 393 394 if (ret < 0) { 395 dev_err(tve->dev, "failed to set divider: %d\n", ret); 396 return ret; 397 } 398 399 return 0; 400} 401 402static const struct clk_ops clk_tve_di_ops = { 403 .round_rate = clk_tve_di_round_rate, 404 .set_rate = clk_tve_di_set_rate, 405 .recalc_rate = clk_tve_di_recalc_rate, 406}; 407 408static int tve_clk_init(struct imx_tve *tve, void __iomem *base) 409{ 410 const char *tve_di_parent[1]; 411 struct clk_init_data init = { 412 .name = "tve_di", 413 .ops = &clk_tve_di_ops, 414 .num_parents = 1, 415 .flags = 0, 416 }; 417 418 tve_di_parent[0] = __clk_get_name(tve->clk); 419 init.parent_names = (const char **)&tve_di_parent; 420 421 tve->clk_hw_di.init = &init; 422 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); 423 if (IS_ERR(tve->di_clk)) { 424 dev_err(tve->dev, "failed to register TVE output clock: %ld\n", 425 PTR_ERR(tve->di_clk)); 426 return PTR_ERR(tve->di_clk); 427 } 428 429 return 0; 430} 431 432static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) 433{ 434 int encoder_type; 435 int ret; 436 437 encoder_type = tve->mode == TVE_MODE_VGA ? 438 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; 439 440 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node); 441 if (ret) 442 return ret; 443 444 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); 445 drm_simple_encoder_init(drm, &tve->encoder, encoder_type); 446 447 drm_connector_helper_add(&tve->connector, 448 &imx_tve_connector_helper_funcs); 449 drm_connector_init_with_ddc(drm, &tve->connector, 450 &imx_tve_connector_funcs, 451 DRM_MODE_CONNECTOR_VGA, 452 tve->ddc); 453 454 drm_connector_attach_encoder(&tve->connector, &tve->encoder); 455 456 return 0; 457} 458 459static void imx_tve_disable_regulator(void *data) 460{ 461 struct imx_tve *tve = data; 462 463 regulator_disable(tve->dac_reg); 464} 465 466static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) 467{ 468 return (reg % 4 == 0) && (reg <= 0xdc); 469} 470 471static struct regmap_config tve_regmap_config = { 472 .reg_bits = 32, 473 .val_bits = 32, 474 .reg_stride = 4, 475 476 .readable_reg = imx_tve_readable_reg, 477 478 .fast_io = true, 479 480 .max_register = 0xdc, 481}; 482 483static const char * const imx_tve_modes[] = { 484 [TVE_MODE_TVOUT] = "tvout", 485 [TVE_MODE_VGA] = "vga", 486}; 487 488static int of_get_tve_mode(struct device_node *np) 489{ 490 const char *bm; 491 int ret, i; 492 493 ret = of_property_read_string(np, "fsl,tve-mode", &bm); 494 if (ret < 0) 495 return ret; 496 497 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) 498 if (!strcasecmp(bm, imx_tve_modes[i])) 499 return i; 500 501 return -EINVAL; 502} 503 504static int imx_tve_bind(struct device *dev, struct device *master, void *data) 505{ 506 struct platform_device *pdev = to_platform_device(dev); 507 struct drm_device *drm = data; 508 struct device_node *np = dev->of_node; 509 struct device_node *ddc_node; 510 struct imx_tve *tve; 511 struct resource *res; 512 void __iomem *base; 513 unsigned int val; 514 int irq; 515 int ret; 516 517 tve = dev_get_drvdata(dev); 518 memset(tve, 0, sizeof(*tve)); 519 520 tve->dev = dev; 521 522 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 523 if (ddc_node) { 524 tve->ddc = of_find_i2c_adapter_by_node(ddc_node); 525 of_node_put(ddc_node); 526 } 527 528 tve->mode = of_get_tve_mode(np); 529 if (tve->mode != TVE_MODE_VGA) { 530 dev_err(dev, "only VGA mode supported, currently\n"); 531 return -EINVAL; 532 } 533 534 if (tve->mode == TVE_MODE_VGA) { 535 ret = of_property_read_u32(np, "fsl,hsync-pin", 536 &tve->di_hsync_pin); 537 538 if (ret < 0) { 539 dev_err(dev, "failed to get hsync pin\n"); 540 return ret; 541 } 542 543 ret = of_property_read_u32(np, "fsl,vsync-pin", 544 &tve->di_vsync_pin); 545 546 if (ret < 0) { 547 dev_err(dev, "failed to get vsync pin\n"); 548 return ret; 549 } 550 } 551 552 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 553 base = devm_ioremap_resource(dev, res); 554 if (IS_ERR(base)) 555 return PTR_ERR(base); 556 557 tve_regmap_config.lock_arg = tve; 558 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, 559 &tve_regmap_config); 560 if (IS_ERR(tve->regmap)) { 561 dev_err(dev, "failed to init regmap: %ld\n", 562 PTR_ERR(tve->regmap)); 563 return PTR_ERR(tve->regmap); 564 } 565 566 irq = platform_get_irq(pdev, 0); 567 if (irq < 0) 568 return irq; 569 570 ret = devm_request_threaded_irq(dev, irq, NULL, 571 imx_tve_irq_handler, IRQF_ONESHOT, 572 "imx-tve", tve); 573 if (ret < 0) { 574 dev_err(dev, "failed to request irq: %d\n", ret); 575 return ret; 576 } 577 578 tve->dac_reg = devm_regulator_get(dev, "dac"); 579 if (!IS_ERR(tve->dac_reg)) { 580 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE) 581 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE); 582 ret = regulator_enable(tve->dac_reg); 583 if (ret) 584 return ret; 585 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve); 586 if (ret) 587 return ret; 588 } 589 590 tve->clk = devm_clk_get(dev, "tve"); 591 if (IS_ERR(tve->clk)) { 592 dev_err(dev, "failed to get high speed tve clock: %ld\n", 593 PTR_ERR(tve->clk)); 594 return PTR_ERR(tve->clk); 595 } 596 597 /* this is the IPU DI clock input selector, can be parented to tve_di */ 598 tve->di_sel_clk = devm_clk_get(dev, "di_sel"); 599 if (IS_ERR(tve->di_sel_clk)) { 600 dev_err(dev, "failed to get ipu di mux clock: %ld\n", 601 PTR_ERR(tve->di_sel_clk)); 602 return PTR_ERR(tve->di_sel_clk); 603 } 604 605 ret = tve_clk_init(tve, base); 606 if (ret < 0) 607 return ret; 608 609 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); 610 if (ret < 0) { 611 dev_err(dev, "failed to read configuration register: %d\n", 612 ret); 613 return ret; 614 } 615 if (val != 0x00100000) { 616 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); 617 return -ENODEV; 618 } 619 620 /* disable cable detection for VGA mode */ 621 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); 622 if (ret) 623 return ret; 624 625 ret = imx_tve_register(drm, tve); 626 if (ret) 627 return ret; 628 629 return 0; 630} 631 632static const struct component_ops imx_tve_ops = { 633 .bind = imx_tve_bind, 634}; 635 636static int imx_tve_probe(struct platform_device *pdev) 637{ 638 struct imx_tve *tve; 639 640 tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL); 641 if (!tve) 642 return -ENOMEM; 643 644 platform_set_drvdata(pdev, tve); 645 646 return component_add(&pdev->dev, &imx_tve_ops); 647} 648 649static int imx_tve_remove(struct platform_device *pdev) 650{ 651 component_del(&pdev->dev, &imx_tve_ops); 652 return 0; 653} 654 655static const struct of_device_id imx_tve_dt_ids[] = { 656 { .compatible = "fsl,imx53-tve", }, 657 { /* sentinel */ } 658}; 659MODULE_DEVICE_TABLE(of, imx_tve_dt_ids); 660 661static struct platform_driver imx_tve_driver = { 662 .probe = imx_tve_probe, 663 .remove = imx_tve_remove, 664 .driver = { 665 .of_match_table = imx_tve_dt_ids, 666 .name = "imx-tve", 667 }, 668}; 669 670module_platform_driver(imx_tve_driver); 671 672MODULE_DESCRIPTION("i.MX Television Encoder driver"); 673MODULE_AUTHOR("Philipp Zabel, Pengutronix"); 674MODULE_LICENSE("GPL"); 675MODULE_ALIAS("platform:imx-tve"); 676