1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "display/intel_display.h"
31
32#include "gt/intel_engine_types.h"
33#include "gt/intel_context_types.h"
34#include "gt/intel_sseu.h"
35
36struct drm_printer;
37struct drm_i915_private;
38
39/* Keep in gen based order, and chronological order within a gen */
40enum intel_platform {
41	INTEL_PLATFORM_UNINITIALIZED = 0,
42	/* gen2 */
43	INTEL_I830,
44	INTEL_I845G,
45	INTEL_I85X,
46	INTEL_I865G,
47	/* gen3 */
48	INTEL_I915G,
49	INTEL_I915GM,
50	INTEL_I945G,
51	INTEL_I945GM,
52	INTEL_G33,
53	INTEL_PINEVIEW,
54	/* gen4 */
55	INTEL_I965G,
56	INTEL_I965GM,
57	INTEL_G45,
58	INTEL_GM45,
59	/* gen5 */
60	INTEL_IRONLAKE,
61	/* gen6 */
62	INTEL_SANDYBRIDGE,
63	/* gen7 */
64	INTEL_IVYBRIDGE,
65	INTEL_VALLEYVIEW,
66	INTEL_HASWELL,
67	/* gen8 */
68	INTEL_BROADWELL,
69	INTEL_CHERRYVIEW,
70	/* gen9 */
71	INTEL_SKYLAKE,
72	INTEL_BROXTON,
73	INTEL_KABYLAKE,
74	INTEL_GEMINILAKE,
75	INTEL_COFFEELAKE,
76	INTEL_COMETLAKE,
77	/* gen10 */
78	INTEL_CANNONLAKE,
79	/* gen11 */
80	INTEL_ICELAKE,
81	INTEL_ELKHARTLAKE,
82	/* gen12 */
83	INTEL_TIGERLAKE,
84	INTEL_ROCKETLAKE,
85	INTEL_DG1,
86	INTEL_MAX_PLATFORMS
87};
88
89/*
90 * Subplatform bits share the same namespace per parent platform. In other words
91 * it is fine for the same bit to be used on multiple parent platforms.
92 */
93
94#define INTEL_SUBPLATFORM_BITS (3)
95
96/* HSW/BDW/SKL/KBL/CFL */
97#define INTEL_SUBPLATFORM_ULT	(0)
98#define INTEL_SUBPLATFORM_ULX	(1)
99
100/* CNL/ICL */
101#define INTEL_SUBPLATFORM_PORTF	(0)
102
103enum intel_ppgtt_type {
104	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
105	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
106	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
107};
108
109#define DEV_INFO_FOR_EACH_FLAG(func) \
110	func(is_mobile); \
111	func(is_lp); \
112	func(require_force_probe); \
113	func(is_dgfx); \
114	/* Keep has_* in alphabetical order */ \
115	func(has_64bit_reloc); \
116	func(gpu_reset_clobbers_display); \
117	func(has_reset_engine); \
118	func(has_fpga_dbg); \
119	func(has_global_mocs); \
120	func(has_gt_uc); \
121	func(has_l3_dpf); \
122	func(has_llc); \
123	func(has_logical_ring_contexts); \
124	func(has_logical_ring_elsq); \
125	func(has_logical_ring_preemption); \
126	func(has_master_unit_irq); \
127	func(has_pooled_eu); \
128	func(has_rc6); \
129	func(has_rc6p); \
130	func(has_rps); \
131	func(has_runtime_pm); \
132	func(has_snoop); \
133	func(has_coherent_ggtt); \
134	func(unfenced_needs_alignment); \
135	func(hws_needs_physical);
136
137#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
138	/* Keep in alphabetical order */ \
139	func(cursor_needs_physical); \
140	func(has_csr); \
141	func(has_ddi); \
142	func(has_dp_mst); \
143	func(has_dsb); \
144	func(has_dsc); \
145	func(has_fbc); \
146	func(has_gmch); \
147	func(has_hdcp); \
148	func(has_hotplug); \
149	func(has_hti); \
150	func(has_ipc); \
151	func(has_modular_fia); \
152	func(has_overlay); \
153	func(has_psr); \
154	func(has_psr_hw_tracking); \
155	func(overlay_needs_physical); \
156	func(supports_tv);
157
158struct intel_device_info {
159	u16 gen_mask;
160
161	u8 gen;
162	u8 gt; /* GT number, 0 if undefined */
163	intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
164
165	enum intel_platform platform;
166
167	unsigned int dma_mask_size; /* available DMA address bits */
168
169	enum intel_ppgtt_type ppgtt_type;
170	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
171
172	unsigned int page_sizes; /* page sizes supported by the HW */
173
174	u32 memory_regions; /* regions supported by the HW */
175
176	u32 display_mmio_offset;
177
178	u8 pipe_mask;
179	u8 cpu_transcoder_mask;
180
181	u8 abox_mask;
182
183#define DEFINE_FLAG(name) u8 name:1
184	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
185#undef DEFINE_FLAG
186
187	struct {
188#define DEFINE_FLAG(name) u8 name:1
189		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
190#undef DEFINE_FLAG
191	} display;
192
193	u16 ddb_size; /* in blocks */
194	u8 num_supported_dbuf_slices; /* number of DBuf slices */
195
196	/* Register offsets for the various display pipes and transcoders */
197	int pipe_offsets[I915_MAX_TRANSCODERS];
198	int trans_offsets[I915_MAX_TRANSCODERS];
199	int cursor_offsets[I915_MAX_PIPES];
200
201	struct color_luts {
202		u32 degamma_lut_size;
203		u32 gamma_lut_size;
204		u32 degamma_lut_tests;
205		u32 gamma_lut_tests;
206	} color;
207};
208
209struct intel_runtime_info {
210	/*
211	 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
212	 * into single runtime conditionals, and also to provide groundwork
213	 * for future per platform, or per SKU build optimizations.
214	 *
215	 * Array can be extended when necessary if the corresponding
216	 * BUILD_BUG_ON is hit.
217	 */
218	u32 platform_mask[2];
219
220	u16 device_id;
221
222	u8 num_sprites[I915_MAX_PIPES];
223	u8 num_scalers[I915_MAX_PIPES];
224
225	u32 rawclk_freq;
226
227	u32 cs_timestamp_frequency_hz;
228	u32 cs_timestamp_period_ns;
229};
230
231struct intel_driver_caps {
232	unsigned int scheduler;
233	bool has_logical_contexts:1;
234};
235
236const char *intel_platform_name(enum intel_platform platform);
237
238void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
239void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
240
241void intel_device_info_print_static(const struct intel_device_info *info,
242				    struct drm_printer *p);
243void intel_device_info_print_runtime(const struct intel_runtime_info *info,
244				     struct drm_printer *p);
245
246void intel_driver_caps_print(const struct intel_driver_caps *caps,
247			     struct drm_printer *p);
248
249#endif
250