1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef _I915_REG_H_ 26#define _I915_REG_H_ 27 28#include <linux/bitfield.h> 29#include <linux/bits.h> 30 31/** 32 * DOC: The i915 register macro definition style guide 33 * 34 * Follow the style described here for new macros, and while changing existing 35 * macros. Do **not** mass change existing definitions just to update the style. 36 * 37 * File Layout 38 * ~~~~~~~~~~~ 39 * 40 * Keep helper macros near the top. For example, _PIPE() and friends. 41 * 42 * Prefix macros that generally should not be used outside of this file with 43 * underscore '_'. For example, _PIPE() and friends, single instances of 44 * registers that are defined solely for the use by function-like macros. 45 * 46 * Avoid using the underscore prefixed macros outside of this file. There are 47 * exceptions, but keep them to a minimum. 48 * 49 * There are two basic types of register definitions: Single registers and 50 * register groups. Register groups are registers which have two or more 51 * instances, for example one per pipe, port, transcoder, etc. Register groups 52 * should be defined using function-like macros. 53 * 54 * For single registers, define the register offset first, followed by register 55 * contents. 56 * 57 * For register groups, define the register instance offsets first, prefixed 58 * with underscore, followed by a function-like macro choosing the right 59 * instance based on the parameter, followed by register contents. 60 * 61 * Define the register contents (i.e. bit and bit field macros) from most 62 * significant to least significant bit. Indent the register content macros 63 * using two extra spaces between ``#define`` and the macro name. 64 * 65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 67 * shifted in place, so they can be directly OR'd together. For convenience, 68 * function-like macros may be used to define bit fields, but do note that the 69 * macros may be needed to read as well as write the register contents. 70 * 71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 72 * 73 * Group the register and its contents together without blank lines, separate 74 * from other registers and their contents with one blank line. 75 * 76 * Indent macro values from macro names using TABs. Align values vertically. Use 77 * braces in macro values as needed to avoid unintended precedence after macro 78 * substitution. Use spaces in macro values according to kernel coding 79 * style. Use lower case in hexadecimal values. 80 * 81 * Naming 82 * ~~~~~~ 83 * 84 * Try to name registers according to the specs. If the register name changes in 85 * the specs from platform to another, stick to the original name. 86 * 87 * Try to re-use existing register macro definitions. Only add new macros for 88 * new register offsets, or when the register contents have changed enough to 89 * warrant a full redefinition. 90 * 91 * When a register macro changes for a new platform, prefix the new macro using 92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 93 * prefix signifies the start platform/generation using the register. 94 * 95 * When a bit (field) macro changes or gets added for a new platform, while 96 * retaining the existing register macro, add a platform acronym or generation 97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 98 * 99 * Examples 100 * ~~~~~~~~ 101 * 102 * (Note that the values in the example are indented using spaces instead of 103 * TABs to avoid misalignment in generated documentation. Use TABs in the 104 * definitions.):: 105 * 106 * #define _FOO_A 0xf000 107 * #define _FOO_B 0xf001 108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 109 * #define FOO_ENABLE REG_BIT(31) 110 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 114 * 115 * #define BAR _MMIO(0xb000) 116 * #define GEN8_BAR _MMIO(0xb888) 117 */ 118 119/** 120 * REG_BIT() - Prepare a u32 bit value 121 * @__n: 0-based bit number 122 * 123 * Local wrapper for BIT() to force u32, with compile time checks. 124 * 125 * @return: Value with bit @__n set. 126 */ 127#define REG_BIT(__n) \ 128 ((u32)(BIT(__n) + \ 129 BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ 130 ((__n) < 0 || (__n) > 31)))) 131 132/** 133 * REG_GENMASK() - Prepare a continuous u32 bitmask 134 * @__high: 0-based high bit 135 * @__low: 0-based low bit 136 * 137 * Local wrapper for GENMASK() to force u32, with compile time checks. 138 * 139 * @return: Continuous bitmask from @__high to @__low, inclusive. 140 */ 141#define REG_GENMASK(__high, __low) \ 142 ((u32)(GENMASK(__high, __low) + \ 143 BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ 144 __is_constexpr(__low) && \ 145 ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) 146 147/* 148 * Local integer constant expression version of is_power_of_2(). 149 */ 150#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0)) 151 152/** 153 * REG_FIELD_PREP() - Prepare a u32 bitfield value 154 * @__mask: shifted mask defining the field's length and position 155 * @__val: value to put in the field 156 * 157 * Local copy of FIELD_PREP() to generate an integer constant expression, force 158 * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK(). 159 * 160 * @return: @__val masked and shifted into the field defined by @__mask. 161 */ 162#define REG_FIELD_PREP(__mask, __val) \ 163 ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ 164 BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ 165 BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \ 166 BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ 167 BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) 168 169/** 170 * REG_FIELD_GET() - Extract a u32 bitfield value 171 * @__mask: shifted mask defining the field's length and position 172 * @__val: value to extract the bitfield value from 173 * 174 * Local wrapper for FIELD_GET() to force u32 and for consistency with 175 * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK(). 176 * 177 * @return: Masked and shifted value of the field defined by @__mask in @__val. 178 */ 179#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) 180 181typedef struct { 182 u32 reg; 183} i915_reg_t; 184 185#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) 186 187#define INVALID_MMIO_REG _MMIO(0) 188 189static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) 190{ 191 return reg.reg; 192} 193 194static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) 195{ 196 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b); 197} 198 199static inline bool i915_mmio_reg_valid(i915_reg_t reg) 200{ 201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); 202} 203 204#define VLV_DISPLAY_BASE 0x180000 205#define VLV_MIPI_BASE VLV_DISPLAY_BASE 206#define BXT_MIPI_BASE 0x60000 207 208#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 209 210/* 211 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 212 * numbers, pick the 0-based __index'th value. 213 * 214 * Always prefer this over _PICK() if the numbers are evenly spaced. 215 */ 216#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 217 218/* 219 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 220 * 221 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 222 */ 223#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 224 225/* 226 * Named helper wrappers around _PICK_EVEN() and _PICK(). 227 */ 228#define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 229#define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 230#define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 231#define _PORT(port, a, b) _PICK_EVEN(port, a, b) 232#define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 233 234#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 235#define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 236#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 237#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 238#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 239 240#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 241 242#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 243#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 244#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 245#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c)) 246 247/* 248 * Device info offset array based helpers for groups of registers with unevenly 249 * spaced base offsets. 250 */ 251#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 253 DISPLAY_MMIO_BASE(dev_priv)) 254#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ 255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 256 DISPLAY_MMIO_BASE(dev_priv)) 257#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) 258#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 260 DISPLAY_MMIO_BASE(dev_priv)) 261 262#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 263#define _MASKED_FIELD(mask, value) ({ \ 264 if (__builtin_constant_p(mask)) \ 265 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 266 if (__builtin_constant_p(value)) \ 267 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 268 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 269 BUILD_BUG_ON_MSG((value) & ~(mask), \ 270 "Incorrect value for mask"); \ 271 __MASKED_FIELD(mask, value); }) 272#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 273#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 274 275/* PCI config space */ 276 277#define MCHBAR_I915 0x44 278#define MCHBAR_I965 0x48 279#define MCHBAR_SIZE (4 * 4096) 280 281#define DEVEN 0x54 282#define DEVEN_MCHBAR_EN (1 << 28) 283 284/* BSM in include/drm/i915_drm.h */ 285 286#define HPLLCC 0xc0 /* 85x only */ 287#define GC_CLOCK_CONTROL_MASK (0x7 << 0) 288#define GC_CLOCK_133_200 (0 << 0) 289#define GC_CLOCK_100_200 (1 << 0) 290#define GC_CLOCK_100_133 (2 << 0) 291#define GC_CLOCK_133_266 (3 << 0) 292#define GC_CLOCK_133_200_2 (4 << 0) 293#define GC_CLOCK_133_266_2 (5 << 0) 294#define GC_CLOCK_166_266 (6 << 0) 295#define GC_CLOCK_166_250 (7 << 0) 296 297#define I915_GDRST 0xc0 /* PCI config register */ 298#define GRDOM_FULL (0 << 2) 299#define GRDOM_RENDER (1 << 2) 300#define GRDOM_MEDIA (3 << 2) 301#define GRDOM_MASK (3 << 2) 302#define GRDOM_RESET_STATUS (1 << 1) 303#define GRDOM_RESET_ENABLE (1 << 0) 304 305/* BSpec only has register offset, PCI device and bit found empirically */ 306#define I830_CLOCK_GATE 0xc8 /* device 0 */ 307#define I830_L2_CACHE_CLOCK_GATE_DISABLE (1 << 2) 308 309#define GCDGMBUS 0xcc 310 311#define GCFGC2 0xda 312#define GCFGC 0xf0 /* 915+ only */ 313#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 314#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 315#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) 316#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 317#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 318#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 319#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 320#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 321#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 322#define GC_DISPLAY_CLOCK_MASK (7 << 4) 323#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 324#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 325#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 326#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 327#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 328#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 329#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 330#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 331#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 332#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 333#define I945_GC_RENDER_CLOCK_MASK (7 << 0) 334#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 335#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 336#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 337#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 338#define I915_GC_RENDER_CLOCK_MASK (7 << 0) 339#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 340#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 341#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 342 343#define ASLE 0xe4 344#define ASLS 0xfc 345 346#define SWSCI 0xe8 347#define SWSCI_SCISEL (1 << 15) 348#define SWSCI_GSSCIE (1 << 0) 349 350#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 351 352 353#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4) 354#define ILK_GRDOM_FULL (0 << 1) 355#define ILK_GRDOM_RENDER (1 << 1) 356#define ILK_GRDOM_MEDIA (3 << 1) 357#define ILK_GRDOM_MASK (3 << 1) 358#define ILK_GRDOM_RESET_ENABLE (1 << 0) 359 360#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 361#define GEN6_MBC_SNPCR_SHIFT 21 362#define GEN6_MBC_SNPCR_MASK (3 << 21) 363#define GEN6_MBC_SNPCR_MAX (0 << 21) 364#define GEN6_MBC_SNPCR_MED (1 << 21) 365#define GEN6_MBC_SNPCR_LOW (2 << 21) 366#define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 367 368#define VLV_G3DCTL _MMIO(0x9024) 369#define VLV_GSCKGCTL _MMIO(0x9028) 370 371#define GEN6_MBCTL _MMIO(0x0907c) 372#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 373#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 374#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 375#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 376#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 377 378#define GEN6_GDRST _MMIO(0x941c) 379#define GEN6_GRDOM_FULL (1 << 0) 380#define GEN6_GRDOM_RENDER (1 << 1) 381#define GEN6_GRDOM_MEDIA (1 << 2) 382#define GEN6_GRDOM_BLT (1 << 3) 383#define GEN6_GRDOM_VECS (1 << 4) 384#define GEN9_GRDOM_GUC (1 << 5) 385#define GEN8_GRDOM_MEDIA2 (1 << 7) 386/* GEN11 changed all bit defs except for FULL & RENDER */ 387#define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 388#define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 389#define GEN11_GRDOM_BLT (1 << 2) 390#define GEN11_GRDOM_GUC (1 << 3) 391#define GEN11_GRDOM_MEDIA (1 << 5) 392#define GEN11_GRDOM_MEDIA2 (1 << 6) 393#define GEN11_GRDOM_MEDIA3 (1 << 7) 394#define GEN11_GRDOM_MEDIA4 (1 << 8) 395#define GEN11_GRDOM_VECS (1 << 13) 396#define GEN11_GRDOM_VECS2 (1 << 14) 397#define GEN11_GRDOM_SFC0 (1 << 17) 398#define GEN11_GRDOM_SFC1 (1 << 18) 399 400#define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 401#define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 402 403#define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C) 404#define GEN11_VCS_SFC_FORCED_LOCK_BIT (1 << 0) 405#define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890) 406#define GEN11_VCS_SFC_USAGE_BIT (1 << 0) 407#define GEN11_VCS_SFC_LOCK_ACK_BIT (1 << 1) 408 409#define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C) 410#define GEN11_VECS_SFC_FORCED_LOCK_BIT (1 << 0) 411#define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018) 412#define GEN11_VECS_SFC_LOCK_ACK_BIT (1 << 0) 413#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) 414#define GEN11_VECS_SFC_USAGE_BIT (1 << 0) 415 416#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) 417#define GEN12_SFC_DONE_MAX 4 418 419#define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228) 420#define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518) 421#define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220) 422#define PP_DIR_DCLV_2G 0xffffffff 423 424#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4) 425#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8) 426 427#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8) 428#define GEN8_RPCS_ENABLE (1 << 31) 429#define GEN8_RPCS_S_CNT_ENABLE (1 << 18) 430#define GEN8_RPCS_S_CNT_SHIFT 15 431#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT) 432#define GEN11_RPCS_S_CNT_SHIFT 12 433#define GEN11_RPCS_S_CNT_MASK (0x3f << GEN11_RPCS_S_CNT_SHIFT) 434#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11) 435#define GEN8_RPCS_SS_CNT_SHIFT 8 436#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT) 437#define GEN8_RPCS_EU_MAX_SHIFT 4 438#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT) 439#define GEN8_RPCS_EU_MIN_SHIFT 0 440#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT) 441 442#define WAIT_FOR_RC6_EXIT _MMIO(0x20CC) 443/* HSW only */ 444#define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 445#define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 446#define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 447#define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 448/* HSW+ */ 449#define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 450#define HSW_RCS_CONTEXT_ENABLE (1 << 7) 451#define HSW_RCS_INHIBIT (1 << 8) 452/* Gen8 */ 453#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 454#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 455#define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 456#define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 457#define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 458#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 459#define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 460#define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 461#define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 462#define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 463 464#define GAM_ECOCHK _MMIO(0x4090) 465#define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 466#define ECOCHK_SNB_BIT (1 << 10) 467#define ECOCHK_DIS_TLB (1 << 8) 468#define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 469#define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 470#define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 471#define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 472#define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 473#define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 474#define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 475#define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 476 477#define GEN8_RC6_CTX_INFO _MMIO(0x8504) 478 479#define GAC_ECO_BITS _MMIO(0x14090) 480#define ECOBITS_SNB_BIT (1 << 13) 481#define ECOBITS_PPGTT_CACHE64B (3 << 8) 482#define ECOBITS_PPGTT_CACHE4B (0 << 8) 483 484#define GAB_CTL _MMIO(0x24000) 485#define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 486 487#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 488#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 489#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 490#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 491#define GEN6_STOLEN_RESERVED_1M (0 << 4) 492#define GEN6_STOLEN_RESERVED_512K (1 << 4) 493#define GEN6_STOLEN_RESERVED_256K (2 << 4) 494#define GEN6_STOLEN_RESERVED_128K (3 << 4) 495#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 496#define GEN7_STOLEN_RESERVED_1M (0 << 5) 497#define GEN7_STOLEN_RESERVED_256K (1 << 5) 498#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 499#define GEN8_STOLEN_RESERVED_1M (0 << 7) 500#define GEN8_STOLEN_RESERVED_2M (1 << 7) 501#define GEN8_STOLEN_RESERVED_4M (2 << 7) 502#define GEN8_STOLEN_RESERVED_8M (3 << 7) 503#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 504#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 505 506/* VGA stuff */ 507 508#define VGA_ST01_MDA 0x3ba 509#define VGA_ST01_CGA 0x3da 510 511#define _VGA_MSR_WRITE _MMIO(0x3c2) 512#define VGA_MSR_WRITE 0x3c2 513#define VGA_MSR_READ 0x3cc 514#define VGA_MSR_MEM_EN (1 << 1) 515#define VGA_MSR_CGA_MODE (1 << 0) 516 517#define VGA_SR_INDEX 0x3c4 518#define SR01 1 519#define VGA_SR_DATA 0x3c5 520 521#define VGA_AR_INDEX 0x3c0 522#define VGA_AR_VID_EN (1 << 5) 523#define VGA_AR_DATA_WRITE 0x3c0 524#define VGA_AR_DATA_READ 0x3c1 525 526#define VGA_GR_INDEX 0x3ce 527#define VGA_GR_DATA 0x3cf 528/* GR05 */ 529#define VGA_GR_MEM_READ_MODE_SHIFT 3 530#define VGA_GR_MEM_READ_MODE_PLANE 1 531/* GR06 */ 532#define VGA_GR_MEM_MODE_MASK 0xc 533#define VGA_GR_MEM_MODE_SHIFT 2 534#define VGA_GR_MEM_A0000_AFFFF 0 535#define VGA_GR_MEM_A0000_BFFFF 1 536#define VGA_GR_MEM_B0000_B7FFF 2 537#define VGA_GR_MEM_B0000_BFFFF 3 538 539#define VGA_DACMASK 0x3c6 540#define VGA_DACRX 0x3c7 541#define VGA_DACWX 0x3c8 542#define VGA_DACDATA 0x3c9 543 544#define VGA_CR_INDEX_MDA 0x3b4 545#define VGA_CR_DATA_MDA 0x3b5 546#define VGA_CR_INDEX_CGA 0x3d4 547#define VGA_CR_DATA_CGA 0x3d5 548 549#define MI_PREDICATE_SRC0 _MMIO(0x2400) 550#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4) 551#define MI_PREDICATE_SRC1 _MMIO(0x2408) 552#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4) 553#define MI_PREDICATE_DATA _MMIO(0x2410) 554#define MI_PREDICATE_RESULT _MMIO(0x2418) 555#define MI_PREDICATE_RESULT_1 _MMIO(0x241c) 556#define MI_PREDICATE_RESULT_2 _MMIO(0x2214) 557#define LOWER_SLICE_ENABLED (1 << 0) 558#define LOWER_SLICE_DISABLED (0 << 0) 559 560/* 561 * Registers used only by the command parser 562 */ 563#define BCS_SWCTRL _MMIO(0x22200) 564#define BCS_SRC_Y REG_BIT(0) 565#define BCS_DST_Y REG_BIT(1) 566 567/* There are 16 GPR registers */ 568#define BCS_GPR(n) _MMIO(0x22600 + (n) * 8) 569#define BCS_GPR_UDW(n) _MMIO(0x22600 + (n) * 8 + 4) 570 571#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 572#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 573#define HS_INVOCATION_COUNT _MMIO(0x2300) 574#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 575#define DS_INVOCATION_COUNT _MMIO(0x2308) 576#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 577#define IA_VERTICES_COUNT _MMIO(0x2310) 578#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 579#define IA_PRIMITIVES_COUNT _MMIO(0x2318) 580#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 581#define VS_INVOCATION_COUNT _MMIO(0x2320) 582#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 583#define GS_INVOCATION_COUNT _MMIO(0x2328) 584#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 585#define GS_PRIMITIVES_COUNT _MMIO(0x2330) 586#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 587#define CL_INVOCATION_COUNT _MMIO(0x2338) 588#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 589#define CL_PRIMITIVES_COUNT _MMIO(0x2340) 590#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 591#define PS_INVOCATION_COUNT _MMIO(0x2348) 592#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 593#define PS_DEPTH_COUNT _MMIO(0x2350) 594#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 595 596/* There are the 4 64-bit counter registers, one for each stream output */ 597#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 598#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 599 600#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 601#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 602 603#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 604#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 605#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 606#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 607#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C) 608#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 609 610#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 611#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 612#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 613 614/* There are the 16 64-bit CS General Purpose Registers */ 615#define HSW_CS_GPR(n) _MMIO(0x2600 + (n) * 8) 616#define HSW_CS_GPR_UDW(n) _MMIO(0x2600 + (n) * 8 + 4) 617 618#define GEN7_OACONTROL _MMIO(0x2360) 619#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 620#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 621#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 622#define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 623#define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 624#define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 625#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 626#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 627#define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 628#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 629#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 630#define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 631#define GEN7_OACONTROL_FORMAT_SHIFT 2 632#define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 633#define GEN7_OACONTROL_ENABLE (1 << 0) 634 635#define GEN8_OACTXID _MMIO(0x2364) 636 637#define GEN8_OA_DEBUG _MMIO(0x2B04) 638#define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 639#define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 640#define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 641#define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 642 643#define GEN8_OACONTROL _MMIO(0x2B00) 644#define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 645#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 646#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 647#define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 648#define GEN8_OA_REPORT_FORMAT_SHIFT 2 649#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 650#define GEN8_OA_COUNTER_ENABLE (1 << 0) 651 652#define GEN8_OACTXCONTROL _MMIO(0x2360) 653#define GEN8_OA_TIMER_PERIOD_MASK 0x3F 654#define GEN8_OA_TIMER_PERIOD_SHIFT 2 655#define GEN8_OA_TIMER_ENABLE (1 << 1) 656#define GEN8_OA_COUNTER_RESUME (1 << 0) 657 658#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 659#define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 660#define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 661#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 662#define GEN7_OABUFFER_RESUME (1 << 0) 663 664#define GEN8_OABUFFER_UDW _MMIO(0x23b4) 665#define GEN8_OABUFFER _MMIO(0x2b14) 666#define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 667 668#define GEN7_OASTATUS1 _MMIO(0x2364) 669#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 670#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 671#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 672#define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 673 674#define GEN7_OASTATUS2 _MMIO(0x2368) 675#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 676#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 677 678#define GEN8_OASTATUS _MMIO(0x2b08) 679#define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17) 680#define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16) 681#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 682#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 683#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 684#define GEN8_OASTATUS_REPORT_LOST (1 << 0) 685 686#define GEN8_OAHEADPTR _MMIO(0x2B0C) 687#define GEN8_OAHEADPTR_MASK 0xffffffc0 688#define GEN8_OATAILPTR _MMIO(0x2B10) 689#define GEN8_OATAILPTR_MASK 0xffffffc0 690 691#define OABUFFER_SIZE_128K (0 << 3) 692#define OABUFFER_SIZE_256K (1 << 3) 693#define OABUFFER_SIZE_512K (2 << 3) 694#define OABUFFER_SIZE_1M (3 << 3) 695#define OABUFFER_SIZE_2M (4 << 3) 696#define OABUFFER_SIZE_4M (5 << 3) 697#define OABUFFER_SIZE_8M (6 << 3) 698#define OABUFFER_SIZE_16M (7 << 3) 699 700#define GEN12_OA_TLB_INV_CR _MMIO(0xceec) 701 702/* Gen12 OAR unit */ 703#define GEN12_OAR_OACONTROL _MMIO(0x2960) 704#define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 705#define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) 706 707#define GEN12_OACTXCONTROL _MMIO(0x2360) 708#define GEN12_OAR_OASTATUS _MMIO(0x2968) 709 710/* Gen12 OAG unit */ 711#define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) 712#define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 713#define GEN12_OAG_OATAILPTR _MMIO(0xdb04) 714#define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 715 716#define GEN12_OAG_OABUFFER _MMIO(0xdb08) 717#define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) 718#define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) 719#define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ 720 721#define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) 722#define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 723#define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) 724#define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) 725 726#define GEN12_OAG_OACONTROL _MMIO(0xdaf4) 727#define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 728#define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) 729 730#define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) 731#define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 732#define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 733#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 734#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 735 736#define GEN12_OAG_OASTATUS _MMIO(0xdafc) 737#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) 738#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) 739#define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) 740 741/* 742 * Flexible, Aggregate EU Counter Registers. 743 * Note: these aren't contiguous 744 */ 745#define EU_PERF_CNTL0 _MMIO(0xe458) 746#define EU_PERF_CNTL1 _MMIO(0xe558) 747#define EU_PERF_CNTL2 _MMIO(0xe658) 748#define EU_PERF_CNTL3 _MMIO(0xe758) 749#define EU_PERF_CNTL4 _MMIO(0xe45c) 750#define EU_PERF_CNTL5 _MMIO(0xe55c) 751#define EU_PERF_CNTL6 _MMIO(0xe65c) 752 753/* 754 * OA Boolean state 755 */ 756 757#define OASTARTTRIG1 _MMIO(0x2710) 758#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 759#define OASTARTTRIG1_THRESHOLD_MASK 0xffff 760 761#define OASTARTTRIG2 _MMIO(0x2714) 762#define OASTARTTRIG2_INVERT_A_0 (1 << 0) 763#define OASTARTTRIG2_INVERT_A_1 (1 << 1) 764#define OASTARTTRIG2_INVERT_A_2 (1 << 2) 765#define OASTARTTRIG2_INVERT_A_3 (1 << 3) 766#define OASTARTTRIG2_INVERT_A_4 (1 << 4) 767#define OASTARTTRIG2_INVERT_A_5 (1 << 5) 768#define OASTARTTRIG2_INVERT_A_6 (1 << 6) 769#define OASTARTTRIG2_INVERT_A_7 (1 << 7) 770#define OASTARTTRIG2_INVERT_A_8 (1 << 8) 771#define OASTARTTRIG2_INVERT_A_9 (1 << 9) 772#define OASTARTTRIG2_INVERT_A_10 (1 << 10) 773#define OASTARTTRIG2_INVERT_A_11 (1 << 11) 774#define OASTARTTRIG2_INVERT_A_12 (1 << 12) 775#define OASTARTTRIG2_INVERT_A_13 (1 << 13) 776#define OASTARTTRIG2_INVERT_A_14 (1 << 14) 777#define OASTARTTRIG2_INVERT_A_15 (1 << 15) 778#define OASTARTTRIG2_INVERT_B_0 (1 << 16) 779#define OASTARTTRIG2_INVERT_B_1 (1 << 17) 780#define OASTARTTRIG2_INVERT_B_2 (1 << 18) 781#define OASTARTTRIG2_INVERT_B_3 (1 << 19) 782#define OASTARTTRIG2_INVERT_C_0 (1 << 20) 783#define OASTARTTRIG2_INVERT_C_1 (1 << 21) 784#define OASTARTTRIG2_INVERT_D_0 (1 << 22) 785#define OASTARTTRIG2_THRESHOLD_ENABLE (1 << 23) 786#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1 << 24) 787#define OASTARTTRIG2_EVENT_SELECT_0 (1 << 28) 788#define OASTARTTRIG2_EVENT_SELECT_1 (1 << 29) 789#define OASTARTTRIG2_EVENT_SELECT_2 (1 << 30) 790#define OASTARTTRIG2_EVENT_SELECT_3 (1 << 31) 791 792#define OASTARTTRIG3 _MMIO(0x2718) 793#define OASTARTTRIG3_NOA_SELECT_MASK 0xf 794#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 795#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 796#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 797#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 798#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 799#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 800#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 801#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 802 803#define OASTARTTRIG4 _MMIO(0x271c) 804#define OASTARTTRIG4_NOA_SELECT_MASK 0xf 805#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 806#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 807#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 808#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 809#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 810#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 811#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 812#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 813 814#define OASTARTTRIG5 _MMIO(0x2720) 815#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 816#define OASTARTTRIG5_THRESHOLD_MASK 0xffff 817 818#define OASTARTTRIG6 _MMIO(0x2724) 819#define OASTARTTRIG6_INVERT_A_0 (1 << 0) 820#define OASTARTTRIG6_INVERT_A_1 (1 << 1) 821#define OASTARTTRIG6_INVERT_A_2 (1 << 2) 822#define OASTARTTRIG6_INVERT_A_3 (1 << 3) 823#define OASTARTTRIG6_INVERT_A_4 (1 << 4) 824#define OASTARTTRIG6_INVERT_A_5 (1 << 5) 825#define OASTARTTRIG6_INVERT_A_6 (1 << 6) 826#define OASTARTTRIG6_INVERT_A_7 (1 << 7) 827#define OASTARTTRIG6_INVERT_A_8 (1 << 8) 828#define OASTARTTRIG6_INVERT_A_9 (1 << 9) 829#define OASTARTTRIG6_INVERT_A_10 (1 << 10) 830#define OASTARTTRIG6_INVERT_A_11 (1 << 11) 831#define OASTARTTRIG6_INVERT_A_12 (1 << 12) 832#define OASTARTTRIG6_INVERT_A_13 (1 << 13) 833#define OASTARTTRIG6_INVERT_A_14 (1 << 14) 834#define OASTARTTRIG6_INVERT_A_15 (1 << 15) 835#define OASTARTTRIG6_INVERT_B_0 (1 << 16) 836#define OASTARTTRIG6_INVERT_B_1 (1 << 17) 837#define OASTARTTRIG6_INVERT_B_2 (1 << 18) 838#define OASTARTTRIG6_INVERT_B_3 (1 << 19) 839#define OASTARTTRIG6_INVERT_C_0 (1 << 20) 840#define OASTARTTRIG6_INVERT_C_1 (1 << 21) 841#define OASTARTTRIG6_INVERT_D_0 (1 << 22) 842#define OASTARTTRIG6_THRESHOLD_ENABLE (1 << 23) 843#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1 << 24) 844#define OASTARTTRIG6_EVENT_SELECT_4 (1 << 28) 845#define OASTARTTRIG6_EVENT_SELECT_5 (1 << 29) 846#define OASTARTTRIG6_EVENT_SELECT_6 (1 << 30) 847#define OASTARTTRIG6_EVENT_SELECT_7 (1 << 31) 848 849#define OASTARTTRIG7 _MMIO(0x2728) 850#define OASTARTTRIG7_NOA_SELECT_MASK 0xf 851#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 852#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 853#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 854#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 855#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 856#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 857#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 858#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 859 860#define OASTARTTRIG8 _MMIO(0x272c) 861#define OASTARTTRIG8_NOA_SELECT_MASK 0xf 862#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 863#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 864#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 865#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 866#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 867#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 868#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 869#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 870 871#define OAREPORTTRIG1 _MMIO(0x2740) 872#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff 873#define OAREPORTTRIG1_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ 874 875#define OAREPORTTRIG2 _MMIO(0x2744) 876#define OAREPORTTRIG2_INVERT_A_0 (1 << 0) 877#define OAREPORTTRIG2_INVERT_A_1 (1 << 1) 878#define OAREPORTTRIG2_INVERT_A_2 (1 << 2) 879#define OAREPORTTRIG2_INVERT_A_3 (1 << 3) 880#define OAREPORTTRIG2_INVERT_A_4 (1 << 4) 881#define OAREPORTTRIG2_INVERT_A_5 (1 << 5) 882#define OAREPORTTRIG2_INVERT_A_6 (1 << 6) 883#define OAREPORTTRIG2_INVERT_A_7 (1 << 7) 884#define OAREPORTTRIG2_INVERT_A_8 (1 << 8) 885#define OAREPORTTRIG2_INVERT_A_9 (1 << 9) 886#define OAREPORTTRIG2_INVERT_A_10 (1 << 10) 887#define OAREPORTTRIG2_INVERT_A_11 (1 << 11) 888#define OAREPORTTRIG2_INVERT_A_12 (1 << 12) 889#define OAREPORTTRIG2_INVERT_A_13 (1 << 13) 890#define OAREPORTTRIG2_INVERT_A_14 (1 << 14) 891#define OAREPORTTRIG2_INVERT_A_15 (1 << 15) 892#define OAREPORTTRIG2_INVERT_B_0 (1 << 16) 893#define OAREPORTTRIG2_INVERT_B_1 (1 << 17) 894#define OAREPORTTRIG2_INVERT_B_2 (1 << 18) 895#define OAREPORTTRIG2_INVERT_B_3 (1 << 19) 896#define OAREPORTTRIG2_INVERT_C_0 (1 << 20) 897#define OAREPORTTRIG2_INVERT_C_1 (1 << 21) 898#define OAREPORTTRIG2_INVERT_D_0 (1 << 22) 899#define OAREPORTTRIG2_THRESHOLD_ENABLE (1 << 23) 900#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1 << 31) 901 902#define OAREPORTTRIG3 _MMIO(0x2748) 903#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf 904#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 905#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 906#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 907#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 908#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 909#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 910#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 911#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 912 913#define OAREPORTTRIG4 _MMIO(0x274c) 914#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf 915#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 916#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 917#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 918#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 919#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 920#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 921#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 922#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 923 924#define OAREPORTTRIG5 _MMIO(0x2750) 925#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff 926#define OAREPORTTRIG5_EDGE_LEVEL_TRIGGER_SELECT_MASK 0xffff0000 /* 0=level */ 927 928#define OAREPORTTRIG6 _MMIO(0x2754) 929#define OAREPORTTRIG6_INVERT_A_0 (1 << 0) 930#define OAREPORTTRIG6_INVERT_A_1 (1 << 1) 931#define OAREPORTTRIG6_INVERT_A_2 (1 << 2) 932#define OAREPORTTRIG6_INVERT_A_3 (1 << 3) 933#define OAREPORTTRIG6_INVERT_A_4 (1 << 4) 934#define OAREPORTTRIG6_INVERT_A_5 (1 << 5) 935#define OAREPORTTRIG6_INVERT_A_6 (1 << 6) 936#define OAREPORTTRIG6_INVERT_A_7 (1 << 7) 937#define OAREPORTTRIG6_INVERT_A_8 (1 << 8) 938#define OAREPORTTRIG6_INVERT_A_9 (1 << 9) 939#define OAREPORTTRIG6_INVERT_A_10 (1 << 10) 940#define OAREPORTTRIG6_INVERT_A_11 (1 << 11) 941#define OAREPORTTRIG6_INVERT_A_12 (1 << 12) 942#define OAREPORTTRIG6_INVERT_A_13 (1 << 13) 943#define OAREPORTTRIG6_INVERT_A_14 (1 << 14) 944#define OAREPORTTRIG6_INVERT_A_15 (1 << 15) 945#define OAREPORTTRIG6_INVERT_B_0 (1 << 16) 946#define OAREPORTTRIG6_INVERT_B_1 (1 << 17) 947#define OAREPORTTRIG6_INVERT_B_2 (1 << 18) 948#define OAREPORTTRIG6_INVERT_B_3 (1 << 19) 949#define OAREPORTTRIG6_INVERT_C_0 (1 << 20) 950#define OAREPORTTRIG6_INVERT_C_1 (1 << 21) 951#define OAREPORTTRIG6_INVERT_D_0 (1 << 22) 952#define OAREPORTTRIG6_THRESHOLD_ENABLE (1 << 23) 953#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1 << 31) 954 955#define OAREPORTTRIG7 _MMIO(0x2758) 956#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf 957#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 958#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 959#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 960#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 961#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 962#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 963#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 964#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 965 966#define OAREPORTTRIG8 _MMIO(0x275c) 967#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf 968#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 969#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 970#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 971#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 972#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 973#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 974#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 975#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 976 977/* Same layout as OASTARTTRIGX */ 978#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900) 979#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904) 980#define GEN12_OAG_OASTARTTRIG3 _MMIO(0xd908) 981#define GEN12_OAG_OASTARTTRIG4 _MMIO(0xd90c) 982#define GEN12_OAG_OASTARTTRIG5 _MMIO(0xd910) 983#define GEN12_OAG_OASTARTTRIG6 _MMIO(0xd914) 984#define GEN12_OAG_OASTARTTRIG7 _MMIO(0xd918) 985#define GEN12_OAG_OASTARTTRIG8 _MMIO(0xd91c) 986 987/* Same layout as OAREPORTTRIGX */ 988#define GEN12_OAG_OAREPORTTRIG1 _MMIO(0xd920) 989#define GEN12_OAG_OAREPORTTRIG2 _MMIO(0xd924) 990#define GEN12_OAG_OAREPORTTRIG3 _MMIO(0xd928) 991#define GEN12_OAG_OAREPORTTRIG4 _MMIO(0xd92c) 992#define GEN12_OAG_OAREPORTTRIG5 _MMIO(0xd930) 993#define GEN12_OAG_OAREPORTTRIG6 _MMIO(0xd934) 994#define GEN12_OAG_OAREPORTTRIG7 _MMIO(0xd938) 995#define GEN12_OAG_OAREPORTTRIG8 _MMIO(0xd93c) 996 997/* CECX_0 */ 998#define OACEC_COMPARE_LESS_OR_EQUAL 6 999#define OACEC_COMPARE_NOT_EQUAL 5 1000#define OACEC_COMPARE_LESS_THAN 4 1001#define OACEC_COMPARE_GREATER_OR_EQUAL 3 1002#define OACEC_COMPARE_EQUAL 2 1003#define OACEC_COMPARE_GREATER_THAN 1 1004#define OACEC_COMPARE_ANY_EQUAL 0 1005 1006#define OACEC_COMPARE_VALUE_MASK 0xffff 1007#define OACEC_COMPARE_VALUE_SHIFT 3 1008 1009#define OACEC_SELECT_NOA (0 << 19) 1010#define OACEC_SELECT_PREV (1 << 19) 1011#define OACEC_SELECT_BOOLEAN (2 << 19) 1012 1013/* 11-bit array 0: pass-through, 1: negated */ 1014#define GEN12_OASCEC_NEGATE_MASK 0x7ff 1015#define GEN12_OASCEC_NEGATE_SHIFT 21 1016 1017/* CECX_1 */ 1018#define OACEC_MASK_MASK 0xffff 1019#define OACEC_CONSIDERATIONS_MASK 0xffff 1020#define OACEC_CONSIDERATIONS_SHIFT 16 1021 1022#define OACEC0_0 _MMIO(0x2770) 1023#define OACEC0_1 _MMIO(0x2774) 1024#define OACEC1_0 _MMIO(0x2778) 1025#define OACEC1_1 _MMIO(0x277c) 1026#define OACEC2_0 _MMIO(0x2780) 1027#define OACEC2_1 _MMIO(0x2784) 1028#define OACEC3_0 _MMIO(0x2788) 1029#define OACEC3_1 _MMIO(0x278c) 1030#define OACEC4_0 _MMIO(0x2790) 1031#define OACEC4_1 _MMIO(0x2794) 1032#define OACEC5_0 _MMIO(0x2798) 1033#define OACEC5_1 _MMIO(0x279c) 1034#define OACEC6_0 _MMIO(0x27a0) 1035#define OACEC6_1 _MMIO(0x27a4) 1036#define OACEC7_0 _MMIO(0x27a8) 1037#define OACEC7_1 _MMIO(0x27ac) 1038 1039/* Same layout as CECX_Y */ 1040#define GEN12_OAG_CEC0_0 _MMIO(0xd940) 1041#define GEN12_OAG_CEC0_1 _MMIO(0xd944) 1042#define GEN12_OAG_CEC1_0 _MMIO(0xd948) 1043#define GEN12_OAG_CEC1_1 _MMIO(0xd94c) 1044#define GEN12_OAG_CEC2_0 _MMIO(0xd950) 1045#define GEN12_OAG_CEC2_1 _MMIO(0xd954) 1046#define GEN12_OAG_CEC3_0 _MMIO(0xd958) 1047#define GEN12_OAG_CEC3_1 _MMIO(0xd95c) 1048#define GEN12_OAG_CEC4_0 _MMIO(0xd960) 1049#define GEN12_OAG_CEC4_1 _MMIO(0xd964) 1050#define GEN12_OAG_CEC5_0 _MMIO(0xd968) 1051#define GEN12_OAG_CEC5_1 _MMIO(0xd96c) 1052#define GEN12_OAG_CEC6_0 _MMIO(0xd970) 1053#define GEN12_OAG_CEC6_1 _MMIO(0xd974) 1054#define GEN12_OAG_CEC7_0 _MMIO(0xd978) 1055#define GEN12_OAG_CEC7_1 _MMIO(0xd97c) 1056 1057/* Same layout as CECX_Y + negate 11-bit array */ 1058#define GEN12_OAG_SCEC0_0 _MMIO(0xdc00) 1059#define GEN12_OAG_SCEC0_1 _MMIO(0xdc04) 1060#define GEN12_OAG_SCEC1_0 _MMIO(0xdc08) 1061#define GEN12_OAG_SCEC1_1 _MMIO(0xdc0c) 1062#define GEN12_OAG_SCEC2_0 _MMIO(0xdc10) 1063#define GEN12_OAG_SCEC2_1 _MMIO(0xdc14) 1064#define GEN12_OAG_SCEC3_0 _MMIO(0xdc18) 1065#define GEN12_OAG_SCEC3_1 _MMIO(0xdc1c) 1066#define GEN12_OAG_SCEC4_0 _MMIO(0xdc20) 1067#define GEN12_OAG_SCEC4_1 _MMIO(0xdc24) 1068#define GEN12_OAG_SCEC5_0 _MMIO(0xdc28) 1069#define GEN12_OAG_SCEC5_1 _MMIO(0xdc2c) 1070#define GEN12_OAG_SCEC6_0 _MMIO(0xdc30) 1071#define GEN12_OAG_SCEC6_1 _MMIO(0xdc34) 1072#define GEN12_OAG_SCEC7_0 _MMIO(0xdc38) 1073#define GEN12_OAG_SCEC7_1 _MMIO(0xdc3c) 1074 1075/* OA perf counters */ 1076#define OA_PERFCNT1_LO _MMIO(0x91B8) 1077#define OA_PERFCNT1_HI _MMIO(0x91BC) 1078#define OA_PERFCNT2_LO _MMIO(0x91C0) 1079#define OA_PERFCNT2_HI _MMIO(0x91C4) 1080#define OA_PERFCNT3_LO _MMIO(0x91C8) 1081#define OA_PERFCNT3_HI _MMIO(0x91CC) 1082#define OA_PERFCNT4_LO _MMIO(0x91D8) 1083#define OA_PERFCNT4_HI _MMIO(0x91DC) 1084 1085#define OA_PERFMATRIX_LO _MMIO(0x91C8) 1086#define OA_PERFMATRIX_HI _MMIO(0x91CC) 1087 1088/* RPM unit config (Gen8+) */ 1089#define RPM_CONFIG0 _MMIO(0x0D00) 1090#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1091#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1092#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 1093#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 1094#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 1095#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 1096#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 1097#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 1098#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 1099#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 1100#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 1101#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 1102 1103#define RPM_CONFIG1 _MMIO(0x0D04) 1104#define GEN10_GT_NOA_ENABLE (1 << 9) 1105 1106/* GPM unit config (Gen9+) */ 1107#define CTC_MODE _MMIO(0xA26C) 1108#define CTC_SOURCE_PARAMETER_MASK 1 1109#define CTC_SOURCE_CRYSTAL_CLOCK 0 1110#define CTC_SOURCE_DIVIDE_LOGIC 1 1111#define CTC_SHIFT_PARAMETER_SHIFT 1 1112#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 1113 1114/* RCP unit config (Gen8+) */ 1115#define RCP_CONFIG _MMIO(0x0D08) 1116 1117/* NOA (HSW) */ 1118#define HSW_MBVID2_NOA0 _MMIO(0x9E80) 1119#define HSW_MBVID2_NOA1 _MMIO(0x9E84) 1120#define HSW_MBVID2_NOA2 _MMIO(0x9E88) 1121#define HSW_MBVID2_NOA3 _MMIO(0x9E8C) 1122#define HSW_MBVID2_NOA4 _MMIO(0x9E90) 1123#define HSW_MBVID2_NOA5 _MMIO(0x9E94) 1124#define HSW_MBVID2_NOA6 _MMIO(0x9E98) 1125#define HSW_MBVID2_NOA7 _MMIO(0x9E9C) 1126#define HSW_MBVID2_NOA8 _MMIO(0x9EA0) 1127#define HSW_MBVID2_NOA9 _MMIO(0x9EA4) 1128 1129#define HSW_MBVID2_MISR0 _MMIO(0x9EC0) 1130 1131/* NOA (Gen8+) */ 1132#define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) 1133 1134#define MICRO_BP0_0 _MMIO(0x9800) 1135#define MICRO_BP0_2 _MMIO(0x9804) 1136#define MICRO_BP0_1 _MMIO(0x9808) 1137 1138#define MICRO_BP1_0 _MMIO(0x980C) 1139#define MICRO_BP1_2 _MMIO(0x9810) 1140#define MICRO_BP1_1 _MMIO(0x9814) 1141 1142#define MICRO_BP2_0 _MMIO(0x9818) 1143#define MICRO_BP2_2 _MMIO(0x981C) 1144#define MICRO_BP2_1 _MMIO(0x9820) 1145 1146#define MICRO_BP3_0 _MMIO(0x9824) 1147#define MICRO_BP3_2 _MMIO(0x9828) 1148#define MICRO_BP3_1 _MMIO(0x982C) 1149 1150#define MICRO_BP_TRIGGER _MMIO(0x9830) 1151#define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 1152#define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 1153#define MICRO_BP_FIRED_ARMED _MMIO(0x983C) 1154 1155#define GEN12_OAA_DBG_REG _MMIO(0xdc44) 1156#define GEN12_OAG_OA_PESS _MMIO(0x2b2c) 1157#define GEN12_OAG_SPCTR_CNF _MMIO(0xdc40) 1158 1159#define GDT_CHICKEN_BITS _MMIO(0x9840) 1160#define GT_NOA_ENABLE 0x00000080 1161 1162#define NOA_DATA _MMIO(0x986C) 1163#define NOA_WRITE _MMIO(0x9888) 1164#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) 1165 1166#define _GEN7_PIPEA_DE_LOAD_SL 0x70068 1167#define _GEN7_PIPEB_DE_LOAD_SL 0x71068 1168#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 1169 1170/* 1171 * Reset registers 1172 */ 1173#define DEBUG_RESET_I830 _MMIO(0x6070) 1174#define DEBUG_RESET_FULL (1 << 7) 1175#define DEBUG_RESET_RENDER (1 << 8) 1176#define DEBUG_RESET_DISPLAY (1 << 9) 1177 1178/* 1179 * IOSF sideband 1180 */ 1181#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 1182#define IOSF_DEVFN_SHIFT 24 1183#define IOSF_OPCODE_SHIFT 16 1184#define IOSF_PORT_SHIFT 8 1185#define IOSF_BYTE_ENABLES_SHIFT 4 1186#define IOSF_BAR_SHIFT 1 1187#define IOSF_SB_BUSY (1 << 0) 1188#define IOSF_PORT_BUNIT 0x03 1189#define IOSF_PORT_PUNIT 0x04 1190#define IOSF_PORT_NC 0x11 1191#define IOSF_PORT_DPIO 0x12 1192#define IOSF_PORT_GPIO_NC 0x13 1193#define IOSF_PORT_CCK 0x14 1194#define IOSF_PORT_DPIO_2 0x1a 1195#define IOSF_PORT_FLISDSI 0x1b 1196#define IOSF_PORT_GPIO_SC 0x48 1197#define IOSF_PORT_GPIO_SUS 0xa8 1198#define IOSF_PORT_CCU 0xa9 1199#define CHV_IOSF_PORT_GPIO_N 0x13 1200#define CHV_IOSF_PORT_GPIO_SE 0x48 1201#define CHV_IOSF_PORT_GPIO_E 0xa8 1202#define CHV_IOSF_PORT_GPIO_SW 0xb2 1203#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 1204#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 1205 1206/* See configdb bunit SB addr map */ 1207#define BUNIT_REG_BISOC 0x11 1208 1209/* PUNIT_REG_*SSPM0 */ 1210#define _SSPM0_SSC(val) ((val) << 0) 1211#define SSPM0_SSC_MASK _SSPM0_SSC(0x3) 1212#define SSPM0_SSC_PWR_ON _SSPM0_SSC(0x0) 1213#define SSPM0_SSC_CLK_GATE _SSPM0_SSC(0x1) 1214#define SSPM0_SSC_RESET _SSPM0_SSC(0x2) 1215#define SSPM0_SSC_PWR_GATE _SSPM0_SSC(0x3) 1216#define _SSPM0_SSS(val) ((val) << 24) 1217#define SSPM0_SSS_MASK _SSPM0_SSS(0x3) 1218#define SSPM0_SSS_PWR_ON _SSPM0_SSS(0x0) 1219#define SSPM0_SSS_CLK_GATE _SSPM0_SSS(0x1) 1220#define SSPM0_SSS_RESET _SSPM0_SSS(0x2) 1221#define SSPM0_SSS_PWR_GATE _SSPM0_SSS(0x3) 1222 1223/* PUNIT_REG_*SSPM1 */ 1224#define SSPM1_FREQSTAT_SHIFT 24 1225#define SSPM1_FREQSTAT_MASK (0x1f << SSPM1_FREQSTAT_SHIFT) 1226#define SSPM1_FREQGUAR_SHIFT 8 1227#define SSPM1_FREQGUAR_MASK (0x1f << SSPM1_FREQGUAR_SHIFT) 1228#define SSPM1_FREQ_SHIFT 0 1229#define SSPM1_FREQ_MASK (0x1f << SSPM1_FREQ_SHIFT) 1230 1231#define PUNIT_REG_VEDSSPM0 0x32 1232#define PUNIT_REG_VEDSSPM1 0x33 1233 1234#define PUNIT_REG_DSPSSPM 0x36 1235#define DSPFREQSTAT_SHIFT_CHV 24 1236#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 1237#define DSPFREQGUAR_SHIFT_CHV 8 1238#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 1239#define DSPFREQSTAT_SHIFT 30 1240#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 1241#define DSPFREQGUAR_SHIFT 14 1242#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 1243#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */ 1244#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */ 1245#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */ 1246#define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 1247#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 1248#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 1249#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 1250#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 1251#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 1252#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 1253#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 1254#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 1255#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 1256#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 1257#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 1258 1259#define PUNIT_REG_ISPSSPM0 0x39 1260#define PUNIT_REG_ISPSSPM1 0x3a 1261 1262#define PUNIT_REG_PWRGT_CTRL 0x60 1263#define PUNIT_REG_PWRGT_STATUS 0x61 1264#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) 1265#define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) 1266#define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) 1267#define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) 1268#define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) 1269 1270#define PUNIT_PWGT_IDX_RENDER 0 1271#define PUNIT_PWGT_IDX_MEDIA 1 1272#define PUNIT_PWGT_IDX_DISP2D 3 1273#define PUNIT_PWGT_IDX_DPIO_CMN_BC 5 1274#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01 6 1275#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23 7 1276#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01 8 1277#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23 9 1278#define PUNIT_PWGT_IDX_DPIO_RX0 10 1279#define PUNIT_PWGT_IDX_DPIO_RX1 11 1280#define PUNIT_PWGT_IDX_DPIO_CMN_D 12 1281 1282#define PUNIT_REG_GPU_LFM 0xd3 1283#define PUNIT_REG_GPU_FREQ_REQ 0xd4 1284#define PUNIT_REG_GPU_FREQ_STS 0xd8 1285#define GPLLENABLE (1 << 4) 1286#define GENFREQSTATUS (1 << 0) 1287#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 1288#define PUNIT_REG_CZ_TIMESTAMP 0xce 1289 1290#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 1291#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 1292 1293#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136 1294#define FB_GFX_FREQ_FUSE_MASK 0xff 1295#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24 1296#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16 1297#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8 1298 1299#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137 1300#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8 1301 1302#define PUNIT_REG_DDR_SETUP2 0x139 1303#define FORCE_DDR_FREQ_REQ_ACK (1 << 8) 1304#define FORCE_DDR_LOW_FREQ (1 << 1) 1305#define FORCE_DDR_HIGH_FREQ (1 << 0) 1306 1307#define PUNIT_GPU_STATUS_REG 0xdb 1308#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 1309#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 1310#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 1311#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 1312 1313#define PUNIT_GPU_DUTYCYCLE_REG 0xdf 1314#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 1315#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 1316 1317#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 1318#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 1319#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 1320#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 1321#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 1322#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 1323#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 1324#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 1325#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 1326#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 1327 1328#define VLV_TURBO_SOC_OVERRIDE 0x04 1329#define VLV_OVERRIDE_EN 1 1330#define VLV_SOC_TDP_EN (1 << 1) 1331#define VLV_BIAS_CPU_125_SOC_875 (6 << 2) 1332#define CHV_BIAS_CPU_50_SOC_50 (3 << 2) 1333 1334/* vlv2 north clock has */ 1335#define CCK_FUSE_REG 0x8 1336#define CCK_FUSE_HPLL_FREQ_MASK 0x3 1337#define CCK_REG_DSI_PLL_FUSE 0x44 1338#define CCK_REG_DSI_PLL_CONTROL 0x48 1339#define DSI_PLL_VCO_EN (1 << 31) 1340#define DSI_PLL_LDO_GATE (1 << 30) 1341#define DSI_PLL_P1_POST_DIV_SHIFT 17 1342#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 1343#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 1344#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 1345#define DSI_PLL_MUX_MASK (3 << 9) 1346#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 1347#define DSI_PLL_MUX_DSI0_CCK (1 << 10) 1348#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 1349#define DSI_PLL_MUX_DSI1_CCK (1 << 9) 1350#define DSI_PLL_CLK_GATE_MASK (0xf << 5) 1351#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 1352#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 1353#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 1354#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 1355#define DSI_PLL_LOCK (1 << 0) 1356#define CCK_REG_DSI_PLL_DIVIDER 0x4c 1357#define DSI_PLL_LFSR (1 << 31) 1358#define DSI_PLL_FRACTION_EN (1 << 30) 1359#define DSI_PLL_FRAC_COUNTER_SHIFT 27 1360#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 1361#define DSI_PLL_USYNC_CNT_SHIFT 18 1362#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 1363#define DSI_PLL_N1_DIV_SHIFT 16 1364#define DSI_PLL_N1_DIV_MASK (3 << 16) 1365#define DSI_PLL_M1_DIV_SHIFT 0 1366#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 1367#define CCK_CZ_CLOCK_CONTROL 0x62 1368#define CCK_GPLL_CLOCK_CONTROL 0x67 1369#define CCK_DISPLAY_CLOCK_CONTROL 0x6b 1370#define CCK_DISPLAY_REF_CLOCK_CONTROL 0x6c 1371#define CCK_TRUNK_FORCE_ON (1 << 17) 1372#define CCK_TRUNK_FORCE_OFF (1 << 16) 1373#define CCK_FREQUENCY_STATUS (0x1f << 8) 1374#define CCK_FREQUENCY_STATUS_SHIFT 8 1375#define CCK_FREQUENCY_VALUES (0x1f << 0) 1376 1377/* DPIO registers */ 1378#define DPIO_DEVFN 0 1379 1380#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 1381#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 1382#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 1383#define DPIO_SFR_BYPASS (1 << 1) 1384#define DPIO_CMNRST (1 << 0) 1385 1386#define DPIO_PHY(pipe) ((pipe) >> 1) 1387 1388/* 1389 * Per pipe/PLL DPIO regs 1390 */ 1391#define _VLV_PLL_DW3_CH0 0x800c 1392#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 1393#define DPIO_POST_DIV_DAC 0 1394#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 1395#define DPIO_POST_DIV_LVDS1 2 1396#define DPIO_POST_DIV_LVDS2 3 1397#define DPIO_K_SHIFT (24) /* 4 bits */ 1398#define DPIO_P1_SHIFT (21) /* 3 bits */ 1399#define DPIO_P2_SHIFT (16) /* 5 bits */ 1400#define DPIO_N_SHIFT (12) /* 4 bits */ 1401#define DPIO_ENABLE_CALIBRATION (1 << 11) 1402#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 1403#define DPIO_M2DIV_MASK 0xff 1404#define _VLV_PLL_DW3_CH1 0x802c 1405#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 1406 1407#define _VLV_PLL_DW5_CH0 0x8014 1408#define DPIO_REFSEL_OVERRIDE 27 1409#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 1410#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 1411#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 1412#define DPIO_PLL_REFCLK_SEL_MASK 3 1413#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 1414#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 1415#define _VLV_PLL_DW5_CH1 0x8034 1416#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 1417 1418#define _VLV_PLL_DW7_CH0 0x801c 1419#define _VLV_PLL_DW7_CH1 0x803c 1420#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 1421 1422#define _VLV_PLL_DW8_CH0 0x8040 1423#define _VLV_PLL_DW8_CH1 0x8060 1424#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 1425 1426#define VLV_PLL_DW9_BCAST 0xc044 1427#define _VLV_PLL_DW9_CH0 0x8044 1428#define _VLV_PLL_DW9_CH1 0x8064 1429#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 1430 1431#define _VLV_PLL_DW10_CH0 0x8048 1432#define _VLV_PLL_DW10_CH1 0x8068 1433#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 1434 1435#define _VLV_PLL_DW11_CH0 0x804c 1436#define _VLV_PLL_DW11_CH1 0x806c 1437#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 1438 1439/* Spec for ref block start counts at DW10 */ 1440#define VLV_REF_DW13 0x80ac 1441 1442#define VLV_CMN_DW0 0x8100 1443 1444/* 1445 * Per DDI channel DPIO regs 1446 */ 1447 1448#define _VLV_PCS_DW0_CH0 0x8200 1449#define _VLV_PCS_DW0_CH1 0x8400 1450#define DPIO_PCS_TX_LANE2_RESET (1 << 16) 1451#define DPIO_PCS_TX_LANE1_RESET (1 << 7) 1452#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 1453#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 1454#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 1455 1456#define _VLV_PCS01_DW0_CH0 0x200 1457#define _VLV_PCS23_DW0_CH0 0x400 1458#define _VLV_PCS01_DW0_CH1 0x2600 1459#define _VLV_PCS23_DW0_CH1 0x2800 1460#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 1461#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 1462 1463#define _VLV_PCS_DW1_CH0 0x8204 1464#define _VLV_PCS_DW1_CH1 0x8404 1465#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 1466#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 1467#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 1468#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 1469#define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 1470#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 1471 1472#define _VLV_PCS01_DW1_CH0 0x204 1473#define _VLV_PCS23_DW1_CH0 0x404 1474#define _VLV_PCS01_DW1_CH1 0x2604 1475#define _VLV_PCS23_DW1_CH1 0x2804 1476#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 1477#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 1478 1479#define _VLV_PCS_DW8_CH0 0x8220 1480#define _VLV_PCS_DW8_CH1 0x8420 1481#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 1482#define CHV_PCS_USEDCLKCHANNEL (1 << 21) 1483#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 1484 1485#define _VLV_PCS01_DW8_CH0 0x0220 1486#define _VLV_PCS23_DW8_CH0 0x0420 1487#define _VLV_PCS01_DW8_CH1 0x2620 1488#define _VLV_PCS23_DW8_CH1 0x2820 1489#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 1490#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 1491 1492#define _VLV_PCS_DW9_CH0 0x8224 1493#define _VLV_PCS_DW9_CH1 0x8424 1494#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 1495#define DPIO_PCS_TX2MARGIN_000 (0 << 13) 1496#define DPIO_PCS_TX2MARGIN_101 (1 << 13) 1497#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 1498#define DPIO_PCS_TX1MARGIN_000 (0 << 10) 1499#define DPIO_PCS_TX1MARGIN_101 (1 << 10) 1500#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 1501 1502#define _VLV_PCS01_DW9_CH0 0x224 1503#define _VLV_PCS23_DW9_CH0 0x424 1504#define _VLV_PCS01_DW9_CH1 0x2624 1505#define _VLV_PCS23_DW9_CH1 0x2824 1506#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 1507#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 1508 1509#define _CHV_PCS_DW10_CH0 0x8228 1510#define _CHV_PCS_DW10_CH1 0x8428 1511#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 1512#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 1513#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 1514#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 1515#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 1516#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 1517#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 1518#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 1519#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 1520 1521#define _VLV_PCS01_DW10_CH0 0x0228 1522#define _VLV_PCS23_DW10_CH0 0x0428 1523#define _VLV_PCS01_DW10_CH1 0x2628 1524#define _VLV_PCS23_DW10_CH1 0x2828 1525#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 1526#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 1527 1528#define _VLV_PCS_DW11_CH0 0x822c 1529#define _VLV_PCS_DW11_CH1 0x842c 1530#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 1531#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 1532#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 1533#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 1534#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 1535 1536#define _VLV_PCS01_DW11_CH0 0x022c 1537#define _VLV_PCS23_DW11_CH0 0x042c 1538#define _VLV_PCS01_DW11_CH1 0x262c 1539#define _VLV_PCS23_DW11_CH1 0x282c 1540#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 1541#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 1542 1543#define _VLV_PCS01_DW12_CH0 0x0230 1544#define _VLV_PCS23_DW12_CH0 0x0430 1545#define _VLV_PCS01_DW12_CH1 0x2630 1546#define _VLV_PCS23_DW12_CH1 0x2830 1547#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 1548#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 1549 1550#define _VLV_PCS_DW12_CH0 0x8230 1551#define _VLV_PCS_DW12_CH1 0x8430 1552#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 1553#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 1554#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 1555#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 1556#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 1557#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 1558 1559#define _VLV_PCS_DW14_CH0 0x8238 1560#define _VLV_PCS_DW14_CH1 0x8438 1561#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 1562 1563#define _VLV_PCS_DW23_CH0 0x825c 1564#define _VLV_PCS_DW23_CH1 0x845c 1565#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 1566 1567#define _VLV_TX_DW2_CH0 0x8288 1568#define _VLV_TX_DW2_CH1 0x8488 1569#define DPIO_SWING_MARGIN000_SHIFT 16 1570#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 1571#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 1572#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 1573 1574#define _VLV_TX_DW3_CH0 0x828c 1575#define _VLV_TX_DW3_CH1 0x848c 1576/* The following bit for CHV phy */ 1577#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 1578#define DPIO_SWING_MARGIN101_SHIFT 16 1579#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 1580#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 1581 1582#define _VLV_TX_DW4_CH0 0x8290 1583#define _VLV_TX_DW4_CH1 0x8490 1584#define DPIO_SWING_DEEMPH9P5_SHIFT 24 1585#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 1586#define DPIO_SWING_DEEMPH6P0_SHIFT 16 1587#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 1588#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 1589 1590#define _VLV_TX3_DW4_CH0 0x690 1591#define _VLV_TX3_DW4_CH1 0x2a90 1592#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 1593 1594#define _VLV_TX_DW5_CH0 0x8294 1595#define _VLV_TX_DW5_CH1 0x8494 1596#define DPIO_TX_OCALINIT_EN (1 << 31) 1597#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 1598 1599#define _VLV_TX_DW11_CH0 0x82ac 1600#define _VLV_TX_DW11_CH1 0x84ac 1601#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 1602 1603#define _VLV_TX_DW14_CH0 0x82b8 1604#define _VLV_TX_DW14_CH1 0x84b8 1605#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 1606 1607/* CHV dpPhy registers */ 1608#define _CHV_PLL_DW0_CH0 0x8000 1609#define _CHV_PLL_DW0_CH1 0x8180 1610#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 1611 1612#define _CHV_PLL_DW1_CH0 0x8004 1613#define _CHV_PLL_DW1_CH1 0x8184 1614#define DPIO_CHV_N_DIV_SHIFT 8 1615#define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 1616#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 1617 1618#define _CHV_PLL_DW2_CH0 0x8008 1619#define _CHV_PLL_DW2_CH1 0x8188 1620#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 1621 1622#define _CHV_PLL_DW3_CH0 0x800c 1623#define _CHV_PLL_DW3_CH1 0x818c 1624#define DPIO_CHV_FRAC_DIV_EN (1 << 16) 1625#define DPIO_CHV_FIRST_MOD (0 << 8) 1626#define DPIO_CHV_SECOND_MOD (1 << 8) 1627#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 1628#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 1629#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 1630 1631#define _CHV_PLL_DW6_CH0 0x8018 1632#define _CHV_PLL_DW6_CH1 0x8198 1633#define DPIO_CHV_GAIN_CTRL_SHIFT 16 1634#define DPIO_CHV_INT_COEFF_SHIFT 8 1635#define DPIO_CHV_PROP_COEFF_SHIFT 0 1636#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 1637 1638#define _CHV_PLL_DW8_CH0 0x8020 1639#define _CHV_PLL_DW8_CH1 0x81A0 1640#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 1641#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 1642#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 1643 1644#define _CHV_PLL_DW9_CH0 0x8024 1645#define _CHV_PLL_DW9_CH1 0x81A4 1646#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 1647#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 1648#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 1649#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 1650 1651#define _CHV_CMN_DW0_CH0 0x8100 1652#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 1653#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 1654#define DPIO_ALLDL_POWERDOWN (1 << 1) 1655#define DPIO_ANYDL_POWERDOWN (1 << 0) 1656 1657#define _CHV_CMN_DW5_CH0 0x8114 1658#define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 1659#define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 1660#define CHV_BUFRIGHTENA1_FORCE (3 << 20) 1661#define CHV_BUFRIGHTENA1_MASK (3 << 20) 1662#define CHV_BUFLEFTENA1_DISABLE (0 << 22) 1663#define CHV_BUFLEFTENA1_NORMAL (1 << 22) 1664#define CHV_BUFLEFTENA1_FORCE (3 << 22) 1665#define CHV_BUFLEFTENA1_MASK (3 << 22) 1666 1667#define _CHV_CMN_DW13_CH0 0x8134 1668#define _CHV_CMN_DW0_CH1 0x8080 1669#define DPIO_CHV_S1_DIV_SHIFT 21 1670#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 1671#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 1672#define DPIO_CHV_K_DIV_SHIFT 4 1673#define DPIO_PLL_FREQLOCK (1 << 1) 1674#define DPIO_PLL_LOCK (1 << 0) 1675#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 1676 1677#define _CHV_CMN_DW14_CH0 0x8138 1678#define _CHV_CMN_DW1_CH1 0x8084 1679#define DPIO_AFC_RECAL (1 << 14) 1680#define DPIO_DCLKP_EN (1 << 13) 1681#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 1682#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 1683#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 1684#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 1685#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 1686#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 1687#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 1688#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 1689#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 1690 1691#define _CHV_CMN_DW19_CH0 0x814c 1692#define _CHV_CMN_DW6_CH1 0x8098 1693#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 1694#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 1695#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 1696#define CHV_CMN_USEDCLKCHANNEL (1 << 13) 1697 1698#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 1699 1700#define CHV_CMN_DW28 0x8170 1701#define DPIO_CL1POWERDOWNEN (1 << 23) 1702#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 1703#define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 1704#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 1705#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 1706#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 1707 1708#define CHV_CMN_DW30 0x8178 1709#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 1710#define DPIO_LRC_BYPASS (1 << 3) 1711 1712#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 1713 (lane) * 0x200 + (offset)) 1714 1715#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 1716#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 1717#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 1718#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 1719#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 1720#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 1721#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 1722#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 1723#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 1724#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 1725#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 1726#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 1727#define DPIO_FRC_LATENCY_SHFIT 8 1728#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 1729#define DPIO_UPAR_SHIFT 30 1730 1731/* BXT PHY registers */ 1732#define _BXT_PHY0_BASE 0x6C000 1733#define _BXT_PHY1_BASE 0x162000 1734#define _BXT_PHY2_BASE 0x163000 1735#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 1736 _BXT_PHY1_BASE, \ 1737 _BXT_PHY2_BASE) 1738 1739#define _BXT_PHY(phy, reg) \ 1740 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 1741 1742#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1743 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 1744 (reg_ch1) - _BXT_PHY0_BASE)) 1745#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 1746 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 1747 1748#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 1749#define MIPIO_RST_CTRL (1 << 2) 1750 1751#define _BXT_PHY_CTL_DDI_A 0x64C00 1752#define _BXT_PHY_CTL_DDI_B 0x64C10 1753#define _BXT_PHY_CTL_DDI_C 0x64C20 1754#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 1755#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 1756#define BXT_PHY_LANE_ENABLED (1 << 8) 1757#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 1758 _BXT_PHY_CTL_DDI_B) 1759 1760#define _PHY_CTL_FAMILY_EDP 0x64C80 1761#define _PHY_CTL_FAMILY_DDI 0x64C90 1762#define _PHY_CTL_FAMILY_DDI_C 0x64CA0 1763#define COMMON_RESET_DIS (1 << 31) 1764#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 1765 _PHY_CTL_FAMILY_EDP, \ 1766 _PHY_CTL_FAMILY_DDI_C) 1767 1768/* BXT PHY PLL registers */ 1769#define _PORT_PLL_A 0x46074 1770#define _PORT_PLL_B 0x46078 1771#define _PORT_PLL_C 0x4607c 1772#define PORT_PLL_ENABLE (1 << 31) 1773#define PORT_PLL_LOCK (1 << 30) 1774#define PORT_PLL_REF_SEL (1 << 27) 1775#define PORT_PLL_POWER_ENABLE (1 << 26) 1776#define PORT_PLL_POWER_STATE (1 << 25) 1777#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 1778 1779#define _PORT_PLL_EBB_0_A 0x162034 1780#define _PORT_PLL_EBB_0_B 0x6C034 1781#define _PORT_PLL_EBB_0_C 0x6C340 1782#define PORT_PLL_P1_SHIFT 13 1783#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT) 1784#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT) 1785#define PORT_PLL_P2_SHIFT 8 1786#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT) 1787#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT) 1788#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1789 _PORT_PLL_EBB_0_B, \ 1790 _PORT_PLL_EBB_0_C) 1791 1792#define _PORT_PLL_EBB_4_A 0x162038 1793#define _PORT_PLL_EBB_4_B 0x6C038 1794#define _PORT_PLL_EBB_4_C 0x6C344 1795#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13) 1796#define PORT_PLL_RECALIBRATE (1 << 14) 1797#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 1798 _PORT_PLL_EBB_4_B, \ 1799 _PORT_PLL_EBB_4_C) 1800 1801#define _PORT_PLL_0_A 0x162100 1802#define _PORT_PLL_0_B 0x6C100 1803#define _PORT_PLL_0_C 0x6C380 1804/* PORT_PLL_0_A */ 1805#define PORT_PLL_M2_MASK 0xFF 1806/* PORT_PLL_1_A */ 1807#define PORT_PLL_N_SHIFT 8 1808#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT) 1809#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT) 1810/* PORT_PLL_2_A */ 1811#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF 1812/* PORT_PLL_3_A */ 1813#define PORT_PLL_M2_FRAC_ENABLE (1 << 16) 1814/* PORT_PLL_6_A */ 1815#define PORT_PLL_PROP_COEFF_MASK 0xF 1816#define PORT_PLL_INT_COEFF_MASK (0x1F << 8) 1817#define PORT_PLL_INT_COEFF(x) ((x) << 8) 1818#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16) 1819#define PORT_PLL_GAIN_CTL(x) ((x) << 16) 1820/* PORT_PLL_8_A */ 1821#define PORT_PLL_TARGET_CNT_MASK 0x3FF 1822/* PORT_PLL_9_A */ 1823#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1 1824#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT) 1825/* PORT_PLL_10_A */ 1826#define PORT_PLL_DCO_AMP_OVR_EN_H (1 << 27) 1827#define PORT_PLL_DCO_AMP_DEFAULT 15 1828#define PORT_PLL_DCO_AMP_MASK 0x3c00 1829#define PORT_PLL_DCO_AMP(x) ((x) << 10) 1830#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 1831 _PORT_PLL_0_B, \ 1832 _PORT_PLL_0_C) 1833#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 1834 (idx) * 4) 1835 1836/* BXT PHY common lane registers */ 1837#define _PORT_CL1CM_DW0_A 0x162000 1838#define _PORT_CL1CM_DW0_BC 0x6C000 1839#define PHY_POWER_GOOD (1 << 16) 1840#define PHY_RESERVED (1 << 7) 1841#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 1842 1843#define _PORT_CL1CM_DW9_A 0x162024 1844#define _PORT_CL1CM_DW9_BC 0x6C024 1845#define IREF0RC_OFFSET_SHIFT 8 1846#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 1847#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 1848 1849#define _PORT_CL1CM_DW10_A 0x162028 1850#define _PORT_CL1CM_DW10_BC 0x6C028 1851#define IREF1RC_OFFSET_SHIFT 8 1852#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 1853#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 1854 1855#define _PORT_CL1CM_DW28_A 0x162070 1856#define _PORT_CL1CM_DW28_BC 0x6C070 1857#define OCL1_POWER_DOWN_EN (1 << 23) 1858#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 1859#define SUS_CLK_CONFIG 0x3 1860#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 1861 1862#define _PORT_CL1CM_DW30_A 0x162078 1863#define _PORT_CL1CM_DW30_BC 0x6C078 1864#define OCL2_LDOFUSE_PWR_DIS (1 << 6) 1865#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 1866 1867/* 1868 * CNL/ICL Port/COMBO-PHY Registers 1869 */ 1870#define _ICL_COMBOPHY_A 0x162000 1871#define _ICL_COMBOPHY_B 0x6C000 1872#define _EHL_COMBOPHY_C 0x160000 1873#define _RKL_COMBOPHY_D 0x161000 1874#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ 1875 _ICL_COMBOPHY_B, \ 1876 _EHL_COMBOPHY_C, \ 1877 _RKL_COMBOPHY_D) 1878 1879/* CNL/ICL Port CL_DW registers */ 1880#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 1881 4 * (dw)) 1882 1883#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014) 1884#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) 1885#define CL_POWER_DOWN_ENABLE (1 << 4) 1886#define SUS_CLOCK_CONFIG (3 << 0) 1887 1888#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) 1889#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25) 1890#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25 1891#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24) 1892#define PWR_UP_ALL_LANES (0x0 << 4) 1893#define PWR_DOWN_LN_3_2_1 (0xe << 4) 1894#define PWR_DOWN_LN_3_2 (0xc << 4) 1895#define PWR_DOWN_LN_3 (0x8 << 4) 1896#define PWR_DOWN_LN_2_1_0 (0x7 << 4) 1897#define PWR_DOWN_LN_1_0 (0x3 << 4) 1898#define PWR_DOWN_LN_3_1 (0xa << 4) 1899#define PWR_DOWN_LN_3_1_0 (0xb << 4) 1900#define PWR_DOWN_LN_MASK (0xf << 4) 1901#define PWR_DOWN_LN_SHIFT 4 1902#define EDP4K2K_MODE_OVRD_EN (1 << 3) 1903#define EDP4K2K_MODE_OVRD_OPTIMIZED (1 << 2) 1904 1905#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) 1906#define ICL_LANE_ENABLE_AUX (1 << 0) 1907 1908/* CNL/ICL Port COMP_DW registers */ 1909#define _ICL_PORT_COMP 0x100 1910#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 1911 _ICL_PORT_COMP + 4 * (dw)) 1912 1913#define CNL_PORT_COMP_DW0 _MMIO(0x162100) 1914#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) 1915#define COMP_INIT (1 << 31) 1916 1917#define CNL_PORT_COMP_DW1 _MMIO(0x162104) 1918#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) 1919 1920#define CNL_PORT_COMP_DW3 _MMIO(0x16210c) 1921#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) 1922#define PROCESS_INFO_DOT_0 (0 << 26) 1923#define PROCESS_INFO_DOT_1 (1 << 26) 1924#define PROCESS_INFO_DOT_4 (2 << 26) 1925#define PROCESS_INFO_MASK (7 << 26) 1926#define PROCESS_INFO_SHIFT 26 1927#define VOLTAGE_INFO_0_85V (0 << 24) 1928#define VOLTAGE_INFO_0_95V (1 << 24) 1929#define VOLTAGE_INFO_1_05V (2 << 24) 1930#define VOLTAGE_INFO_MASK (3 << 24) 1931#define VOLTAGE_INFO_SHIFT 24 1932 1933#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) 1934#define IREFGEN (1 << 24) 1935 1936#define CNL_PORT_COMP_DW9 _MMIO(0x162124) 1937#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) 1938 1939#define CNL_PORT_COMP_DW10 _MMIO(0x162128) 1940#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) 1941 1942/* CNL/ICL Port PCS registers */ 1943#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304 1944#define _CNL_PORT_PCS_DW1_GRP_B 0x162384 1945#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04 1946#define _CNL_PORT_PCS_DW1_GRP_D 0x162B84 1947#define _CNL_PORT_PCS_DW1_GRP_F 0x162A04 1948#define _CNL_PORT_PCS_DW1_LN0_AE 0x162404 1949#define _CNL_PORT_PCS_DW1_LN0_B 0x162604 1950#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 1951#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 1952#define _CNL_PORT_PCS_DW1_LN0_F 0x162804 1953#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \ 1954 _CNL_PORT_PCS_DW1_GRP_AE, \ 1955 _CNL_PORT_PCS_DW1_GRP_B, \ 1956 _CNL_PORT_PCS_DW1_GRP_C, \ 1957 _CNL_PORT_PCS_DW1_GRP_D, \ 1958 _CNL_PORT_PCS_DW1_GRP_AE, \ 1959 _CNL_PORT_PCS_DW1_GRP_F)) 1960#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \ 1961 _CNL_PORT_PCS_DW1_LN0_AE, \ 1962 _CNL_PORT_PCS_DW1_LN0_B, \ 1963 _CNL_PORT_PCS_DW1_LN0_C, \ 1964 _CNL_PORT_PCS_DW1_LN0_D, \ 1965 _CNL_PORT_PCS_DW1_LN0_AE, \ 1966 _CNL_PORT_PCS_DW1_LN0_F)) 1967 1968#define _ICL_PORT_PCS_AUX 0x300 1969#define _ICL_PORT_PCS_GRP 0x600 1970#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 1971#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 1972 _ICL_PORT_PCS_AUX + 4 * (dw)) 1973#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 1974 _ICL_PORT_PCS_GRP + 4 * (dw)) 1975#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 1976 _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 1977#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) 1978#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) 1979#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy)) 1980#define DCC_MODE_SELECT_MASK (0x3 << 20) 1981#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20) 1982#define COMMON_KEEPER_EN (1 << 26) 1983#define LATENCY_OPTIM_MASK (0x3 << 2) 1984#define LATENCY_OPTIM_VAL(x) ((x) << 2) 1985 1986/* CNL/ICL Port TX registers */ 1987#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 1988#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 1989#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 1990#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 1991#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 1992#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 1993#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 1994#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 1995#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 1996#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 1997#define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \ 1998 _CNL_PORT_TX_AE_GRP_OFFSET, \ 1999 _CNL_PORT_TX_B_GRP_OFFSET, \ 2000 _CNL_PORT_TX_B_GRP_OFFSET, \ 2001 _CNL_PORT_TX_D_GRP_OFFSET, \ 2002 _CNL_PORT_TX_AE_GRP_OFFSET, \ 2003 _CNL_PORT_TX_F_GRP_OFFSET) + \ 2004 4 * (dw)) 2005#define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \ 2006 _CNL_PORT_TX_AE_LN0_OFFSET, \ 2007 _CNL_PORT_TX_B_LN0_OFFSET, \ 2008 _CNL_PORT_TX_B_LN0_OFFSET, \ 2009 _CNL_PORT_TX_D_LN0_OFFSET, \ 2010 _CNL_PORT_TX_AE_LN0_OFFSET, \ 2011 _CNL_PORT_TX_F_LN0_OFFSET) + \ 2012 4 * (dw)) 2013 2014#define _ICL_PORT_TX_AUX 0x380 2015#define _ICL_PORT_TX_GRP 0x680 2016#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 2017 2018#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 2019 _ICL_PORT_TX_AUX + 4 * (dw)) 2020#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 2021 _ICL_PORT_TX_GRP + 4 * (dw)) 2022#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 2023 _ICL_PORT_TX_LN(ln) + 4 * (dw)) 2024 2025#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port)) 2026#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port)) 2027#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) 2028#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) 2029#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy)) 2030#define SWING_SEL_UPPER(x) (((x) >> 3) << 15) 2031#define SWING_SEL_UPPER_MASK (1 << 15) 2032#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11) 2033#define SWING_SEL_LOWER_MASK (0x7 << 11) 2034#define FRC_LATENCY_OPTIM_MASK (0x7 << 8) 2035#define FRC_LATENCY_OPTIM_VAL(x) ((x) << 8) 2036#define RCOMP_SCALAR(x) ((x) << 0) 2037#define RCOMP_SCALAR_MASK (0xFF << 0) 2038 2039#define _CNL_PORT_TX_DW4_LN0_AE 0x162450 2040#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 2041#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) 2042#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) 2043#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ 2044 ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ 2045 _CNL_PORT_TX_DW4_LN0_AE))) 2046#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) 2047#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) 2048#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy)) 2049#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) 2050#define LOADGEN_SELECT (1 << 31) 2051#define POST_CURSOR_1(x) ((x) << 12) 2052#define POST_CURSOR_1_MASK (0x3F << 12) 2053#define POST_CURSOR_2(x) ((x) << 6) 2054#define POST_CURSOR_2_MASK (0x3F << 6) 2055#define CURSOR_COEFF(x) ((x) << 0) 2056#define CURSOR_COEFF_MASK (0x3F << 0) 2057 2058#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port)) 2059#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port)) 2060#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) 2061#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) 2062#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy)) 2063#define TX_TRAINING_EN (1 << 31) 2064#define TAP2_DISABLE (1 << 30) 2065#define TAP3_DISABLE (1 << 29) 2066#define SCALING_MODE_SEL(x) ((x) << 18) 2067#define SCALING_MODE_SEL_MASK (0x7 << 18) 2068#define RTERM_SELECT(x) ((x) << 3) 2069#define RTERM_SELECT_MASK (0x7 << 3) 2070 2071#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port))) 2072#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port))) 2073#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) 2074#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) 2075#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy)) 2076#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) 2077#define N_SCALAR(x) ((x) << 24) 2078#define N_SCALAR_MASK (0x7F << 24) 2079 2080#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy)) 2081#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) 2082#define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy)) 2083#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) 2084#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) 2085#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) 2086 2087#define _ICL_DPHY_CHKN_REG 0x194 2088#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) 2089#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) 2090 2091#define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ 2092 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) 2093 2094#define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C 2095#define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C 2096#define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C 2097#define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C 2098#define MG_TX_LINK_PARAMS_TX1LN0_PORT3 0x16A12C 2099#define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C 2100#define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C 2101#define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C 2102#define MG_TX1_LINK_PARAMS(ln, tc_port) \ 2103 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ 2104 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ 2105 MG_TX_LINK_PARAMS_TX1LN1_PORT1) 2106 2107#define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC 2108#define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC 2109#define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC 2110#define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC 2111#define MG_TX_LINK_PARAMS_TX2LN0_PORT3 0x16A0AC 2112#define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC 2113#define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC 2114#define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC 2115#define MG_TX2_LINK_PARAMS(ln, tc_port) \ 2116 MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ 2117 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ 2118 MG_TX_LINK_PARAMS_TX2LN1_PORT1) 2119#define CRI_USE_FS32 (1 << 5) 2120 2121#define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C 2122#define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C 2123#define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C 2124#define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C 2125#define MG_TX_PISO_READLOAD_TX1LN0_PORT3 0x16A14C 2126#define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C 2127#define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C 2128#define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C 2129#define MG_TX1_PISO_READLOAD(ln, tc_port) \ 2130 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ 2131 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ 2132 MG_TX_PISO_READLOAD_TX1LN1_PORT1) 2133 2134#define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC 2135#define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC 2136#define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC 2137#define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC 2138#define MG_TX_PISO_READLOAD_TX2LN0_PORT3 0x16A0CC 2139#define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC 2140#define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC 2141#define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC 2142#define MG_TX2_PISO_READLOAD(ln, tc_port) \ 2143 MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ 2144 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ 2145 MG_TX_PISO_READLOAD_TX2LN1_PORT1) 2146#define CRI_CALCINIT (1 << 1) 2147 2148#define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 2149#define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 2150#define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 2151#define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 2152#define MG_TX_SWINGCTRL_TX1LN0_PORT3 0x16A148 2153#define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 2154#define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 2155#define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 2156#define MG_TX1_SWINGCTRL(ln, tc_port) \ 2157 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ 2158 MG_TX_SWINGCTRL_TX1LN0_PORT2, \ 2159 MG_TX_SWINGCTRL_TX1LN1_PORT1) 2160 2161#define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 2162#define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 2163#define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 2164#define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 2165#define MG_TX_SWINGCTRL_TX2LN0_PORT3 0x16A0C8 2166#define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 2167#define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 2168#define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 2169#define MG_TX2_SWINGCTRL(ln, tc_port) \ 2170 MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ 2171 MG_TX_SWINGCTRL_TX2LN0_PORT2, \ 2172 MG_TX_SWINGCTRL_TX2LN1_PORT1) 2173#define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) 2174#define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) 2175 2176#define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 2177#define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 2178#define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 2179#define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 2180#define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 2181#define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 2182#define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 2183#define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 2184#define MG_TX1_DRVCTRL(ln, tc_port) \ 2185 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ 2186 MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ 2187 MG_TX_DRVCTRL_TX1LN1_TXPORT1) 2188 2189#define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 2190#define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 2191#define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 2192#define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 2193#define MG_TX_DRVCTRL_TX2LN0_PORT3 0x16A0C4 2194#define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 2195#define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 2196#define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 2197#define MG_TX2_DRVCTRL(ln, tc_port) \ 2198 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ 2199 MG_TX_DRVCTRL_TX2LN0_PORT2, \ 2200 MG_TX_DRVCTRL_TX2LN1_PORT1) 2201#define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) 2202#define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) 2203#define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) 2204#define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) 2205#define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) 2206#define CRI_LOADGEN_SEL(x) ((x) << 12) 2207#define CRI_LOADGEN_SEL_MASK (0x3 << 12) 2208 2209#define MG_CLKHUB_LN0_PORT1 0x16839C 2210#define MG_CLKHUB_LN1_PORT1 0x16879C 2211#define MG_CLKHUB_LN0_PORT2 0x16939C 2212#define MG_CLKHUB_LN1_PORT2 0x16979C 2213#define MG_CLKHUB_LN0_PORT3 0x16A39C 2214#define MG_CLKHUB_LN1_PORT3 0x16A79C 2215#define MG_CLKHUB_LN0_PORT4 0x16B39C 2216#define MG_CLKHUB_LN1_PORT4 0x16B79C 2217#define MG_CLKHUB(ln, tc_port) \ 2218 MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \ 2219 MG_CLKHUB_LN0_PORT2, \ 2220 MG_CLKHUB_LN1_PORT1) 2221#define CFG_LOW_RATE_LKREN_EN (1 << 11) 2222 2223#define MG_TX_DCC_TX1LN0_PORT1 0x168110 2224#define MG_TX_DCC_TX1LN1_PORT1 0x168510 2225#define MG_TX_DCC_TX1LN0_PORT2 0x169110 2226#define MG_TX_DCC_TX1LN1_PORT2 0x169510 2227#define MG_TX_DCC_TX1LN0_PORT3 0x16A110 2228#define MG_TX_DCC_TX1LN1_PORT3 0x16A510 2229#define MG_TX_DCC_TX1LN0_PORT4 0x16B110 2230#define MG_TX_DCC_TX1LN1_PORT4 0x16B510 2231#define MG_TX1_DCC(ln, tc_port) \ 2232 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \ 2233 MG_TX_DCC_TX1LN0_PORT2, \ 2234 MG_TX_DCC_TX1LN1_PORT1) 2235#define MG_TX_DCC_TX2LN0_PORT1 0x168090 2236#define MG_TX_DCC_TX2LN1_PORT1 0x168490 2237#define MG_TX_DCC_TX2LN0_PORT2 0x169090 2238#define MG_TX_DCC_TX2LN1_PORT2 0x169490 2239#define MG_TX_DCC_TX2LN0_PORT3 0x16A090 2240#define MG_TX_DCC_TX2LN1_PORT3 0x16A490 2241#define MG_TX_DCC_TX2LN0_PORT4 0x16B090 2242#define MG_TX_DCC_TX2LN1_PORT4 0x16B490 2243#define MG_TX2_DCC(ln, tc_port) \ 2244 MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \ 2245 MG_TX_DCC_TX2LN0_PORT2, \ 2246 MG_TX_DCC_TX2LN1_PORT1) 2247#define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) 2248#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) 2249#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) 2250 2251#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 2252#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 2253#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 2254#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 2255#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0 2256#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 2257#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 2258#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 2259#define MG_DP_MODE(ln, tc_port) \ 2260 MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \ 2261 MG_DP_MODE_LN0_ACU_PORT2, \ 2262 MG_DP_MODE_LN1_ACU_PORT1) 2263#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) 2264#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) 2265 2266/* The spec defines this only for BXT PHY0, but lets assume that this 2267 * would exist for PHY1 too if it had a second channel. 2268 */ 2269#define _PORT_CL2CM_DW6_A 0x162358 2270#define _PORT_CL2CM_DW6_BC 0x6C358 2271#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 2272#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 2273 2274#define FIA1_BASE 0x163000 2275#define FIA2_BASE 0x16E000 2276#define FIA3_BASE 0x16F000 2277#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE) 2278#define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) 2279 2280/* ICL PHY DFLEX registers */ 2281#define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0) 2282#define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx))) 2283#define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx))) 2284#define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx))) 2285#define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx))) 2286#define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx))) 2287#define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx))) 2288 2289/* BXT PHY Ref registers */ 2290#define _PORT_REF_DW3_A 0x16218C 2291#define _PORT_REF_DW3_BC 0x6C18C 2292#define GRC_DONE (1 << 22) 2293#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 2294 2295#define _PORT_REF_DW6_A 0x162198 2296#define _PORT_REF_DW6_BC 0x6C198 2297#define GRC_CODE_SHIFT 24 2298#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 2299#define GRC_CODE_FAST_SHIFT 16 2300#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 2301#define GRC_CODE_SLOW_SHIFT 8 2302#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 2303#define GRC_CODE_NOM_MASK 0xFF 2304#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 2305 2306#define _PORT_REF_DW8_A 0x1621A0 2307#define _PORT_REF_DW8_BC 0x6C1A0 2308#define GRC_DIS (1 << 15) 2309#define GRC_RDY_OVRD (1 << 1) 2310#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 2311 2312/* BXT PHY PCS registers */ 2313#define _PORT_PCS_DW10_LN01_A 0x162428 2314#define _PORT_PCS_DW10_LN01_B 0x6C428 2315#define _PORT_PCS_DW10_LN01_C 0x6C828 2316#define _PORT_PCS_DW10_GRP_A 0x162C28 2317#define _PORT_PCS_DW10_GRP_B 0x6CC28 2318#define _PORT_PCS_DW10_GRP_C 0x6CE28 2319#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2320 _PORT_PCS_DW10_LN01_B, \ 2321 _PORT_PCS_DW10_LN01_C) 2322#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2323 _PORT_PCS_DW10_GRP_B, \ 2324 _PORT_PCS_DW10_GRP_C) 2325 2326#define TX2_SWING_CALC_INIT (1 << 31) 2327#define TX1_SWING_CALC_INIT (1 << 30) 2328 2329#define _PORT_PCS_DW12_LN01_A 0x162430 2330#define _PORT_PCS_DW12_LN01_B 0x6C430 2331#define _PORT_PCS_DW12_LN01_C 0x6C830 2332#define _PORT_PCS_DW12_LN23_A 0x162630 2333#define _PORT_PCS_DW12_LN23_B 0x6C630 2334#define _PORT_PCS_DW12_LN23_C 0x6CA30 2335#define _PORT_PCS_DW12_GRP_A 0x162c30 2336#define _PORT_PCS_DW12_GRP_B 0x6CC30 2337#define _PORT_PCS_DW12_GRP_C 0x6CE30 2338#define LANESTAGGER_STRAP_OVRD (1 << 6) 2339#define LANE_STAGGER_MASK 0x1F 2340#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2341 _PORT_PCS_DW12_LN01_B, \ 2342 _PORT_PCS_DW12_LN01_C) 2343#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2344 _PORT_PCS_DW12_LN23_B, \ 2345 _PORT_PCS_DW12_LN23_C) 2346#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2347 _PORT_PCS_DW12_GRP_B, \ 2348 _PORT_PCS_DW12_GRP_C) 2349 2350/* BXT PHY TX registers */ 2351#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 2352 ((lane) & 1) * 0x80) 2353 2354#define _PORT_TX_DW2_LN0_A 0x162508 2355#define _PORT_TX_DW2_LN0_B 0x6C508 2356#define _PORT_TX_DW2_LN0_C 0x6C908 2357#define _PORT_TX_DW2_GRP_A 0x162D08 2358#define _PORT_TX_DW2_GRP_B 0x6CD08 2359#define _PORT_TX_DW2_GRP_C 0x6CF08 2360#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2361 _PORT_TX_DW2_LN0_B, \ 2362 _PORT_TX_DW2_LN0_C) 2363#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2364 _PORT_TX_DW2_GRP_B, \ 2365 _PORT_TX_DW2_GRP_C) 2366#define MARGIN_000_SHIFT 16 2367#define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 2368#define UNIQ_TRANS_SCALE_SHIFT 8 2369#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 2370 2371#define _PORT_TX_DW3_LN0_A 0x16250C 2372#define _PORT_TX_DW3_LN0_B 0x6C50C 2373#define _PORT_TX_DW3_LN0_C 0x6C90C 2374#define _PORT_TX_DW3_GRP_A 0x162D0C 2375#define _PORT_TX_DW3_GRP_B 0x6CD0C 2376#define _PORT_TX_DW3_GRP_C 0x6CF0C 2377#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2378 _PORT_TX_DW3_LN0_B, \ 2379 _PORT_TX_DW3_LN0_C) 2380#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2381 _PORT_TX_DW3_GRP_B, \ 2382 _PORT_TX_DW3_GRP_C) 2383#define SCALE_DCOMP_METHOD (1 << 26) 2384#define UNIQUE_TRANGE_EN_METHOD (1 << 27) 2385 2386#define _PORT_TX_DW4_LN0_A 0x162510 2387#define _PORT_TX_DW4_LN0_B 0x6C510 2388#define _PORT_TX_DW4_LN0_C 0x6C910 2389#define _PORT_TX_DW4_GRP_A 0x162D10 2390#define _PORT_TX_DW4_GRP_B 0x6CD10 2391#define _PORT_TX_DW4_GRP_C 0x6CF10 2392#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2393 _PORT_TX_DW4_LN0_B, \ 2394 _PORT_TX_DW4_LN0_C) 2395#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2396 _PORT_TX_DW4_GRP_B, \ 2397 _PORT_TX_DW4_GRP_C) 2398#define DEEMPH_SHIFT 24 2399#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 2400 2401#define _PORT_TX_DW5_LN0_A 0x162514 2402#define _PORT_TX_DW5_LN0_B 0x6C514 2403#define _PORT_TX_DW5_LN0_C 0x6C914 2404#define _PORT_TX_DW5_GRP_A 0x162D14 2405#define _PORT_TX_DW5_GRP_B 0x6CD14 2406#define _PORT_TX_DW5_GRP_C 0x6CF14 2407#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2408 _PORT_TX_DW5_LN0_B, \ 2409 _PORT_TX_DW5_LN0_C) 2410#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 2411 _PORT_TX_DW5_GRP_B, \ 2412 _PORT_TX_DW5_GRP_C) 2413#define DCC_DELAY_RANGE_1 (1 << 9) 2414#define DCC_DELAY_RANGE_2 (1 << 8) 2415 2416#define _PORT_TX_DW14_LN0_A 0x162538 2417#define _PORT_TX_DW14_LN0_B 0x6C538 2418#define _PORT_TX_DW14_LN0_C 0x6C938 2419#define LATENCY_OPTIM_SHIFT 30 2420#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 2421#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 2422 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 2423 _PORT_TX_DW14_LN0_C) + \ 2424 _BXT_LANE_OFFSET(lane)) 2425 2426/* UAIMI scratch pad register 1 */ 2427#define UAIMI_SPR1 _MMIO(0x4F074) 2428/* SKL VccIO mask */ 2429#define SKL_VCCIO_MASK 0x1 2430/* SKL balance leg register */ 2431#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 2432/* I_boost values */ 2433#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 2434#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 2435/* Balance leg disable bits */ 2436#define BALANCE_LEG_DISABLE_SHIFT 23 2437#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 2438 2439/* 2440 * Fence registers 2441 * [0-7] @ 0x2000 gen2,gen3 2442 * [8-15] @ 0x3000 945,g33,pnv 2443 * 2444 * [0-15] @ 0x3000 gen4,gen5 2445 * 2446 * [0-15] @ 0x100000 gen6,vlv,chv 2447 * [0-31] @ 0x100000 gen7+ 2448 */ 2449#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 2450#define I830_FENCE_START_MASK 0x07f80000 2451#define I830_FENCE_TILING_Y_SHIFT 12 2452#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 2453#define I830_FENCE_PITCH_SHIFT 4 2454#define I830_FENCE_REG_VALID (1 << 0) 2455#define I915_FENCE_MAX_PITCH_VAL 4 2456#define I830_FENCE_MAX_PITCH_VAL 6 2457#define I830_FENCE_MAX_SIZE_VAL (1 << 8) 2458 2459#define I915_FENCE_START_MASK 0x0ff00000 2460#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 2461 2462#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 2463#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 2464#define I965_FENCE_PITCH_SHIFT 2 2465#define I965_FENCE_TILING_Y_SHIFT 1 2466#define I965_FENCE_REG_VALID (1 << 0) 2467#define I965_FENCE_MAX_PITCH_VAL 0x0400 2468 2469#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 2470#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 2471#define GEN6_FENCE_PITCH_SHIFT 32 2472#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 2473 2474 2475/* control register for cpu gtt access */ 2476#define TILECTL _MMIO(0x101000) 2477#define TILECTL_SWZCTL (1 << 0) 2478#define TILECTL_TLBPF (1 << 1) 2479#define TILECTL_TLB_PREFETCH_DIS (1 << 2) 2480#define TILECTL_BACKSNOOP_DIS (1 << 3) 2481 2482/* 2483 * Instruction and interrupt control regs 2484 */ 2485#define PGTBL_CTL _MMIO(0x02020) 2486#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 2487#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 2488#define PGTBL_ER _MMIO(0x02024) 2489#define PRB0_BASE (0x2030 - 0x30) 2490#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 2491#define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 2492#define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 2493#define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 2494#define SRB2_BASE (0x2120 - 0x30) /* 830 */ 2495#define SRB3_BASE (0x2130 - 0x30) /* 830 */ 2496#define RENDER_RING_BASE 0x02000 2497#define BSD_RING_BASE 0x04000 2498#define GEN6_BSD_RING_BASE 0x12000 2499#define GEN8_BSD2_RING_BASE 0x1c000 2500#define GEN11_BSD_RING_BASE 0x1c0000 2501#define GEN11_BSD2_RING_BASE 0x1c4000 2502#define GEN11_BSD3_RING_BASE 0x1d0000 2503#define GEN11_BSD4_RING_BASE 0x1d4000 2504#define VEBOX_RING_BASE 0x1a000 2505#define GEN11_VEBOX_RING_BASE 0x1c8000 2506#define GEN11_VEBOX2_RING_BASE 0x1d8000 2507#define BLT_RING_BASE 0x22000 2508#define RING_TAIL(base) _MMIO((base) + 0x30) 2509#define RING_HEAD(base) _MMIO((base) + 0x34) 2510#define RING_START(base) _MMIO((base) + 0x38) 2511#define RING_CTL(base) _MMIO((base) + 0x3c) 2512#define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 2513#define RING_SYNC_0(base) _MMIO((base) + 0x40) 2514#define RING_SYNC_1(base) _MMIO((base) + 0x44) 2515#define RING_SYNC_2(base) _MMIO((base) + 0x48) 2516#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 2517#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 2518#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 2519#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 2520#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 2521#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 2522#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 2523#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 2524#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 2525#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 2526#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 2527#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 2528#define GEN6_NOSYNC INVALID_MMIO_REG 2529#define RING_PSMI_CTL(base) _MMIO((base) + 0x50) 2530#define RING_MAX_IDLE(base) _MMIO((base) + 0x54) 2531#define RING_HWS_PGA(base) _MMIO((base) + 0x80) 2532#define RING_HWS_PGA_GEN6(base) _MMIO((base) + 0x2080) 2533#define RING_RESET_CTL(base) _MMIO((base) + 0xd0) 2534#define RESET_CTL_CAT_ERROR REG_BIT(2) 2535#define RESET_CTL_READY_TO_RESET REG_BIT(1) 2536#define RESET_CTL_REQUEST_RESET REG_BIT(0) 2537 2538#define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c) 2539 2540#define HSW_GTT_CACHE_EN _MMIO(0x4024) 2541#define GTT_CACHE_EN_ALL 0xF0007FFF 2542#define GEN7_WR_WATERMARK _MMIO(0x4028) 2543#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 2544#define ARB_MODE _MMIO(0x4030) 2545#define ARB_MODE_SWIZZLE_SNB (1 << 4) 2546#define ARB_MODE_SWIZZLE_IVB (1 << 5) 2547#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 2548#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 2549/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 2550#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 2551#define GEN7_LRA_LIMITS_REG_NUM 13 2552#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 2553#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 2554 2555#define GAMTARBMODE _MMIO(0x04a08) 2556#define ARB_MODE_BWGTLB_DISABLE (1 << 9) 2557#define ARB_MODE_SWIZZLE_BDW (1 << 1) 2558#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080) 2559#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id) 2560#define GEN8_RING_FAULT_REG _MMIO(0x4094) 2561#define GEN12_RING_FAULT_REG _MMIO(0xcec4) 2562#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 2563#define RING_FAULT_GTTSEL_MASK (1 << 11) 2564#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 2565#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 2566#define RING_FAULT_VALID (1 << 0) 2567#define DONE_REG _MMIO(0x40b0) 2568#define GEN12_GAM_DONE _MMIO(0xcf68) 2569#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 2570#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 2571#define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 2572#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) 2573#define BSD_HWS_PGA_GEN7 _MMIO(0x04180) 2574#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) 2575#define GEN12_VD0_AUX_NV _MMIO(0x4218) 2576#define GEN12_VD1_AUX_NV _MMIO(0x4228) 2577#define GEN12_VD2_AUX_NV _MMIO(0x4298) 2578#define GEN12_VD3_AUX_NV _MMIO(0x42A8) 2579#define GEN12_VE0_AUX_NV _MMIO(0x4238) 2580#define GEN12_VE1_AUX_NV _MMIO(0x42B8) 2581#define AUX_INV REG_BIT(0) 2582#define BLT_HWS_PGA_GEN7 _MMIO(0x04280) 2583#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380) 2584#define RING_ACTHD(base) _MMIO((base) + 0x74) 2585#define RING_ACTHD_UDW(base) _MMIO((base) + 0x5c) 2586#define RING_NOPID(base) _MMIO((base) + 0x94) 2587#define RING_IMR(base) _MMIO((base) + 0xa8) 2588#define RING_HWSTAM(base) _MMIO((base) + 0x98) 2589#define RING_TIMESTAMP(base) _MMIO((base) + 0x358) 2590#define RING_TIMESTAMP_UDW(base) _MMIO((base) + 0x358 + 4) 2591#define TAIL_ADDR 0x001FFFF8 2592#define HEAD_WRAP_COUNT 0xFFE00000 2593#define HEAD_WRAP_ONE 0x00200000 2594#define HEAD_ADDR 0x001FFFFC 2595#define RING_NR_PAGES 0x001FF000 2596#define RING_REPORT_MASK 0x00000006 2597#define RING_REPORT_64K 0x00000002 2598#define RING_REPORT_128K 0x00000004 2599#define RING_NO_REPORT 0x00000000 2600#define RING_VALID_MASK 0x00000001 2601#define RING_VALID 0x00000001 2602#define RING_INVALID 0x00000000 2603#define RING_WAIT_I8XX (1 << 0) /* gen2, PRBx_HEAD */ 2604#define RING_WAIT (1 << 11) /* gen3+, PRBx_CTL */ 2605#define RING_WAIT_SEMAPHORE (1 << 10) /* gen6+ */ 2606 2607/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */ 2608#define GEN8_RING_CS_GPR(base, n) _MMIO((base) + 0x600 + (n) * 8) 2609#define GEN8_RING_CS_GPR_UDW(base, n) _MMIO((base) + 0x600 + (n) * 8 + 4) 2610 2611#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4) 2612#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 2613#define RING_FORCE_TO_NONPRIV_ACCESS_RW (0 << 28) /* CFL+ & Gen11+ */ 2614#define RING_FORCE_TO_NONPRIV_ACCESS_RD (1 << 28) 2615#define RING_FORCE_TO_NONPRIV_ACCESS_WR (2 << 28) 2616#define RING_FORCE_TO_NONPRIV_ACCESS_INVALID (3 << 28) 2617#define RING_FORCE_TO_NONPRIV_ACCESS_MASK (3 << 28) 2618#define RING_FORCE_TO_NONPRIV_RANGE_1 (0 << 0) /* CFL+ & Gen11+ */ 2619#define RING_FORCE_TO_NONPRIV_RANGE_4 (1 << 0) 2620#define RING_FORCE_TO_NONPRIV_RANGE_16 (2 << 0) 2621#define RING_FORCE_TO_NONPRIV_RANGE_64 (3 << 0) 2622#define RING_FORCE_TO_NONPRIV_RANGE_MASK (3 << 0) 2623#define RING_FORCE_TO_NONPRIV_MASK_VALID \ 2624 (RING_FORCE_TO_NONPRIV_RANGE_MASK \ 2625 | RING_FORCE_TO_NONPRIV_ACCESS_MASK) 2626#define RING_MAX_NONPRIV_SLOTS 12 2627 2628#define GEN7_TLB_RD_ADDR _MMIO(0x4700) 2629 2630#define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 2631#define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 2632 2633#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 2634#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 2635#define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 2636 2637#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 2638#define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 2639#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 2640#define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 2641 2642#define GEN8_RTCR _MMIO(0x4260) 2643#define GEN8_M1TCR _MMIO(0x4264) 2644#define GEN8_M2TCR _MMIO(0x4268) 2645#define GEN8_BTCR _MMIO(0x426c) 2646#define GEN8_VTCR _MMIO(0x4270) 2647 2648#if 0 2649#define PRB0_TAIL _MMIO(0x2030) 2650#define PRB0_HEAD _MMIO(0x2034) 2651#define PRB0_START _MMIO(0x2038) 2652#define PRB0_CTL _MMIO(0x203c) 2653#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */ 2654#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */ 2655#define PRB1_START _MMIO(0x2048) /* 915+ only */ 2656#define PRB1_CTL _MMIO(0x204c) /* 915+ only */ 2657#endif 2658#define IPEIR_I965 _MMIO(0x2064) 2659#define IPEHR_I965 _MMIO(0x2068) 2660#define GEN7_SC_INSTDONE _MMIO(0x7100) 2661#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) 2662#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) 2663#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 2664#define GEN7_ROW_INSTDONE _MMIO(0xe164) 2665#define GEN8_MCR_SELECTOR _MMIO(0xfdc) 2666#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 2667#define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 2668#define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 2669#define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 2670#define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 2671#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 2672#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 2673#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 2674#define RING_IPEIR(base) _MMIO((base) + 0x64) 2675#define RING_IPEHR(base) _MMIO((base) + 0x68) 2676#define RING_EIR(base) _MMIO((base) + 0xb0) 2677#define RING_EMR(base) _MMIO((base) + 0xb4) 2678#define RING_ESR(base) _MMIO((base) + 0xb8) 2679/* 2680 * On GEN4, only the render ring INSTDONE exists and has a different 2681 * layout than the GEN7+ version. 2682 * The GEN2 counterpart of this register is GEN2_INSTDONE. 2683 */ 2684#define RING_INSTDONE(base) _MMIO((base) + 0x6c) 2685#define RING_INSTPS(base) _MMIO((base) + 0x70) 2686#define RING_DMA_FADD(base) _MMIO((base) + 0x78) 2687#define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ 2688#define RING_INSTPM(base) _MMIO((base) + 0xc0) 2689#define RING_MI_MODE(base) _MMIO((base) + 0x9c) 2690#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) 2691#define INSTPS _MMIO(0x2070) /* 965+ only */ 2692#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 2693#define ACTHD_I965 _MMIO(0x2074) 2694#define HWS_PGA _MMIO(0x2080) 2695#define HWS_ADDRESS_MASK 0xfffff000 2696#define HWS_START_ADDRESS_SHIFT 4 2697#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 2698#define PWRCTX_EN (1 << 0) 2699#define IPEIR(base) _MMIO((base) + 0x88) 2700#define IPEHR(base) _MMIO((base) + 0x8c) 2701#define GEN2_INSTDONE _MMIO(0x2090) 2702#define NOPID _MMIO(0x2094) 2703#define HWSTAM _MMIO(0x2098) 2704#define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0) 2705#define RING_BBSTATE(base) _MMIO((base) + 0x110) 2706#define RING_BB_PPGTT (1 << 5) 2707#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ 2708#define RING_SBBSTATE(base) _MMIO((base) + 0x118) /* hsw+ */ 2709#define RING_SBBADDR_UDW(base) _MMIO((base) + 0x11c) /* gen8+ */ 2710#define RING_BBADDR(base) _MMIO((base) + 0x140) 2711#define RING_BBADDR_UDW(base) _MMIO((base) + 0x168) /* gen8+ */ 2712#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ 2713#define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ 2714#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ 2715#define RING_CTX_TIMESTAMP(base) _MMIO((base) + 0x3a8) /* gen8+ */ 2716 2717#define ERROR_GEN6 _MMIO(0x40a0) 2718#define GEN7_ERR_INT _MMIO(0x44040) 2719#define ERR_INT_POISON (1 << 31) 2720#define ERR_INT_MMIO_UNCLAIMED (1 << 13) 2721#define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 2722#define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 2723#define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 2724#define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 2725#define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 2726#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 2727#define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 2728#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 2729 2730#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 2731#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 2732#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) 2733#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) 2734#define FAULT_VA_HIGH_BITS (0xf << 0) 2735#define FAULT_GTT_SEL (1 << 4) 2736 2737#define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) 2738#define GEN12_VD_TLB_INV_CR _MMIO(0xcedc) 2739#define GEN12_VE_TLB_INV_CR _MMIO(0xcee0) 2740#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4) 2741 2742#define GEN12_AUX_ERR_DBG _MMIO(0x43f4) 2743 2744#define FPGA_DBG _MMIO(0x42300) 2745#define FPGA_DBG_RM_NOCLAIM (1 << 31) 2746 2747#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 2748#define CLAIM_ER_CLR (1 << 31) 2749#define CLAIM_ER_OVERFLOW (1 << 16) 2750#define CLAIM_ER_CTR_MASK 0xffff 2751 2752#define DERRMR _MMIO(0x44050) 2753/* Note that HBLANK events are reserved on bdw+ */ 2754#define DERRMR_PIPEA_SCANLINE (1 << 0) 2755#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 2756#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 2757#define DERRMR_PIPEA_VBLANK (1 << 3) 2758#define DERRMR_PIPEA_HBLANK (1 << 5) 2759#define DERRMR_PIPEB_SCANLINE (1 << 8) 2760#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 2761#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 2762#define DERRMR_PIPEB_VBLANK (1 << 11) 2763#define DERRMR_PIPEB_HBLANK (1 << 13) 2764/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 2765#define DERRMR_PIPEC_SCANLINE (1 << 14) 2766#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 2767#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 2768#define DERRMR_PIPEC_VBLANK (1 << 21) 2769#define DERRMR_PIPEC_HBLANK (1 << 22) 2770 2771 2772/* GM45+ chicken bits -- debug workaround bits that may be required 2773 * for various sorts of correct behavior. The top 16 bits of each are 2774 * the enables for writing to the corresponding low bit. 2775 */ 2776#define _3D_CHICKEN _MMIO(0x2084) 2777#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 2778#define _3D_CHICKEN2 _MMIO(0x208c) 2779 2780#define FF_SLICE_CHICKEN _MMIO(0x2088) 2781#define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 2782 2783/* Disables pipelining of read flushes past the SF-WIZ interface. 2784 * Required on all Ironlake steppings according to the B-Spec, but the 2785 * particular danger of not doing so is not specified. 2786 */ 2787# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 2788#define _3D_CHICKEN3 _MMIO(0x2090) 2789#define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 2790#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 2791#define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 2792#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 2793#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 2794#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 2795 2796#define MI_MODE _MMIO(0x209c) 2797# define VS_TIMER_DISPATCH (1 << 6) 2798# define MI_FLUSH_ENABLE (1 << 12) 2799# define ASYNC_FLIP_PERF_DISABLE (1 << 14) 2800# define MODE_IDLE (1 << 9) 2801# define STOP_RING (1 << 8) 2802 2803#define GEN6_GT_MODE _MMIO(0x20d0) 2804#define GEN7_GT_MODE _MMIO(0x7008) 2805#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 2806#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 2807#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 2808#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 2809#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 2810#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 2811#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 2812#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 2813 2814/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 2815#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4) 2816#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 2817#define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 2818 2819/* WaClearTdlStateAckDirtyBits */ 2820#define GEN8_STATE_ACK _MMIO(0x20F0) 2821#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8) 2822#define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 2823#define GEN9_STATE_ACK_TDL0 (1 << 12) 2824#define GEN9_STATE_ACK_TDL1 (1 << 13) 2825#define GEN9_STATE_ACK_TDL2 (1 << 14) 2826#define GEN9_STATE_ACK_TDL3 (1 << 15) 2827#define GEN9_SUBSLICE_TDL_ACK_BITS \ 2828 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 2829 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 2830 2831#define GFX_MODE _MMIO(0x2520) 2832#define GFX_MODE_GEN7 _MMIO(0x229c) 2833#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c) 2834#define GFX_RUN_LIST_ENABLE (1 << 15) 2835#define GFX_INTERRUPT_STEERING (1 << 14) 2836#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13) 2837#define GFX_SURFACE_FAULT_ENABLE (1 << 12) 2838#define GFX_REPLAY_MODE (1 << 11) 2839#define GFX_PSMI_GRANULARITY (1 << 10) 2840#define GFX_PPGTT_ENABLE (1 << 9) 2841#define GEN8_GFX_PPGTT_48B (1 << 7) 2842 2843#define GFX_FORWARD_VBLANK_MASK (3 << 5) 2844#define GFX_FORWARD_VBLANK_NEVER (0 << 5) 2845#define GFX_FORWARD_VBLANK_ALWAYS (1 << 5) 2846#define GFX_FORWARD_VBLANK_COND (2 << 5) 2847 2848#define GEN11_GFX_DISABLE_LEGACY_MODE (1 << 3) 2849 2850#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 2851#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 2852#define SCPD0 _MMIO(0x209c) /* 915+ only */ 2853#define SCPD_FBC_IGNORE_3D (1 << 6) 2854#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 2855#define GEN2_IER _MMIO(0x20a0) 2856#define GEN2_IIR _MMIO(0x20a4) 2857#define GEN2_IMR _MMIO(0x20a8) 2858#define GEN2_ISR _MMIO(0x20ac) 2859#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 2860#define GINT_DIS (1 << 22) 2861#define GCFG_DIS (1 << 8) 2862#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 2863#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 2864#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 2865#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 2866#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 2867#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 2868#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 2869#define VLV_PCBR_ADDR_SHIFT 12 2870 2871#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 2872#define EIR _MMIO(0x20b0) 2873#define EMR _MMIO(0x20b4) 2874#define ESR _MMIO(0x20b8) 2875#define GM45_ERROR_PAGE_TABLE (1 << 5) 2876#define GM45_ERROR_MEM_PRIV (1 << 4) 2877#define I915_ERROR_PAGE_TABLE (1 << 4) 2878#define GM45_ERROR_CP_PRIV (1 << 3) 2879#define I915_ERROR_MEMORY_REFRESH (1 << 1) 2880#define I915_ERROR_INSTRUCTION (1 << 0) 2881#define INSTPM _MMIO(0x20c0) 2882#define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 2883#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 2884 will not assert AGPBUSY# and will only 2885 be delivered when out of C3. */ 2886#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 2887#define INSTPM_TLB_INVALIDATE (1 << 9) 2888#define INSTPM_SYNC_FLUSH (1 << 5) 2889#define ACTHD(base) _MMIO((base) + 0xc8) 2890#define MEM_MODE _MMIO(0x20cc) 2891#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 2892#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 2893#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 2894#define FW_BLC _MMIO(0x20d8) 2895#define FW_BLC2 _MMIO(0x20dc) 2896#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 2897#define FW_BLC_SELF_EN_MASK (1 << 31) 2898#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 2899#define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 2900#define MM_BURST_LENGTH 0x00700000 2901#define MM_FIFO_WATERMARK 0x0001F000 2902#define LM_BURST_LENGTH 0x00000700 2903#define LM_FIFO_WATERMARK 0x0000001F 2904#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 2905 2906#define _MBUS_ABOX0_CTL 0x45038 2907#define _MBUS_ABOX1_CTL 0x45048 2908#define _MBUS_ABOX2_CTL 0x4504C 2909#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 2910 _MBUS_ABOX1_CTL, \ 2911 _MBUS_ABOX2_CTL)) 2912#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 2913#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 2914#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 2915#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 2916#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 2917#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 2918#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 2919#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 2920 2921#define _PIPEA_MBUS_DBOX_CTL 0x7003C 2922#define _PIPEB_MBUS_DBOX_CTL 0x7103C 2923#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 2924 _PIPEB_MBUS_DBOX_CTL) 2925#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) 2926#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) 2927#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) 2928#define MBUS_DBOX_B_CREDIT(x) ((x) << 8) 2929#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) 2930#define MBUS_DBOX_A_CREDIT(x) ((x) << 0) 2931 2932#define MBUS_UBOX_CTL _MMIO(0x4503C) 2933#define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 2934#define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 2935 2936#define HDPORT_STATE _MMIO(0x45050) 2937#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12) 2938#define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2) 2939#define HDPORT_PHY_USED_HDMI(phy) REG_BIT(2 * (phy) + 1) 2940#define HDPORT_ENABLED REG_BIT(0) 2941 2942/* Make render/texture TLB fetches lower priorty than associated data 2943 * fetches. This is not turned on by default 2944 */ 2945#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 2946 2947/* Isoch request wait on GTT enable (Display A/B/C streams). 2948 * Make isoch requests stall on the TLB update. May cause 2949 * display underruns (test mode only) 2950 */ 2951#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 2952 2953/* Block grant count for isoch requests when block count is 2954 * set to a finite value. 2955 */ 2956#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 2957#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 2958#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 2959#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 2960#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 2961 2962/* Enable render writes to complete in C2/C3/C4 power states. 2963 * If this isn't enabled, render writes are prevented in low 2964 * power states. That seems bad to me. 2965 */ 2966#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 2967 2968/* This acknowledges an async flip immediately instead 2969 * of waiting for 2TLB fetches. 2970 */ 2971#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 2972 2973/* Enables non-sequential data reads through arbiter 2974 */ 2975#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 2976 2977/* Disable FSB snooping of cacheable write cycles from binner/render 2978 * command stream 2979 */ 2980#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 2981 2982/* Arbiter time slice for non-isoch streams */ 2983#define MI_ARB_TIME_SLICE_MASK (7 << 5) 2984#define MI_ARB_TIME_SLICE_1 (0 << 5) 2985#define MI_ARB_TIME_SLICE_2 (1 << 5) 2986#define MI_ARB_TIME_SLICE_4 (2 << 5) 2987#define MI_ARB_TIME_SLICE_6 (3 << 5) 2988#define MI_ARB_TIME_SLICE_8 (4 << 5) 2989#define MI_ARB_TIME_SLICE_10 (5 << 5) 2990#define MI_ARB_TIME_SLICE_14 (6 << 5) 2991#define MI_ARB_TIME_SLICE_16 (7 << 5) 2992 2993/* Low priority grace period page size */ 2994#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 2995#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 2996 2997/* Disable display A/B trickle feed */ 2998#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 2999 3000/* Set display plane priority */ 3001#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 3002#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 3003 3004#define MI_STATE _MMIO(0x20e4) /* gen2 only */ 3005#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 3006#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 3007 3008#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 3009#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 3010#define CM0_IZ_OPT_DISABLE (1 << 6) 3011#define CM0_ZR_OPT_DISABLE (1 << 5) 3012#define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 3013#define CM0_DEPTH_EVICT_DISABLE (1 << 4) 3014#define CM0_COLOR_EVICT_DISABLE (1 << 3) 3015#define CM0_DEPTH_WRITE_DISABLE (1 << 1) 3016#define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 3017#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 3018#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 3019#define GFX_FLSH_CNTL_EN (1 << 0) 3020#define ECOSKPD _MMIO(0x21d0) 3021#define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) 3022#define ECO_GATING_CX_ONLY (1 << 3) 3023#define ECO_FLIP_DONE (1 << 0) 3024 3025#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 3026#define RC_OP_FLUSH_ENABLE (1 << 0) 3027#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 3028#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 3029#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) 3030#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) 3031#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) 3032 3033#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0) 3034#define GEN6_BLITTER_LOCK_SHIFT 16 3035#define GEN6_BLITTER_FBC_NOTIFY (1 << 3) 3036 3037#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050) 3038#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) 3039#define GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 3040#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 3041#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1 << 10) 3042 3043#define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 3044#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 3045 3046#define GEN10_CACHE_MODE_SS _MMIO(0xe420) 3047#define FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) 3048 3049/* Fuse readout registers for GT */ 3050#define HSW_PAVP_FUSE1 _MMIO(0x911C) 3051#define HSW_F1_EU_DIS_SHIFT 16 3052#define HSW_F1_EU_DIS_MASK (0x3 << HSW_F1_EU_DIS_SHIFT) 3053#define HSW_F1_EU_DIS_10EUS 0 3054#define HSW_F1_EU_DIS_8EUS 1 3055#define HSW_F1_EU_DIS_6EUS 2 3056 3057#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168) 3058#define CHV_FGT_DISABLE_SS0 (1 << 10) 3059#define CHV_FGT_DISABLE_SS1 (1 << 11) 3060#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 3061#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 3062#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 3063#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 3064#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 3065#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 3066#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 3067#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 3068 3069#define GEN8_FUSE2 _MMIO(0x9120) 3070#define GEN8_F2_SS_DIS_SHIFT 21 3071#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 3072#define GEN8_F2_S_ENA_SHIFT 25 3073#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 3074 3075#define GEN9_F2_SS_DIS_SHIFT 20 3076#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 3077 3078#define GEN10_F2_S_ENA_SHIFT 22 3079#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 3080#define GEN10_F2_SS_DIS_SHIFT 18 3081#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 3082 3083#define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 3084#define GEN10_L3BANK_PAIR_COUNT 4 3085#define GEN10_L3BANK_MASK 0x0F 3086 3087#define GEN8_EU_DISABLE0 _MMIO(0x9134) 3088#define GEN8_EU_DIS0_S0_MASK 0xffffff 3089#define GEN8_EU_DIS0_S1_SHIFT 24 3090#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 3091 3092#define GEN8_EU_DISABLE1 _MMIO(0x9138) 3093#define GEN8_EU_DIS1_S1_MASK 0xffff 3094#define GEN8_EU_DIS1_S2_SHIFT 16 3095#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 3096 3097#define GEN8_EU_DISABLE2 _MMIO(0x913c) 3098#define GEN8_EU_DIS2_S2_MASK 0xff 3099 3100#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 3101 3102#define GEN10_EU_DISABLE3 _MMIO(0x9140) 3103#define GEN10_EU_DIS_SS_MASK 0xff 3104 3105#define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 3106#define GEN11_GT_VDBOX_DISABLE_MASK 0xff 3107#define GEN11_GT_VEBOX_DISABLE_SHIFT 16 3108#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 3109 3110#define GEN11_EU_DISABLE _MMIO(0x9134) 3111#define GEN11_EU_DIS_MASK 0xFF 3112 3113#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 3114#define GEN11_GT_S_ENA_MASK 0xFF 3115 3116#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C) 3117 3118#define GEN12_GT_DSS_ENABLE _MMIO(0x913C) 3119 3120#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050) 3121#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 3122#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 3123#define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 3124#define GEN6_BSD_GO_INDICATOR (1 << 4) 3125 3126/* On modern GEN architectures interrupt control consists of two sets 3127 * of registers. The first set pertains to the ring generating the 3128 * interrupt. The second control is for the functional block generating the 3129 * interrupt. These are PM, GT, DE, etc. 3130 * 3131 * Luckily *knocks on wood* all the ring interrupt bits match up with the 3132 * GT interrupt bits, so we don't need to duplicate the defines. 3133 * 3134 * These defines should cover us well from SNB->HSW with minor exceptions 3135 * it can also work on ILK. 3136 */ 3137#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 3138#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 3139#define GT_BLT_USER_INTERRUPT (1 << 22) 3140#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 3141#define GT_BSD_USER_INTERRUPT (1 << 12) 3142#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 3143#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 3144#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 3145#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 3146#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 3147#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 3148#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 3149#define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 3150#define GT_RENDER_USER_INTERRUPT (1 << 0) 3151 3152#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 3153#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 3154 3155#define GT_PARITY_ERROR(dev_priv) \ 3156 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 3157 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 3158 3159/* These are all the "old" interrupts */ 3160#define ILK_BSD_USER_INTERRUPT (1 << 5) 3161 3162#define I915_PM_INTERRUPT (1 << 31) 3163#define I915_ISP_INTERRUPT (1 << 22) 3164#define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 3165#define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 3166#define I915_MIPIC_INTERRUPT (1 << 19) 3167#define I915_MIPIA_INTERRUPT (1 << 18) 3168#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 3169#define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 3170#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 3171#define I915_MASTER_ERROR_INTERRUPT (1 << 15) 3172#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 3173#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 3174#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 3175#define I915_HWB_OOM_INTERRUPT (1 << 13) 3176#define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 3177#define I915_SYNC_STATUS_INTERRUPT (1 << 12) 3178#define I915_MISC_INTERRUPT (1 << 11) 3179#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 3180#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 3181#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 3182#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 3183#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 3184#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 3185#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 3186#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 3187#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 3188#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 3189#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 3190#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 3191#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 3192#define I915_DEBUG_INTERRUPT (1 << 2) 3193#define I915_WINVALID_INTERRUPT (1 << 1) 3194#define I915_USER_INTERRUPT (1 << 1) 3195#define I915_ASLE_INTERRUPT (1 << 0) 3196#define I915_BSD_USER_INTERRUPT (1 << 25) 3197 3198#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 3199#define I915_HDMI_LPE_AUDIO_SIZE 0x1000 3200 3201/* DisplayPort Audio w/ LPE */ 3202#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 3203#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 3204 3205#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 3206#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 3207#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 3208#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 3209 _VLV_AUD_PORT_EN_B_DBG, \ 3210 _VLV_AUD_PORT_EN_C_DBG, \ 3211 _VLV_AUD_PORT_EN_D_DBG) 3212#define VLV_AMP_MUTE (1 << 1) 3213 3214#define GEN6_BSD_RNCID _MMIO(0x12198) 3215 3216#define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 3217#define GEN7_FF_SCHED_MASK 0x0077070 3218#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 3219#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 3220#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 3221#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 3222#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 3223#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 3224#define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 3225#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 3226#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 3227#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 3228#define GEN7_FF_VS_SCHED_HW (0x0 << 12) 3229#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 3230#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 3231#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 3232#define GEN7_FF_DS_SCHED_HW (0x0 << 4) 3233 3234/* 3235 * Framebuffer compression (915+ only) 3236 */ 3237 3238#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 3239#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 3240#define FBC_CONTROL _MMIO(0x3208) 3241#define FBC_CTL_EN REG_BIT(31) 3242#define FBC_CTL_PERIODIC REG_BIT(30) 3243#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 3244#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 3245#define FBC_CTL_STOP_ON_MOD REG_BIT(15) 3246#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 3247#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ 3248#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 3249#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 3250#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 3251#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 3252#define FBC_COMMAND _MMIO(0x320c) 3253#define FBC_CMD_COMPRESS (1 << 0) 3254#define FBC_STATUS _MMIO(0x3210) 3255#define FBC_STAT_COMPRESSING (1 << 31) 3256#define FBC_STAT_COMPRESSED (1 << 30) 3257#define FBC_STAT_MODIFIED (1 << 29) 3258#define FBC_STAT_CURRENT_LINE_SHIFT (0) 3259#define FBC_CONTROL2 _MMIO(0x3214) 3260#define FBC_CTL_FENCE_DBL (0 << 4) 3261#define FBC_CTL_IDLE_IMM (0 << 2) 3262#define FBC_CTL_IDLE_FULL (1 << 2) 3263#define FBC_CTL_IDLE_LINE (2 << 2) 3264#define FBC_CTL_IDLE_DEBUG (3 << 2) 3265#define FBC_CTL_CPU_FENCE (1 << 1) 3266#define FBC_CTL_PLANE(plane) ((plane) << 0) 3267#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */ 3268#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) 3269 3270#define FBC_LL_SIZE (1536) 3271 3272#define FBC_LLC_READ_CTRL _MMIO(0x9044) 3273#define FBC_LLC_FULLY_OPEN (1 << 30) 3274 3275/* Framebuffer compression for GM45+ */ 3276#define DPFC_CB_BASE _MMIO(0x3200) 3277#define DPFC_CONTROL _MMIO(0x3208) 3278#define DPFC_CTL_EN (1 << 31) 3279#define DPFC_CTL_PLANE(plane) ((plane) << 30) 3280#define IVB_DPFC_CTL_PLANE(plane) ((plane) << 29) 3281#define DPFC_CTL_FENCE_EN (1 << 29) 3282#define IVB_DPFC_CTL_FENCE_EN (1 << 28) 3283#define DPFC_CTL_PERSISTENT_MODE (1 << 25) 3284#define DPFC_SR_EN (1 << 10) 3285#define DPFC_CTL_LIMIT_1X (0 << 6) 3286#define DPFC_CTL_LIMIT_2X (1 << 6) 3287#define DPFC_CTL_LIMIT_4X (2 << 6) 3288#define DPFC_RECOMP_CTL _MMIO(0x320c) 3289#define DPFC_RECOMP_STALL_EN (1 << 27) 3290#define DPFC_RECOMP_STALL_WM_SHIFT (16) 3291#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 3292#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 3293#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 3294#define DPFC_STATUS _MMIO(0x3210) 3295#define DPFC_INVAL_SEG_SHIFT (16) 3296#define DPFC_INVAL_SEG_MASK (0x07ff0000) 3297#define DPFC_COMP_SEG_SHIFT (0) 3298#define DPFC_COMP_SEG_MASK (0x000007ff) 3299#define DPFC_STATUS2 _MMIO(0x3214) 3300#define DPFC_FENCE_YOFF _MMIO(0x3218) 3301#define DPFC_CHICKEN _MMIO(0x3224) 3302#define DPFC_HT_MODIFY (1 << 31) 3303 3304/* Framebuffer compression for Ironlake */ 3305#define ILK_DPFC_CB_BASE _MMIO(0x43200) 3306#define ILK_DPFC_CONTROL _MMIO(0x43208) 3307#define FBC_CTL_FALSE_COLOR (1 << 10) 3308/* The bit 28-8 is reserved */ 3309#define DPFC_RESERVED (0x1FFFFF00) 3310#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c) 3311#define ILK_DPFC_STATUS _MMIO(0x43210) 3312#define ILK_DPFC_COMP_SEG_MASK 0x7ff 3313#define IVB_FBC_STATUS2 _MMIO(0x43214) 3314#define IVB_FBC_COMP_SEG_MASK 0x7ff 3315#define BDW_FBC_COMP_SEG_MASK 0xfff 3316#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218) 3317#define ILK_DPFC_CHICKEN _MMIO(0x43224) 3318#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8) 3319#define ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL (1 << 14) 3320#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1 << 23) 3321#define ILK_FBC_RT_BASE _MMIO(0x2128) 3322#define ILK_FBC_RT_VALID (1 << 0) 3323#define SNB_FBC_FRONT_BUFFER (1 << 1) 3324 3325#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 3326#define ILK_FBCQ_DIS (1 << 22) 3327#define ILK_PABSTRETCH_DIS (1 << 21) 3328 3329 3330/* 3331 * Framebuffer compression for Sandybridge 3332 * 3333 * The following two registers are of type GTTMMADR 3334 */ 3335#define SNB_DPFC_CTL_SA _MMIO(0x100100) 3336#define SNB_CPU_FENCE_ENABLE (1 << 29) 3337#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 3338 3339/* Framebuffer compression for Ivybridge */ 3340#define IVB_FBC_RT_BASE _MMIO(0x7020) 3341#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 3342 3343#define IPS_CTL _MMIO(0x43408) 3344#define IPS_ENABLE (1 << 31) 3345 3346#define MSG_FBC_REND_STATE _MMIO(0x50380) 3347#define FBC_REND_NUKE (1 << 2) 3348#define FBC_REND_CACHE_CLEAN (1 << 1) 3349 3350/* 3351 * GPIO regs 3352 */ 3353#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 3354 4 * (gpio)) 3355 3356# define GPIO_CLOCK_DIR_MASK (1 << 0) 3357# define GPIO_CLOCK_DIR_IN (0 << 1) 3358# define GPIO_CLOCK_DIR_OUT (1 << 1) 3359# define GPIO_CLOCK_VAL_MASK (1 << 2) 3360# define GPIO_CLOCK_VAL_OUT (1 << 3) 3361# define GPIO_CLOCK_VAL_IN (1 << 4) 3362# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 3363# define GPIO_DATA_DIR_MASK (1 << 8) 3364# define GPIO_DATA_DIR_IN (0 << 9) 3365# define GPIO_DATA_DIR_OUT (1 << 9) 3366# define GPIO_DATA_VAL_MASK (1 << 10) 3367# define GPIO_DATA_VAL_OUT (1 << 11) 3368# define GPIO_DATA_VAL_IN (1 << 12) 3369# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 3370 3371#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 3372#define GMBUS_AKSV_SELECT (1 << 11) 3373#define GMBUS_RATE_100KHZ (0 << 8) 3374#define GMBUS_RATE_50KHZ (1 << 8) 3375#define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 3376#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 3377#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 3378#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 3379 3380#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 3381#define GMBUS_SW_CLR_INT (1 << 31) 3382#define GMBUS_SW_RDY (1 << 30) 3383#define GMBUS_ENT (1 << 29) /* enable timeout */ 3384#define GMBUS_CYCLE_NONE (0 << 25) 3385#define GMBUS_CYCLE_WAIT (1 << 25) 3386#define GMBUS_CYCLE_INDEX (2 << 25) 3387#define GMBUS_CYCLE_STOP (4 << 25) 3388#define GMBUS_BYTE_COUNT_SHIFT 16 3389#define GMBUS_BYTE_COUNT_MAX 256U 3390#define GEN9_GMBUS_BYTE_COUNT_MAX 511U 3391#define GMBUS_SLAVE_INDEX_SHIFT 8 3392#define GMBUS_SLAVE_ADDR_SHIFT 1 3393#define GMBUS_SLAVE_READ (1 << 0) 3394#define GMBUS_SLAVE_WRITE (0 << 0) 3395#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 3396#define GMBUS_INUSE (1 << 15) 3397#define GMBUS_HW_WAIT_PHASE (1 << 14) 3398#define GMBUS_STALL_TIMEOUT (1 << 13) 3399#define GMBUS_INT (1 << 12) 3400#define GMBUS_HW_RDY (1 << 11) 3401#define GMBUS_SATOER (1 << 10) 3402#define GMBUS_ACTIVE (1 << 9) 3403#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 3404#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 3405#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 3406#define GMBUS_NAK_EN (1 << 3) 3407#define GMBUS_IDLE_EN (1 << 2) 3408#define GMBUS_HW_WAIT_EN (1 << 1) 3409#define GMBUS_HW_RDY_EN (1 << 0) 3410#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 3411#define GMBUS_2BYTE_INDEX_EN (1 << 31) 3412 3413/* 3414 * Clock control & power management 3415 */ 3416#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 3417#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 3418#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 3419#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 3420 3421#define VGA0 _MMIO(0x6000) 3422#define VGA1 _MMIO(0x6004) 3423#define VGA_PD _MMIO(0x6010) 3424#define VGA0_PD_P2_DIV_4 (1 << 7) 3425#define VGA0_PD_P1_DIV_2 (1 << 5) 3426#define VGA0_PD_P1_SHIFT 0 3427#define VGA0_PD_P1_MASK (0x1f << 0) 3428#define VGA1_PD_P2_DIV_4 (1 << 15) 3429#define VGA1_PD_P1_DIV_2 (1 << 13) 3430#define VGA1_PD_P1_SHIFT 8 3431#define VGA1_PD_P1_MASK (0x1f << 8) 3432#define DPLL_VCO_ENABLE (1 << 31) 3433#define DPLL_SDVO_HIGH_SPEED (1 << 30) 3434#define DPLL_DVO_2X_MODE (1 << 30) 3435#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 3436#define DPLL_SYNCLOCK_ENABLE (1 << 29) 3437#define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 3438#define DPLL_VGA_MODE_DIS (1 << 28) 3439#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 3440#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 3441#define DPLL_MODE_MASK (3 << 26) 3442#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 3443#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 3444#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 3445#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 3446#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 3447#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 3448#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 3449#define DPLL_LOCK_VLV (1 << 15) 3450#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 3451#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 3452#define DPLL_SSC_REF_CLK_CHV (1 << 13) 3453#define DPLL_PORTC_READY_MASK (0xf << 4) 3454#define DPLL_PORTB_READY_MASK (0xf) 3455 3456#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 3457 3458/* Additional CHV pll/phy registers */ 3459#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 3460#define DPLL_PORTD_READY_MASK (0xf) 3461#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 3462#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 3463#define PHY_LDO_DELAY_0NS 0x0 3464#define PHY_LDO_DELAY_200NS 0x1 3465#define PHY_LDO_DELAY_600NS 0x2 3466#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 3467#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 3468#define PHY_CH_SU_PSR 0x1 3469#define PHY_CH_DEEP_PSR 0x7 3470#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 3471#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 3472#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 3473#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 3474#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 3475#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 3476 3477/* 3478 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 3479 * this field (only one bit may be set). 3480 */ 3481#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 3482#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 3483#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 3484/* i830, required in DVO non-gang */ 3485#define PLL_P2_DIVIDE_BY_4 (1 << 23) 3486#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 3487#define PLL_REF_INPUT_DREFCLK (0 << 13) 3488#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 3489#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 3490#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 3491#define PLL_REF_INPUT_MASK (3 << 13) 3492#define PLL_LOAD_PULSE_PHASE_SHIFT 9 3493/* Ironlake */ 3494# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 3495# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 3496# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 3497# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 3498# define DPLL_FPA1_P1_POST_DIV_MASK 0xff 3499 3500/* 3501 * Parallel to Serial Load Pulse phase selection. 3502 * Selects the phase for the 10X DPLL clock for the PCIe 3503 * digital display port. The range is 4 to 13; 10 or more 3504 * is just a flip delay. The default is 6 3505 */ 3506#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 3507#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 3508/* 3509 * SDVO multiplier for 945G/GM. Not used on 965. 3510 */ 3511#define SDVO_MULTIPLIER_MASK 0x000000ff 3512#define SDVO_MULTIPLIER_SHIFT_HIRES 4 3513#define SDVO_MULTIPLIER_SHIFT_VGA 0 3514 3515#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 3516#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 3517#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 3518#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 3519 3520/* 3521 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 3522 * 3523 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 3524 */ 3525#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 3526#define DPLL_MD_UDI_DIVIDER_SHIFT 24 3527/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 3528#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 3529#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 3530/* 3531 * SDVO/UDI pixel multiplier. 3532 * 3533 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 3534 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 3535 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 3536 * dummy bytes in the datastream at an increased clock rate, with both sides of 3537 * the link knowing how many bytes are fill. 3538 * 3539 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 3540 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 3541 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 3542 * through an SDVO command. 3543 * 3544 * This register field has values of multiplication factor minus 1, with 3545 * a maximum multiplier of 5 for SDVO. 3546 */ 3547#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 3548#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 3549/* 3550 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 3551 * This best be set to the default value (3) or the CRT won't work. No, 3552 * I don't entirely understand what this does... 3553 */ 3554#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 3555#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 3556 3557#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 3558 3559#define _FPA0 0x6040 3560#define _FPA1 0x6044 3561#define _FPB0 0x6048 3562#define _FPB1 0x604c 3563#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 3564#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 3565#define FP_N_DIV_MASK 0x003f0000 3566#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 3567#define FP_N_DIV_SHIFT 16 3568#define FP_M1_DIV_MASK 0x00003f00 3569#define FP_M1_DIV_SHIFT 8 3570#define FP_M2_DIV_MASK 0x0000003f 3571#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 3572#define FP_M2_DIV_SHIFT 0 3573#define DPLL_TEST _MMIO(0x606c) 3574#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 3575#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 3576#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 3577#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 3578#define DPLLB_TEST_N_BYPASS (1 << 19) 3579#define DPLLB_TEST_M_BYPASS (1 << 18) 3580#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 3581#define DPLLA_TEST_N_BYPASS (1 << 3) 3582#define DPLLA_TEST_M_BYPASS (1 << 2) 3583#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 3584#define D_STATE _MMIO(0x6104) 3585#define DSTATE_GFX_RESET_I830 (1 << 6) 3586#define DSTATE_PLL_D3_OFF (1 << 3) 3587#define DSTATE_GFX_CLOCK_GATING (1 << 1) 3588#define DSTATE_DOT_CLOCK_GATING (1 << 0) 3589#define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 3590# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 3591# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 3592# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 3593# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 3594# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 3595# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 3596# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 3597# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 3598# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 3599# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 3600# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 3601# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 3602# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 3603# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 3604# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 3605# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 3606# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 3607# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 3608# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 3609# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 3610# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 3611# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 3612# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 3613# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 3614# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 3615# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 3616# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 3617# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 3618# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 3619/* 3620 * This bit must be set on the 830 to prevent hangs when turning off the 3621 * overlay scaler. 3622 */ 3623# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 3624# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 3625# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 3626# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 3627# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 3628 3629#define RENCLK_GATE_D1 _MMIO(0x6204) 3630# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 3631# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 3632# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 3633# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 3634# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 3635# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 3636# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 3637# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 3638# define MAG_CLOCK_GATE_DISABLE (1 << 5) 3639/* This bit must be unset on 855,865 */ 3640# define MECI_CLOCK_GATE_DISABLE (1 << 4) 3641# define DCMP_CLOCK_GATE_DISABLE (1 << 3) 3642# define MEC_CLOCK_GATE_DISABLE (1 << 2) 3643# define MECO_CLOCK_GATE_DISABLE (1 << 1) 3644/* This bit must be set on 855,865. */ 3645# define SV_CLOCK_GATE_DISABLE (1 << 0) 3646# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 3647# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 3648# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 3649# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 3650# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 3651# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 3652# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 3653# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 3654# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 3655# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 3656# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 3657# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 3658# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 3659# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 3660# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 3661# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 3662# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 3663 3664# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 3665/* This bit must always be set on 965G/965GM */ 3666# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 3667# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 3668# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 3669# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 3670# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 3671# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 3672/* This bit must always be set on 965G */ 3673# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 3674# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 3675# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 3676# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 3677# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 3678# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 3679# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 3680# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 3681# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 3682# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 3683# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 3684# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 3685# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 3686# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 3687# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 3688# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 3689# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 3690# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 3691# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 3692 3693#define RENCLK_GATE_D2 _MMIO(0x6208) 3694#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 3695#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 3696#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 3697 3698#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 3699#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 3700 3701#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 3702#define DEUC _MMIO(0x6214) /* CRL only */ 3703 3704#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 3705#define FW_CSPWRDWNEN (1 << 15) 3706 3707#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 3708 3709#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 3710#define CDCLK_FREQ_SHIFT 4 3711#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 3712#define CZCLK_FREQ_MASK 0xf 3713 3714#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 3715#define PFI_CREDIT_63 (9 << 28) /* chv only */ 3716#define PFI_CREDIT_31 (8 << 28) /* chv only */ 3717#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 3718#define PFI_CREDIT_RESEND (1 << 27) 3719#define VGA_FAST_MODE_DISABLE (1 << 14) 3720 3721#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 3722 3723/* 3724 * Palette regs 3725 */ 3726#define _PALETTE_A 0xa000 3727#define _PALETTE_B 0xa800 3728#define _CHV_PALETTE_C 0xc000 3729#define PALETTE_RED_MASK REG_GENMASK(23, 16) 3730#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 3731#define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 3732#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 3733 _PICK((pipe), _PALETTE_A, \ 3734 _PALETTE_B, _CHV_PALETTE_C) + \ 3735 (i) * 4) 3736 3737/* MCH MMIO space */ 3738 3739/* 3740 * MCHBAR mirror. 3741 * 3742 * This mirrors the MCHBAR MMIO space whose location is determined by 3743 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 3744 * every way. It is not accessible from the CP register read instructions. 3745 * 3746 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 3747 * just read. 3748 */ 3749#define MCHBAR_MIRROR_BASE 0x10000 3750 3751#define MCHBAR_MIRROR_BASE_SNB 0x140000 3752 3753#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34) 3754#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48) 3755#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16) 3756#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4) 3757#define G4X_STOLEN_RESERVED_ENABLE (1 << 0) 3758 3759/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 3760#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) 3761 3762/* 915-945 and GM965 MCH register controlling DRAM channel access */ 3763#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200) 3764#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 3765#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 3766#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 3767#define DCC_ADDRESSING_MODE_MASK (3 << 0) 3768#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 3769#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 3770#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204) 3771#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20) 3772 3773/* Pineview MCH register contains DDR3 setting */ 3774#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8) 3775#define CSHRDDR3CTL_DDR3 (1 << 2) 3776 3777/* 965 MCH register controlling DRAM channel configuration */ 3778#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) 3779#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) 3780 3781/* snb MCH registers for reading the DRAM channel configuration */ 3782#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) 3783#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008) 3784#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 3785#define MAD_DIMM_ECC_MASK (0x3 << 24) 3786#define MAD_DIMM_ECC_OFF (0x0 << 24) 3787#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 3788#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 3789#define MAD_DIMM_ECC_ON (0x3 << 24) 3790#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 3791#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 3792#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 3793#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 3794#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 3795#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 3796#define MAD_DIMM_A_SELECT (0x1 << 16) 3797/* DIMM sizes are in multiples of 256mb. */ 3798#define MAD_DIMM_B_SIZE_SHIFT 8 3799#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 3800#define MAD_DIMM_A_SIZE_SHIFT 0 3801#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 3802 3803/* snb MCH registers for priority tuning */ 3804#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10) 3805#define MCH_SSKPD_WM0_MASK 0x3f 3806#define MCH_SSKPD_WM0_VAL 0xc 3807 3808/* Clocking configuration register */ 3809#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00) 3810#define CLKCFG_FSB_400 (0 << 0) /* hrawclk 100 */ 3811#define CLKCFG_FSB_400_ALT (5 << 0) /* hrawclk 100 */ 3812#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 3813#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 3814#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 3815#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 3816#define CLKCFG_FSB_1067_ALT (0 << 0) /* hrawclk 266 */ 3817#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 3818#define CLKCFG_FSB_1333_ALT (4 << 0) /* hrawclk 333 */ 3819#define CLKCFG_FSB_1600_ALT (6 << 0) /* hrawclk 400 */ 3820#define CLKCFG_FSB_MASK (7 << 0) 3821#define CLKCFG_MEM_533 (1 << 4) 3822#define CLKCFG_MEM_667 (2 << 4) 3823#define CLKCFG_MEM_800 (3 << 4) 3824#define CLKCFG_MEM_MASK (7 << 4) 3825 3826#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38) 3827#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f) 3828 3829#define TSC1 _MMIO(0x11001) 3830#define TSE (1 << 0) 3831#define TR1 _MMIO(0x11006) 3832#define TSFS _MMIO(0x11020) 3833#define TSFS_SLOPE_MASK 0x0000ff00 3834#define TSFS_SLOPE_SHIFT 8 3835#define TSFS_INTR_MASK 0x000000ff 3836 3837#define CRSTANDVID _MMIO(0x11100) 3838#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 3839#define PXVFREQ_PX_MASK 0x7f000000 3840#define PXVFREQ_PX_SHIFT 24 3841#define VIDFREQ_BASE _MMIO(0x11110) 3842#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 3843#define VIDFREQ2 _MMIO(0x11114) 3844#define VIDFREQ3 _MMIO(0x11118) 3845#define VIDFREQ4 _MMIO(0x1111c) 3846#define VIDFREQ_P0_MASK 0x1f000000 3847#define VIDFREQ_P0_SHIFT 24 3848#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 3849#define VIDFREQ_P0_CSCLK_SHIFT 20 3850#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 3851#define VIDFREQ_P0_CRCLK_SHIFT 16 3852#define VIDFREQ_P1_MASK 0x00001f00 3853#define VIDFREQ_P1_SHIFT 8 3854#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 3855#define VIDFREQ_P1_CSCLK_SHIFT 4 3856#define VIDFREQ_P1_CRCLK_MASK 0x0000000f 3857#define INTTOEXT_BASE_ILK _MMIO(0x11300) 3858#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 3859#define INTTOEXT_MAP3_SHIFT 24 3860#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 3861#define INTTOEXT_MAP2_SHIFT 16 3862#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 3863#define INTTOEXT_MAP1_SHIFT 8 3864#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 3865#define INTTOEXT_MAP0_SHIFT 0 3866#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 3867#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 3868#define MEMCTL_CMD_MASK 0xe000 3869#define MEMCTL_CMD_SHIFT 13 3870#define MEMCTL_CMD_RCLK_OFF 0 3871#define MEMCTL_CMD_RCLK_ON 1 3872#define MEMCTL_CMD_CHFREQ 2 3873#define MEMCTL_CMD_CHVID 3 3874#define MEMCTL_CMD_VMMOFF 4 3875#define MEMCTL_CMD_VMMON 5 3876#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 3877 when command complete */ 3878#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 3879#define MEMCTL_FREQ_SHIFT 8 3880#define MEMCTL_SFCAVM (1 << 7) 3881#define MEMCTL_TGT_VID_MASK 0x007f 3882#define MEMIHYST _MMIO(0x1117c) 3883#define MEMINTREN _MMIO(0x11180) /* 16 bits */ 3884#define MEMINT_RSEXIT_EN (1 << 8) 3885#define MEMINT_CX_SUPR_EN (1 << 7) 3886#define MEMINT_CONT_BUSY_EN (1 << 6) 3887#define MEMINT_AVG_BUSY_EN (1 << 5) 3888#define MEMINT_EVAL_CHG_EN (1 << 4) 3889#define MEMINT_MON_IDLE_EN (1 << 3) 3890#define MEMINT_UP_EVAL_EN (1 << 2) 3891#define MEMINT_DOWN_EVAL_EN (1 << 1) 3892#define MEMINT_SW_CMD_EN (1 << 0) 3893#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 3894#define MEM_RSEXIT_MASK 0xc000 3895#define MEM_RSEXIT_SHIFT 14 3896#define MEM_CONT_BUSY_MASK 0x3000 3897#define MEM_CONT_BUSY_SHIFT 12 3898#define MEM_AVG_BUSY_MASK 0x0c00 3899#define MEM_AVG_BUSY_SHIFT 10 3900#define MEM_EVAL_CHG_MASK 0x0300 3901#define MEM_EVAL_BUSY_SHIFT 8 3902#define MEM_MON_IDLE_MASK 0x00c0 3903#define MEM_MON_IDLE_SHIFT 6 3904#define MEM_UP_EVAL_MASK 0x0030 3905#define MEM_UP_EVAL_SHIFT 4 3906#define MEM_DOWN_EVAL_MASK 0x000c 3907#define MEM_DOWN_EVAL_SHIFT 2 3908#define MEM_SW_CMD_MASK 0x0003 3909#define MEM_INT_STEER_GFX 0 3910#define MEM_INT_STEER_CMR 1 3911#define MEM_INT_STEER_SMI 2 3912#define MEM_INT_STEER_SCI 3 3913#define MEMINTRSTS _MMIO(0x11184) 3914#define MEMINT_RSEXIT (1 << 7) 3915#define MEMINT_CONT_BUSY (1 << 6) 3916#define MEMINT_AVG_BUSY (1 << 5) 3917#define MEMINT_EVAL_CHG (1 << 4) 3918#define MEMINT_MON_IDLE (1 << 3) 3919#define MEMINT_UP_EVAL (1 << 2) 3920#define MEMINT_DOWN_EVAL (1 << 1) 3921#define MEMINT_SW_CMD (1 << 0) 3922#define MEMMODECTL _MMIO(0x11190) 3923#define MEMMODE_BOOST_EN (1 << 31) 3924#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 3925#define MEMMODE_BOOST_FREQ_SHIFT 24 3926#define MEMMODE_IDLE_MODE_MASK 0x00030000 3927#define MEMMODE_IDLE_MODE_SHIFT 16 3928#define MEMMODE_IDLE_MODE_EVAL 0 3929#define MEMMODE_IDLE_MODE_CONT 1 3930#define MEMMODE_HWIDLE_EN (1 << 15) 3931#define MEMMODE_SWMODE_EN (1 << 14) 3932#define MEMMODE_RCLK_GATE (1 << 13) 3933#define MEMMODE_HW_UPDATE (1 << 12) 3934#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 3935#define MEMMODE_FSTART_SHIFT 8 3936#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 3937#define MEMMODE_FMAX_SHIFT 4 3938#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 3939#define RCBMAXAVG _MMIO(0x1119c) 3940#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 3941#define SWMEMCMD_RENDER_OFF (0 << 13) 3942#define SWMEMCMD_RENDER_ON (1 << 13) 3943#define SWMEMCMD_SWFREQ (2 << 13) 3944#define SWMEMCMD_TARVID (3 << 13) 3945#define SWMEMCMD_VRM_OFF (4 << 13) 3946#define SWMEMCMD_VRM_ON (5 << 13) 3947#define CMDSTS (1 << 12) 3948#define SFCAVM (1 << 11) 3949#define SWFREQ_MASK 0x0380 /* P0-7 */ 3950#define SWFREQ_SHIFT 7 3951#define TARVID_MASK 0x001f 3952#define MEMSTAT_CTG _MMIO(0x111a0) 3953#define RCBMINAVG _MMIO(0x111a0) 3954#define RCUPEI _MMIO(0x111b0) 3955#define RCDNEI _MMIO(0x111b4) 3956#define RSTDBYCTL _MMIO(0x111b8) 3957#define RS1EN (1 << 31) 3958#define RS2EN (1 << 30) 3959#define RS3EN (1 << 29) 3960#define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 3961#define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 3962#define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 3963#define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 3964#define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 3965#define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 3966#define RSX_STATUS_MASK (7 << 20) 3967#define RSX_STATUS_ON (0 << 20) 3968#define RSX_STATUS_RC1 (1 << 20) 3969#define RSX_STATUS_RC1E (2 << 20) 3970#define RSX_STATUS_RS1 (3 << 20) 3971#define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 3972#define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 3973#define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 3974#define RSX_STATUS_RSVD2 (7 << 20) 3975#define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 3976#define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 3977#define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 3978#define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 3979#define RS1CONTSAV_MASK (3 << 14) 3980#define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 3981#define RS1CONTSAV_RSVD (1 << 14) 3982#define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 3983#define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 3984#define NORMSLEXLAT_MASK (3 << 12) 3985#define SLOW_RS123 (0 << 12) 3986#define SLOW_RS23 (1 << 12) 3987#define SLOW_RS3 (2 << 12) 3988#define NORMAL_RS123 (3 << 12) 3989#define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 3990#define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 3991#define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 3992#define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 3993#define RS_CSTATE_MASK (3 << 4) 3994#define RS_CSTATE_C367_RS1 (0 << 4) 3995#define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 3996#define RS_CSTATE_RSVD (2 << 4) 3997#define RS_CSTATE_C367_RS2 (3 << 4) 3998#define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 3999#define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 4000#define VIDCTL _MMIO(0x111c0) 4001#define VIDSTS _MMIO(0x111c8) 4002#define VIDSTART _MMIO(0x111cc) /* 8 bits */ 4003#define MEMSTAT_ILK _MMIO(0x111f8) 4004#define MEMSTAT_VID_MASK 0x7f00 4005#define MEMSTAT_VID_SHIFT 8 4006#define MEMSTAT_PSTATE_MASK 0x00f8 4007#define MEMSTAT_PSTATE_SHIFT 3 4008#define MEMSTAT_MON_ACTV (1 << 2) 4009#define MEMSTAT_SRC_CTL_MASK 0x0003 4010#define MEMSTAT_SRC_CTL_CORE 0 4011#define MEMSTAT_SRC_CTL_TRB 1 4012#define MEMSTAT_SRC_CTL_THM 2 4013#define MEMSTAT_SRC_CTL_STDBY 3 4014#define RCPREVBSYTUPAVG _MMIO(0x113b8) 4015#define RCPREVBSYTDNAVG _MMIO(0x113bc) 4016#define PMMISC _MMIO(0x11214) 4017#define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 4018#define SDEW _MMIO(0x1124c) 4019#define CSIEW0 _MMIO(0x11250) 4020#define CSIEW1 _MMIO(0x11254) 4021#define CSIEW2 _MMIO(0x11258) 4022#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 4023#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 4024#define MCHAFE _MMIO(0x112c0) 4025#define CSIEC _MMIO(0x112e0) 4026#define DMIEC _MMIO(0x112e4) 4027#define DDREC _MMIO(0x112e8) 4028#define PEG0EC _MMIO(0x112ec) 4029#define PEG1EC _MMIO(0x112f0) 4030#define GFXEC _MMIO(0x112f4) 4031#define RPPREVBSYTUPAVG _MMIO(0x113b8) 4032#define RPPREVBSYTDNAVG _MMIO(0x113bc) 4033#define ECR _MMIO(0x11600) 4034#define ECR_GPFE (1 << 31) 4035#define ECR_IMONE (1 << 30) 4036#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 4037#define OGW0 _MMIO(0x11608) 4038#define OGW1 _MMIO(0x1160c) 4039#define EG0 _MMIO(0x11610) 4040#define EG1 _MMIO(0x11614) 4041#define EG2 _MMIO(0x11618) 4042#define EG3 _MMIO(0x1161c) 4043#define EG4 _MMIO(0x11620) 4044#define EG5 _MMIO(0x11624) 4045#define EG6 _MMIO(0x11628) 4046#define EG7 _MMIO(0x1162c) 4047#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 4048#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 4049#define LCFUSE02 _MMIO(0x116c0) 4050#define LCFUSE_HIV_MASK 0x000000ff 4051#define CSIPLL0 _MMIO(0x12c10) 4052#define DDRMPLL1 _MMIO(0X12c20) 4053#define PEG_BAND_GAP_DATA _MMIO(0x14d68) 4054 4055#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 4056#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 4057 4058#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948) 4059#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070) 4060#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994) 4061#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998) 4062#define BXT_RP_STATE_CAP _MMIO(0x138170) 4063#define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 4064 4065/* 4066 * Logical Context regs 4067 */ 4068#define CCID(base) _MMIO((base) + 0x180) 4069#define CCID_EN BIT(0) 4070#define CCID_EXTENDED_STATE_RESTORE BIT(2) 4071#define CCID_EXTENDED_STATE_SAVE BIT(3) 4072/* 4073 * Notes on SNB/IVB/VLV context size: 4074 * - Power context is saved elsewhere (LLC or stolen) 4075 * - Ring/execlist context is saved on SNB, not on IVB 4076 * - Extended context size already includes render context size 4077 * - We always need to follow the extended context size. 4078 * SNB BSpec has comments indicating that we should use the 4079 * render context size instead if execlists are disabled, but 4080 * based on empirical testing that's just nonsense. 4081 * - Pipelined/VF state is saved on SNB/IVB respectively 4082 * - GT1 size just indicates how much of render context 4083 * doesn't need saving on GT1 4084 */ 4085#define CXT_SIZE _MMIO(0x21a0) 4086#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 4087#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 4088#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 4089#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 4090#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 4091#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 4092 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 4093 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 4094#define GEN7_CXT_SIZE _MMIO(0x21a8) 4095#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 4096#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 4097#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 4098#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 4099#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 4100#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 4101#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 4102 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 4103 4104enum { 4105 INTEL_ADVANCED_CONTEXT = 0, 4106 INTEL_LEGACY_32B_CONTEXT, 4107 INTEL_ADVANCED_AD_CONTEXT, 4108 INTEL_LEGACY_64B_CONTEXT 4109}; 4110 4111enum { 4112 FAULT_AND_HANG = 0, 4113 FAULT_AND_HALT, /* Debug only */ 4114 FAULT_AND_STREAM, 4115 FAULT_AND_CONTINUE /* Unsupported */ 4116}; 4117 4118#define GEN8_CTX_VALID (1 << 0) 4119#define GEN8_CTX_FORCE_PD_RESTORE (1 << 1) 4120#define GEN8_CTX_FORCE_RESTORE (1 << 2) 4121#define GEN8_CTX_L3LLC_COHERENT (1 << 5) 4122#define GEN8_CTX_PRIVILEGE (1 << 8) 4123#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 4124 4125#define GEN8_CTX_ID_SHIFT 32 4126#define GEN8_CTX_ID_WIDTH 21 4127#define GEN11_SW_CTX_ID_SHIFT 37 4128#define GEN11_SW_CTX_ID_WIDTH 11 4129#define GEN11_ENGINE_CLASS_SHIFT 61 4130#define GEN11_ENGINE_CLASS_WIDTH 3 4131#define GEN11_ENGINE_INSTANCE_SHIFT 48 4132#define GEN11_ENGINE_INSTANCE_WIDTH 6 4133 4134#define CHV_CLK_CTL1 _MMIO(0x101100) 4135#define VLV_CLK_CTL2 _MMIO(0x101104) 4136#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 4137 4138/* 4139 * Overlay regs 4140 */ 4141 4142#define OVADD _MMIO(0x30000) 4143#define DOVSTA _MMIO(0x30008) 4144#define OC_BUF (0x3 << 20) 4145#define OGAMC5 _MMIO(0x30010) 4146#define OGAMC4 _MMIO(0x30014) 4147#define OGAMC3 _MMIO(0x30018) 4148#define OGAMC2 _MMIO(0x3001c) 4149#define OGAMC1 _MMIO(0x30020) 4150#define OGAMC0 _MMIO(0x30024) 4151 4152/* 4153 * GEN9 clock gating regs 4154 */ 4155#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 4156#define DARBF_GATING_DIS (1 << 27) 4157#define PWM2_GATING_DIS (1 << 14) 4158#define PWM1_GATING_DIS (1 << 13) 4159 4160#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 4161#define TGL_VRH_GATING_DIS REG_BIT(31) 4162 4163#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 4164#define BXT_GMBUS_GATING_DIS (1 << 14) 4165 4166#define _CLKGATE_DIS_PSL_A 0x46520 4167#define _CLKGATE_DIS_PSL_B 0x46524 4168#define _CLKGATE_DIS_PSL_C 0x46528 4169#define DUPS1_GATING_DIS (1 << 15) 4170#define DUPS2_GATING_DIS (1 << 19) 4171#define DUPS3_GATING_DIS (1 << 23) 4172#define DPF_GATING_DIS (1 << 10) 4173#define DPF_RAM_GATING_DIS (1 << 9) 4174#define DPFR_GATING_DIS (1 << 8) 4175 4176#define CLKGATE_DIS_PSL(pipe) \ 4177 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 4178 4179/* 4180 * GEN10 clock gating regs 4181 */ 4182#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 4183#define SARBUNIT_CLKGATE_DIS (1 << 5) 4184#define RCCUNIT_CLKGATE_DIS (1 << 7) 4185#define MSCUNIT_CLKGATE_DIS (1 << 10) 4186#define L3_CLKGATE_DIS REG_BIT(16) 4187#define L3_CR2X_CLKGATE_DIS REG_BIT(17) 4188 4189#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524) 4190#define GWUNIT_CLKGATE_DIS (1 << 16) 4191 4192#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528) 4193#define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 4194 4195#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 4196#define VFUNIT_CLKGATE_DIS REG_BIT(20) 4197#define HSUNIT_CLKGATE_DIS REG_BIT(8) 4198#define VSUNIT_CLKGATE_DIS REG_BIT(3) 4199 4200#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) 4201#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) 4202#define PSDUNIT_CLKGATE_DIS REG_BIT(5) 4203 4204#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) 4205#define CGPSF_CLKGATE_DIS (1 << 3) 4206 4207/* 4208 * Display engine regs 4209 */ 4210 4211/* Pipe A CRC regs */ 4212#define _PIPE_CRC_CTL_A 0x60050 4213#define PIPE_CRC_ENABLE (1 << 31) 4214/* skl+ source selection */ 4215#define PIPE_CRC_SOURCE_PLANE_1_SKL (0 << 28) 4216#define PIPE_CRC_SOURCE_PLANE_2_SKL (2 << 28) 4217#define PIPE_CRC_SOURCE_DMUX_SKL (4 << 28) 4218#define PIPE_CRC_SOURCE_PLANE_3_SKL (6 << 28) 4219#define PIPE_CRC_SOURCE_PLANE_4_SKL (7 << 28) 4220#define PIPE_CRC_SOURCE_PLANE_5_SKL (5 << 28) 4221#define PIPE_CRC_SOURCE_PLANE_6_SKL (3 << 28) 4222#define PIPE_CRC_SOURCE_PLANE_7_SKL (1 << 28) 4223/* ivb+ source selection */ 4224#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 4225#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 4226#define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 4227/* ilk+ source selection */ 4228#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 4229#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 4230#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 4231/* embedded DP port on the north display block, reserved on ivb */ 4232#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 4233#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 4234/* vlv source selection */ 4235#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 4236#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 4237#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 4238/* with DP port the pipe source is invalid */ 4239#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 4240#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 4241#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 4242/* gen3+ source selection */ 4243#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 4244#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 4245#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 4246/* with DP/TV port the pipe source is invalid */ 4247#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 4248#define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 4249#define PIPE_CRC_SOURCE_TV_POST (5 << 28) 4250#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 4251#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 4252/* gen2 doesn't have source selection bits */ 4253#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 4254 4255#define _PIPE_CRC_RES_1_A_IVB 0x60064 4256#define _PIPE_CRC_RES_2_A_IVB 0x60068 4257#define _PIPE_CRC_RES_3_A_IVB 0x6006c 4258#define _PIPE_CRC_RES_4_A_IVB 0x60070 4259#define _PIPE_CRC_RES_5_A_IVB 0x60074 4260 4261#define _PIPE_CRC_RES_RED_A 0x60060 4262#define _PIPE_CRC_RES_GREEN_A 0x60064 4263#define _PIPE_CRC_RES_BLUE_A 0x60068 4264#define _PIPE_CRC_RES_RES1_A_I915 0x6006c 4265#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 4266 4267/* Pipe B CRC regs */ 4268#define _PIPE_CRC_RES_1_B_IVB 0x61064 4269#define _PIPE_CRC_RES_2_B_IVB 0x61068 4270#define _PIPE_CRC_RES_3_B_IVB 0x6106c 4271#define _PIPE_CRC_RES_4_B_IVB 0x61070 4272#define _PIPE_CRC_RES_5_B_IVB 0x61074 4273 4274#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 4275#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 4276#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 4277#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 4278#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 4279#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 4280 4281#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 4282#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 4283#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 4284#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 4285#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 4286 4287/* Pipe A timing regs */ 4288#define _HTOTAL_A 0x60000 4289#define _HBLANK_A 0x60004 4290#define _HSYNC_A 0x60008 4291#define _VTOTAL_A 0x6000c 4292#define _VBLANK_A 0x60010 4293#define _VSYNC_A 0x60014 4294#define _EXITLINE_A 0x60018 4295#define _PIPEASRC 0x6001c 4296#define _BCLRPAT_A 0x60020 4297#define _VSYNCSHIFT_A 0x60028 4298#define _PIPE_MULT_A 0x6002c 4299 4300/* Pipe B timing regs */ 4301#define _HTOTAL_B 0x61000 4302#define _HBLANK_B 0x61004 4303#define _HSYNC_B 0x61008 4304#define _VTOTAL_B 0x6100c 4305#define _VBLANK_B 0x61010 4306#define _VSYNC_B 0x61014 4307#define _PIPEBSRC 0x6101c 4308#define _BCLRPAT_B 0x61020 4309#define _VSYNCSHIFT_B 0x61028 4310#define _PIPE_MULT_B 0x6102c 4311 4312/* DSI 0 timing regs */ 4313#define _HTOTAL_DSI0 0x6b000 4314#define _HSYNC_DSI0 0x6b008 4315#define _VTOTAL_DSI0 0x6b00c 4316#define _VSYNC_DSI0 0x6b014 4317#define _VSYNCSHIFT_DSI0 0x6b028 4318 4319/* DSI 1 timing regs */ 4320#define _HTOTAL_DSI1 0x6b800 4321#define _HSYNC_DSI1 0x6b808 4322#define _VTOTAL_DSI1 0x6b80c 4323#define _VSYNC_DSI1 0x6b814 4324#define _VSYNCSHIFT_DSI1 0x6b828 4325 4326#define TRANSCODER_A_OFFSET 0x60000 4327#define TRANSCODER_B_OFFSET 0x61000 4328#define TRANSCODER_C_OFFSET 0x62000 4329#define CHV_TRANSCODER_C_OFFSET 0x63000 4330#define TRANSCODER_D_OFFSET 0x63000 4331#define TRANSCODER_EDP_OFFSET 0x6f000 4332#define TRANSCODER_DSI0_OFFSET 0x6b000 4333#define TRANSCODER_DSI1_OFFSET 0x6b800 4334 4335#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 4336#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 4337#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 4338#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 4339#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 4340#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 4341#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 4342#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 4343#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 4344#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 4345 4346#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 4347#define EXITLINE_ENABLE REG_BIT(31) 4348#define EXITLINE_MASK REG_GENMASK(12, 0) 4349#define EXITLINE_SHIFT 0 4350 4351/* VRR registers */ 4352#define _TRANS_VRR_CTL_A 0x60420 4353#define _TRANS_VRR_CTL_B 0x61420 4354#define _TRANS_VRR_CTL_C 0x62420 4355#define _TRANS_VRR_CTL_D 0x63420 4356#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 4357#define VRR_CTL_VRR_ENABLE REG_BIT(31) 4358#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 4359#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 4360#define VRR_CTL_LINE_COUNT_MASK REG_GENMASK(10, 3) 4361#define VRR_CTL_SW_FULLLINE_COUNT REG_BIT(0) 4362 4363#define _TRANS_VRR_VMAX_A 0x60424 4364#define _TRANS_VRR_VMAX_B 0x61424 4365#define _TRANS_VRR_VMAX_C 0x62424 4366#define _TRANS_VRR_VMAX_D 0x63424 4367#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 4368#define VRR_VMAX_MASK REG_GENMASK(19, 0) 4369 4370#define _TRANS_VRR_VMIN_A 0x60434 4371#define _TRANS_VRR_VMIN_B 0x61434 4372#define _TRANS_VRR_VMIN_C 0x62434 4373#define _TRANS_VRR_VMIN_D 0x63434 4374#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 4375#define VRR_VMIN_MASK REG_GENMASK(15, 0) 4376 4377#define _TRANS_VRR_VMAXSHIFT_A 0x60428 4378#define _TRANS_VRR_VMAXSHIFT_B 0x61428 4379#define _TRANS_VRR_VMAXSHIFT_C 0x62428 4380#define _TRANS_VRR_VMAXSHIFT_D 0x63428 4381#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 4382 _TRANS_VRR_VMAXSHIFT_A) 4383#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 4384#define VRR_VMAXSHIFT_DEC REG_BIT(16) 4385#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 4386 4387#define _TRANS_VRR_STATUS_A 0x6042C 4388#define _TRANS_VRR_STATUS_B 0x6142C 4389#define _TRANS_VRR_STATUS_C 0x6242C 4390#define _TRANS_VRR_STATUS_D 0x6342C 4391#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 4392#define VRR_STATUS_VMAX_REACHED REG_BIT(31) 4393#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 4394#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 4395#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 4396#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 4397#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 4398#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 4399#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 4400#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 4401#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 4402#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 4403#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 4404#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 4405#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 4406 4407#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 4408#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 4409#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 4410#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 4411#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 4412 _TRANS_VRR_VTOTAL_PREV_A) 4413#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 4414#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 4415#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 4416#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 4417 4418#define _TRANS_VRR_FLIPLINE_A 0x60438 4419#define _TRANS_VRR_FLIPLINE_B 0x61438 4420#define _TRANS_VRR_FLIPLINE_C 0x62438 4421#define _TRANS_VRR_FLIPLINE_D 0x63438 4422#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 4423 _TRANS_VRR_FLIPLINE_A) 4424#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 4425 4426#define _TRANS_VRR_STATUS2_A 0x6043C 4427#define _TRANS_VRR_STATUS2_B 0x6143C 4428#define _TRANS_VRR_STATUS2_C 0x6243C 4429#define _TRANS_VRR_STATUS2_D 0x6343C 4430#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 4431#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 4432 4433#define _TRANS_PUSH_A 0x60A70 4434#define _TRANS_PUSH_B 0x61A70 4435#define _TRANS_PUSH_C 0x62A70 4436#define _TRANS_PUSH_D 0x63A70 4437#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 4438#define TRANS_PUSH_EN REG_BIT(31) 4439#define TRANS_PUSH_SEND REG_BIT(30) 4440 4441/* 4442 * HSW+ eDP PSR registers 4443 * 4444 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 4445 * instance of it 4446 */ 4447#define _HSW_EDP_PSR_BASE 0x64800 4448#define _SRD_CTL_A 0x60800 4449#define _SRD_CTL_EDP 0x6f800 4450#define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust) 4451#define EDP_PSR_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_CTL_A)) 4452#define EDP_PSR_ENABLE (1 << 31) 4453#define BDW_PSR_SINGLE_FRAME (1 << 30) 4454#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 4455#define EDP_PSR_LINK_STANDBY (1 << 27) 4456#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 4457#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 4458#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 4459#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 4460#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 4461#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 4462#define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 4463#define EDP_PSR_TP1_TP2_SEL (0 << 11) 4464#define EDP_PSR_TP1_TP3_SEL (1 << 11) 4465#define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 4466#define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 4467#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 4468#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 4469#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 4470#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 4471#define EDP_PSR_TP1_TIME_500us (0 << 4) 4472#define EDP_PSR_TP1_TIME_100us (1 << 4) 4473#define EDP_PSR_TP1_TIME_2500us (2 << 4) 4474#define EDP_PSR_TP1_TIME_0us (3 << 4) 4475#define EDP_PSR_IDLE_FRAME_SHIFT 0 4476 4477/* 4478 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 4479 * to transcoder and bits defined for each one as if using no shift (i.e. as if 4480 * it was for TRANSCODER_EDP) 4481 */ 4482#define EDP_PSR_IMR _MMIO(0x64834) 4483#define EDP_PSR_IIR _MMIO(0x64838) 4484#define _PSR_IMR_A 0x60814 4485#define _PSR_IIR_A 0x60818 4486#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 4487#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 4488#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 4489 0 : ((trans) - TRANSCODER_A + 1) * 8) 4490#define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) 4491#define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) 4492#define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) 4493#define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) 4494 4495#define _SRD_AUX_CTL_A 0x60810 4496#define _SRD_AUX_CTL_EDP 0x6f810 4497#define EDP_PSR_AUX_CTL(tran) _MMIO(_PSR_ADJ(tran, _SRD_AUX_CTL_A)) 4498#define EDP_PSR_AUX_CTL_TIME_OUT_MASK (3 << 26) 4499#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 4500#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK (0xf << 16) 4501#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT (1 << 11) 4502#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff) 4503 4504#define _SRD_AUX_DATA_A 0x60814 4505#define _SRD_AUX_DATA_EDP 0x6f814 4506#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_PSR_ADJ(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ 4507 4508#define _SRD_STATUS_A 0x60840 4509#define _SRD_STATUS_EDP 0x6f840 4510#define EDP_PSR_STATUS(tran) _MMIO(_PSR_ADJ(tran, _SRD_STATUS_A)) 4511#define EDP_PSR_STATUS_STATE_MASK (7 << 29) 4512#define EDP_PSR_STATUS_STATE_SHIFT 29 4513#define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 4514#define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 4515#define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 4516#define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 4517#define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 4518#define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 4519#define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 4520#define EDP_PSR_STATUS_LINK_MASK (3 << 26) 4521#define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 4522#define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 4523#define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 4524#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 4525#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 4526#define EDP_PSR_STATUS_COUNT_SHIFT 16 4527#define EDP_PSR_STATUS_COUNT_MASK 0xf 4528#define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 4529#define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 4530#define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 4531#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 4532#define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 4533#define EDP_PSR_STATUS_IDLE_MASK 0xf 4534 4535#define _SRD_PERF_CNT_A 0x60844 4536#define _SRD_PERF_CNT_EDP 0x6f844 4537#define EDP_PSR_PERF_CNT(tran) _MMIO(_PSR_ADJ(tran, _SRD_PERF_CNT_A)) 4538#define EDP_PSR_PERF_CNT_MASK 0xffffff 4539 4540/* PSR_MASK on SKL+ */ 4541#define _SRD_DEBUG_A 0x60860 4542#define _SRD_DEBUG_EDP 0x6f860 4543#define EDP_PSR_DEBUG(tran) _MMIO(_PSR_ADJ(tran, _SRD_DEBUG_A)) 4544#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 4545#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 4546#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 4547#define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 4548#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 4549#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 4550 4551#define _PSR2_CTL_A 0x60900 4552#define _PSR2_CTL_EDP 0x6f900 4553#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 4554#define EDP_PSR2_ENABLE (1 << 31) 4555#define EDP_SU_TRACK_ENABLE (1 << 30) 4556#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 4557#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 4558#define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ 4559#define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ 4560#define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 4561#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 4562#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 4563#define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 4564#define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 4565#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 4566#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) 4567#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 4568#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 4569#define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 4570#define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 4571#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 4572#define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) 4573#define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 4574#define EDP_PSR2_TP2_TIME_500us (0 << 8) 4575#define EDP_PSR2_TP2_TIME_100us (1 << 8) 4576#define EDP_PSR2_TP2_TIME_2500us (2 << 8) 4577#define EDP_PSR2_TP2_TIME_50us (3 << 8) 4578#define EDP_PSR2_TP2_TIME_MASK (3 << 8) 4579#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 4580#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 4581#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 4582#define EDP_PSR2_IDLE_FRAME_MASK 0xf 4583#define EDP_PSR2_IDLE_FRAME_SHIFT 0 4584 4585#define _PSR_EVENT_TRANS_A 0x60848 4586#define _PSR_EVENT_TRANS_B 0x61848 4587#define _PSR_EVENT_TRANS_C 0x62848 4588#define _PSR_EVENT_TRANS_D 0x63848 4589#define _PSR_EVENT_TRANS_EDP 0x6f848 4590#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 4591#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 4592#define PSR_EVENT_PSR2_DISABLED (1 << 16) 4593#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 4594#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 4595#define PSR_EVENT_GRAPHICS_RESET (1 << 12) 4596#define PSR_EVENT_PCH_INTERRUPT (1 << 11) 4597#define PSR_EVENT_MEMORY_UP (1 << 10) 4598#define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 4599#define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 4600#define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 4601#define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 4602#define PSR_EVENT_HDCP_ENABLE (1 << 4) 4603#define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 4604#define PSR_EVENT_VBI_ENABLE (1 << 2) 4605#define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 4606#define PSR_EVENT_PSR_DISABLE (1 << 0) 4607 4608#define _PSR2_STATUS_A 0x60940 4609#define _PSR2_STATUS_EDP 0x6f940 4610#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 4611#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28) 4612#define EDP_PSR2_STATUS_STATE_SHIFT 28 4613 4614#define _PSR2_SU_STATUS_A 0x60914 4615#define _PSR2_SU_STATUS_EDP 0x6f914 4616#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4) 4617#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 4618#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 4619#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 4620#define PSR2_SU_STATUS_FRAMES 8 4621 4622#define _PSR2_MAN_TRK_CTL_A 0x60910 4623#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 4624#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 4625#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 4626#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 4627#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 4628#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 4629#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 4630#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 4631#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 4632#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 4633 4634/* VGA port control */ 4635#define ADPA _MMIO(0x61100) 4636#define PCH_ADPA _MMIO(0xe1100) 4637#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 4638 4639#define ADPA_DAC_ENABLE (1 << 31) 4640#define ADPA_DAC_DISABLE 0 4641#define ADPA_PIPE_SEL_SHIFT 30 4642#define ADPA_PIPE_SEL_MASK (1 << 30) 4643#define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 4644#define ADPA_PIPE_SEL_SHIFT_CPT 29 4645#define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 4646#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4647#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 4648#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 4649#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 4650#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 4651#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 4652#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 4653#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 4654#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 4655#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 4656#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 4657#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 4658#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 4659#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 4660#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 4661#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 4662#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 4663#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 4664#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 4665#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 4666#define ADPA_USE_VGA_HVPOLARITY (1 << 15) 4667#define ADPA_SETS_HVPOLARITY 0 4668#define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 4669#define ADPA_VSYNC_CNTL_ENABLE 0 4670#define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 4671#define ADPA_HSYNC_CNTL_ENABLE 0 4672#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 4673#define ADPA_VSYNC_ACTIVE_LOW 0 4674#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 4675#define ADPA_HSYNC_ACTIVE_LOW 0 4676#define ADPA_DPMS_MASK (~(3 << 10)) 4677#define ADPA_DPMS_ON (0 << 10) 4678#define ADPA_DPMS_SUSPEND (1 << 10) 4679#define ADPA_DPMS_STANDBY (2 << 10) 4680#define ADPA_DPMS_OFF (3 << 10) 4681 4682 4683/* Hotplug control (945+ only) */ 4684#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 4685#define PORTB_HOTPLUG_INT_EN (1 << 29) 4686#define PORTC_HOTPLUG_INT_EN (1 << 28) 4687#define PORTD_HOTPLUG_INT_EN (1 << 27) 4688#define SDVOB_HOTPLUG_INT_EN (1 << 26) 4689#define SDVOC_HOTPLUG_INT_EN (1 << 25) 4690#define TV_HOTPLUG_INT_EN (1 << 18) 4691#define CRT_HOTPLUG_INT_EN (1 << 9) 4692#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 4693 PORTC_HOTPLUG_INT_EN | \ 4694 PORTD_HOTPLUG_INT_EN | \ 4695 SDVOC_HOTPLUG_INT_EN | \ 4696 SDVOB_HOTPLUG_INT_EN | \ 4697 CRT_HOTPLUG_INT_EN) 4698#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 4699#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 4700/* must use period 64 on GM45 according to docs */ 4701#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 4702#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 4703#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 4704#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 4705#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 4706#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 4707#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 4708#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 4709#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 4710#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 4711#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 4712#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 4713 4714#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 4715/* 4716 * HDMI/DP bits are g4x+ 4717 * 4718 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 4719 * Please check the detailed lore in the commit message for for experimental 4720 * evidence. 4721 */ 4722/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 4723#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 4724#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 4725#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 4726/* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 4727#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 4728#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 4729#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 4730#define PORTD_HOTPLUG_INT_STATUS (3 << 21) 4731#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 4732#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 4733#define PORTC_HOTPLUG_INT_STATUS (3 << 19) 4734#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 4735#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 4736#define PORTB_HOTPLUG_INT_STATUS (3 << 17) 4737#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 4738#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 4739/* CRT/TV common between gen3+ */ 4740#define CRT_HOTPLUG_INT_STATUS (1 << 11) 4741#define TV_HOTPLUG_INT_STATUS (1 << 10) 4742#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 4743#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 4744#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 4745#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 4746#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 4747#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 4748#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 4749#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 4750 4751/* SDVO is different across gen3/4 */ 4752#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 4753#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 4754/* 4755 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 4756 * since reality corrobates that they're the same as on gen3. But keep these 4757 * bits here (and the comment!) to help any other lost wanderers back onto the 4758 * right tracks. 4759 */ 4760#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 4761#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 4762#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 4763#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 4764#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 4765 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 4766 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 4767 PORTB_HOTPLUG_INT_STATUS | \ 4768 PORTC_HOTPLUG_INT_STATUS | \ 4769 PORTD_HOTPLUG_INT_STATUS) 4770 4771#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 4772 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 4773 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 4774 PORTB_HOTPLUG_INT_STATUS | \ 4775 PORTC_HOTPLUG_INT_STATUS | \ 4776 PORTD_HOTPLUG_INT_STATUS) 4777 4778/* SDVO and HDMI port control. 4779 * The same register may be used for SDVO or HDMI */ 4780#define _GEN3_SDVOB 0x61140 4781#define _GEN3_SDVOC 0x61160 4782#define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 4783#define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 4784#define GEN4_HDMIB GEN3_SDVOB 4785#define GEN4_HDMIC GEN3_SDVOC 4786#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 4787#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 4788#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 4789#define PCH_SDVOB _MMIO(0xe1140) 4790#define PCH_HDMIB PCH_SDVOB 4791#define PCH_HDMIC _MMIO(0xe1150) 4792#define PCH_HDMID _MMIO(0xe1160) 4793 4794#define PORT_DFT_I9XX _MMIO(0x61150) 4795#define DC_BALANCE_RESET (1 << 25) 4796#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 4797#define DC_BALANCE_RESET_VLV (1 << 31) 4798#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 4799#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */ 4800#define PIPE_B_SCRAMBLE_RESET (1 << 1) 4801#define PIPE_A_SCRAMBLE_RESET (1 << 0) 4802 4803/* Gen 3 SDVO bits: */ 4804#define SDVO_ENABLE (1 << 31) 4805#define SDVO_PIPE_SEL_SHIFT 30 4806#define SDVO_PIPE_SEL_MASK (1 << 30) 4807#define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 4808#define SDVO_STALL_SELECT (1 << 29) 4809#define SDVO_INTERRUPT_ENABLE (1 << 26) 4810/* 4811 * 915G/GM SDVO pixel multiplier. 4812 * Programmed value is multiplier - 1, up to 5x. 4813 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 4814 */ 4815#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 4816#define SDVO_PORT_MULTIPLY_SHIFT 23 4817#define SDVO_PHASE_SELECT_MASK (15 << 19) 4818#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 4819#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 4820#define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 4821#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 4822#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 4823#define SDVO_DETECTED (1 << 2) 4824/* Bits to be preserved when writing */ 4825#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 4826 SDVO_INTERRUPT_ENABLE) 4827#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 4828 4829/* Gen 4 SDVO/HDMI bits: */ 4830#define SDVO_COLOR_FORMAT_8bpc (0 << 26) 4831#define SDVO_COLOR_FORMAT_MASK (7 << 26) 4832#define SDVO_ENCODING_SDVO (0 << 10) 4833#define SDVO_ENCODING_HDMI (2 << 10) 4834#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 4835#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 4836#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 4837#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 4838/* VSYNC/HSYNC bits new with 965, default is to be set */ 4839#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 4840#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 4841 4842/* Gen 5 (IBX) SDVO/HDMI bits: */ 4843#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 4844#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 4845 4846/* Gen 6 (CPT) SDVO/HDMI bits: */ 4847#define SDVO_PIPE_SEL_SHIFT_CPT 29 4848#define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 4849#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4850 4851/* CHV SDVO/HDMI bits: */ 4852#define SDVO_PIPE_SEL_SHIFT_CHV 24 4853#define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 4854#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 4855 4856 4857/* DVO port control */ 4858#define _DVOA 0x61120 4859#define DVOA _MMIO(_DVOA) 4860#define _DVOB 0x61140 4861#define DVOB _MMIO(_DVOB) 4862#define _DVOC 0x61160 4863#define DVOC _MMIO(_DVOC) 4864#define DVO_ENABLE (1 << 31) 4865#define DVO_PIPE_SEL_SHIFT 30 4866#define DVO_PIPE_SEL_MASK (1 << 30) 4867#define DVO_PIPE_SEL(pipe) ((pipe) << 30) 4868#define DVO_PIPE_STALL_UNUSED (0 << 28) 4869#define DVO_PIPE_STALL (1 << 28) 4870#define DVO_PIPE_STALL_TV (2 << 28) 4871#define DVO_PIPE_STALL_MASK (3 << 28) 4872#define DVO_USE_VGA_SYNC (1 << 15) 4873#define DVO_DATA_ORDER_I740 (0 << 14) 4874#define DVO_DATA_ORDER_FP (1 << 14) 4875#define DVO_VSYNC_DISABLE (1 << 11) 4876#define DVO_HSYNC_DISABLE (1 << 10) 4877#define DVO_VSYNC_TRISTATE (1 << 9) 4878#define DVO_HSYNC_TRISTATE (1 << 8) 4879#define DVO_BORDER_ENABLE (1 << 7) 4880#define DVO_DATA_ORDER_GBRG (1 << 6) 4881#define DVO_DATA_ORDER_RGGB (0 << 6) 4882#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 4883#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 4884#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 4885#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 4886#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 4887#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 4888#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 4889#define DVO_PRESERVE_MASK (0x7 << 24) 4890#define DVOA_SRCDIM _MMIO(0x61124) 4891#define DVOB_SRCDIM _MMIO(0x61144) 4892#define DVOC_SRCDIM _MMIO(0x61164) 4893#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 4894#define DVO_SRCDIM_VERTICAL_SHIFT 0 4895 4896/* LVDS port control */ 4897#define LVDS _MMIO(0x61180) 4898/* 4899 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 4900 * the DPLL semantics change when the LVDS is assigned to that pipe. 4901 */ 4902#define LVDS_PORT_EN (1 << 31) 4903/* Selects pipe B for LVDS data. Must be set on pre-965. */ 4904#define LVDS_PIPE_SEL_SHIFT 30 4905#define LVDS_PIPE_SEL_MASK (1 << 30) 4906#define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 4907#define LVDS_PIPE_SEL_SHIFT_CPT 29 4908#define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 4909#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 4910/* LVDS dithering flag on 965/g4x platform */ 4911#define LVDS_ENABLE_DITHER (1 << 25) 4912/* LVDS sync polarity flags. Set to invert (i.e. negative) */ 4913#define LVDS_VSYNC_POLARITY (1 << 21) 4914#define LVDS_HSYNC_POLARITY (1 << 20) 4915 4916/* Enable border for unscaled (or aspect-scaled) display */ 4917#define LVDS_BORDER_ENABLE (1 << 15) 4918/* 4919 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 4920 * pixel. 4921 */ 4922#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 4923#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 4924#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 4925/* 4926 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 4927 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 4928 * on. 4929 */ 4930#define LVDS_A3_POWER_MASK (3 << 6) 4931#define LVDS_A3_POWER_DOWN (0 << 6) 4932#define LVDS_A3_POWER_UP (3 << 6) 4933/* 4934 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 4935 * is set. 4936 */ 4937#define LVDS_CLKB_POWER_MASK (3 << 4) 4938#define LVDS_CLKB_POWER_DOWN (0 << 4) 4939#define LVDS_CLKB_POWER_UP (3 << 4) 4940/* 4941 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 4942 * setting for whether we are in dual-channel mode. The B3 pair will 4943 * additionally only be powered up when LVDS_A3_POWER_UP is set. 4944 */ 4945#define LVDS_B0B3_POWER_MASK (3 << 2) 4946#define LVDS_B0B3_POWER_DOWN (0 << 2) 4947#define LVDS_B0B3_POWER_UP (3 << 2) 4948 4949/* Video Data Island Packet control */ 4950#define VIDEO_DIP_DATA _MMIO(0x61178) 4951/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 4952 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 4953 * of the infoframe structure specified by CEA-861. */ 4954#define VIDEO_DIP_DATA_SIZE 32 4955#define VIDEO_DIP_GMP_DATA_SIZE 36 4956#define VIDEO_DIP_VSC_DATA_SIZE 36 4957#define VIDEO_DIP_PPS_DATA_SIZE 132 4958#define VIDEO_DIP_CTL _MMIO(0x61170) 4959/* Pre HSW: */ 4960#define VIDEO_DIP_ENABLE (1 << 31) 4961#define VIDEO_DIP_PORT(port) ((port) << 29) 4962#define VIDEO_DIP_PORT_MASK (3 << 29) 4963#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 4964#define VIDEO_DIP_ENABLE_AVI (1 << 21) 4965#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 4966#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 4967#define VIDEO_DIP_ENABLE_SPD (8 << 21) 4968#define VIDEO_DIP_SELECT_AVI (0 << 19) 4969#define VIDEO_DIP_SELECT_VENDOR (1 << 19) 4970#define VIDEO_DIP_SELECT_GAMUT (2 << 19) 4971#define VIDEO_DIP_SELECT_SPD (3 << 19) 4972#define VIDEO_DIP_SELECT_MASK (3 << 19) 4973#define VIDEO_DIP_FREQ_ONCE (0 << 16) 4974#define VIDEO_DIP_FREQ_VSYNC (1 << 16) 4975#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 4976#define VIDEO_DIP_FREQ_MASK (3 << 16) 4977/* HSW and later: */ 4978#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 4979#define PSR_VSC_BIT_7_SET (1 << 27) 4980#define VSC_SELECT_MASK (0x3 << 25) 4981#define VSC_SELECT_SHIFT 25 4982#define VSC_DIP_HW_HEA_DATA (0 << 25) 4983#define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 4984#define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 4985#define VSC_DIP_SW_HEA_DATA (3 << 25) 4986#define VDIP_ENABLE_PPS (1 << 24) 4987#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 4988#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 4989#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 4990#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 4991#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 4992#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 4993 4994/* Panel power sequencing */ 4995#define PPS_BASE 0x61200 4996#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 4997#define PCH_PPS_BASE 0xC7200 4998 4999#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 5000 PPS_BASE + (reg) + \ 5001 (pps_idx) * 0x100) 5002 5003#define _PP_STATUS 0x61200 5004#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 5005#define PP_ON REG_BIT(31) 5006/* 5007 * Indicates that all dependencies of the panel are on: 5008 * 5009 * - PLL enabled 5010 * - pipe enabled 5011 * - LVDS/DVOB/DVOC on 5012 */ 5013#define PP_READY REG_BIT(30) 5014#define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 5015#define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 5016#define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 5017#define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 5018#define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 5019#define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 5020#define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 5021#define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 5022#define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 5023#define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 5024#define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 5025#define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 5026#define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 5027#define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 5028#define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 5029 5030#define _PP_CONTROL 0x61204 5031#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 5032#define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 5033#define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 5034#define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 5035#define EDP_FORCE_VDD REG_BIT(3) 5036#define EDP_BLC_ENABLE REG_BIT(2) 5037#define PANEL_POWER_RESET REG_BIT(1) 5038#define PANEL_POWER_ON REG_BIT(0) 5039 5040#define _PP_ON_DELAYS 0x61208 5041#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 5042#define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 5043#define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 5044#define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 5045#define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 5046#define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 5047#define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 5048#define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 5049#define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 5050 5051#define _PP_OFF_DELAYS 0x6120C 5052#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 5053#define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 5054#define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 5055 5056#define _PP_DIVISOR 0x61210 5057#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 5058#define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 5059#define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 5060 5061/* Panel fitting */ 5062#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 5063#define PFIT_ENABLE (1 << 31) 5064#define PFIT_PIPE_MASK (3 << 29) 5065#define PFIT_PIPE_SHIFT 29 5066#define PFIT_PIPE(pipe) ((pipe) << 29) 5067#define VERT_INTERP_DISABLE (0 << 10) 5068#define VERT_INTERP_BILINEAR (1 << 10) 5069#define VERT_INTERP_MASK (3 << 10) 5070#define VERT_AUTO_SCALE (1 << 9) 5071#define HORIZ_INTERP_DISABLE (0 << 6) 5072#define HORIZ_INTERP_BILINEAR (1 << 6) 5073#define HORIZ_INTERP_MASK (3 << 6) 5074#define HORIZ_AUTO_SCALE (1 << 5) 5075#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 5076#define PFIT_FILTER_FUZZY (0 << 24) 5077#define PFIT_SCALING_AUTO (0 << 26) 5078#define PFIT_SCALING_PROGRAMMED (1 << 26) 5079#define PFIT_SCALING_PILLAR (2 << 26) 5080#define PFIT_SCALING_LETTER (3 << 26) 5081#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 5082/* Pre-965 */ 5083#define PFIT_VERT_SCALE_SHIFT 20 5084#define PFIT_VERT_SCALE_MASK 0xfff00000 5085#define PFIT_HORIZ_SCALE_SHIFT 4 5086#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 5087/* 965+ */ 5088#define PFIT_VERT_SCALE_SHIFT_965 16 5089#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 5090#define PFIT_HORIZ_SCALE_SHIFT_965 0 5091#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 5092 5093#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 5094 5095#define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 5096#define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 5097#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 5098 _VLV_BLC_PWM_CTL2_B) 5099 5100#define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 5101#define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 5102#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 5103 _VLV_BLC_PWM_CTL_B) 5104 5105#define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 5106#define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 5107#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 5108 _VLV_BLC_HIST_CTL_B) 5109 5110/* Backlight control */ 5111#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 5112#define BLM_PWM_ENABLE (1 << 31) 5113#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 5114#define BLM_PIPE_SELECT (1 << 29) 5115#define BLM_PIPE_SELECT_IVB (3 << 29) 5116#define BLM_PIPE_A (0 << 29) 5117#define BLM_PIPE_B (1 << 29) 5118#define BLM_PIPE_C (2 << 29) /* ivb + */ 5119#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 5120#define BLM_TRANSCODER_B BLM_PIPE_B 5121#define BLM_TRANSCODER_C BLM_PIPE_C 5122#define BLM_TRANSCODER_EDP (3 << 29) 5123#define BLM_PIPE(pipe) ((pipe) << 29) 5124#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 5125#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 5126#define BLM_PHASE_IN_ENABLE (1 << 25) 5127#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 5128#define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 5129#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 5130#define BLM_PHASE_IN_COUNT_SHIFT (8) 5131#define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 5132#define BLM_PHASE_IN_INCR_SHIFT (0) 5133#define BLM_PHASE_IN_INCR_MASK (0xff << 0) 5134#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 5135/* 5136 * This is the most significant 15 bits of the number of backlight cycles in a 5137 * complete cycle of the modulated backlight control. 5138 * 5139 * The actual value is this field multiplied by two. 5140 */ 5141#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 5142#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 5143#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 5144/* 5145 * This is the number of cycles out of the backlight modulation cycle for which 5146 * the backlight is on. 5147 * 5148 * This field must be no greater than the number of cycles in the complete 5149 * backlight modulation cycle. 5150 */ 5151#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 5152#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 5153#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 5154#define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 5155 5156#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 5157#define BLM_HISTOGRAM_ENABLE (1 << 31) 5158 5159/* New registers for PCH-split platforms. Safe where new bits show up, the 5160 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 5161#define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 5162#define BLC_PWM_CPU_CTL _MMIO(0x48254) 5163 5164#define HSW_BLC_PWM2_CTL _MMIO(0x48350) 5165 5166/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 5167 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 5168#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 5169#define BLM_PCH_PWM_ENABLE (1 << 31) 5170#define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 5171#define BLM_PCH_POLARITY (1 << 29) 5172#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 5173 5174#define UTIL_PIN_CTL _MMIO(0x48400) 5175#define UTIL_PIN_ENABLE (1 << 31) 5176#define UTIL_PIN_PIPE_MASK (3 << 29) 5177#define UTIL_PIN_PIPE(x) ((x) << 29) 5178#define UTIL_PIN_MODE_MASK (0xf << 24) 5179#define UTIL_PIN_MODE_DATA (0 << 24) 5180#define UTIL_PIN_MODE_PWM (1 << 24) 5181#define UTIL_PIN_MODE_VBLANK (4 << 24) 5182#define UTIL_PIN_MODE_VSYNC (5 << 24) 5183#define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) 5184#define UTIL_PIN_OUTPUT_DATA (1 << 23) 5185#define UTIL_PIN_POLARITY (1 << 22) 5186#define UTIL_PIN_DIRECTION_INPUT (1 << 19) 5187#define UTIL_PIN_INPUT_DATA (1 << 16) 5188 5189/* BXT backlight register definition. */ 5190#define _BXT_BLC_PWM_CTL1 0xC8250 5191#define BXT_BLC_PWM_ENABLE (1 << 31) 5192#define BXT_BLC_PWM_POLARITY (1 << 29) 5193#define _BXT_BLC_PWM_FREQ1 0xC8254 5194#define _BXT_BLC_PWM_DUTY1 0xC8258 5195 5196#define _BXT_BLC_PWM_CTL2 0xC8350 5197#define _BXT_BLC_PWM_FREQ2 0xC8354 5198#define _BXT_BLC_PWM_DUTY2 0xC8358 5199 5200#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 5201 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 5202#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 5203 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 5204#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 5205 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 5206 5207#define PCH_GTC_CTL _MMIO(0xe7000) 5208#define PCH_GTC_ENABLE (1 << 31) 5209 5210/* TV port control */ 5211#define TV_CTL _MMIO(0x68000) 5212/* Enables the TV encoder */ 5213# define TV_ENC_ENABLE (1 << 31) 5214/* Sources the TV encoder input from pipe B instead of A. */ 5215# define TV_ENC_PIPE_SEL_SHIFT 30 5216# define TV_ENC_PIPE_SEL_MASK (1 << 30) 5217# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 5218/* Outputs composite video (DAC A only) */ 5219# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 5220/* Outputs SVideo video (DAC B/C) */ 5221# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 5222/* Outputs Component video (DAC A/B/C) */ 5223# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 5224/* Outputs Composite and SVideo (DAC A/B/C) */ 5225# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 5226# define TV_TRILEVEL_SYNC (1 << 21) 5227/* Enables slow sync generation (945GM only) */ 5228# define TV_SLOW_SYNC (1 << 20) 5229/* Selects 4x oversampling for 480i and 576p */ 5230# define TV_OVERSAMPLE_4X (0 << 18) 5231/* Selects 2x oversampling for 720p and 1080i */ 5232# define TV_OVERSAMPLE_2X (1 << 18) 5233/* Selects no oversampling for 1080p */ 5234# define TV_OVERSAMPLE_NONE (2 << 18) 5235/* Selects 8x oversampling */ 5236# define TV_OVERSAMPLE_8X (3 << 18) 5237# define TV_OVERSAMPLE_MASK (3 << 18) 5238/* Selects progressive mode rather than interlaced */ 5239# define TV_PROGRESSIVE (1 << 17) 5240/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 5241# define TV_PAL_BURST (1 << 16) 5242/* Field for setting delay of Y compared to C */ 5243# define TV_YC_SKEW_MASK (7 << 12) 5244/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 5245# define TV_ENC_SDP_FIX (1 << 11) 5246/* 5247 * Enables a fix for the 915GM only. 5248 * 5249 * Not sure what it does. 5250 */ 5251# define TV_ENC_C0_FIX (1 << 10) 5252/* Bits that must be preserved by software */ 5253# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 5254# define TV_FUSE_STATE_MASK (3 << 4) 5255/* Read-only state that reports all features enabled */ 5256# define TV_FUSE_STATE_ENABLED (0 << 4) 5257/* Read-only state that reports that Macrovision is disabled in hardware*/ 5258# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 5259/* Read-only state that reports that TV-out is disabled in hardware. */ 5260# define TV_FUSE_STATE_DISABLED (2 << 4) 5261/* Normal operation */ 5262# define TV_TEST_MODE_NORMAL (0 << 0) 5263/* Encoder test pattern 1 - combo pattern */ 5264# define TV_TEST_MODE_PATTERN_1 (1 << 0) 5265/* Encoder test pattern 2 - full screen vertical 75% color bars */ 5266# define TV_TEST_MODE_PATTERN_2 (2 << 0) 5267/* Encoder test pattern 3 - full screen horizontal 75% color bars */ 5268# define TV_TEST_MODE_PATTERN_3 (3 << 0) 5269/* Encoder test pattern 4 - random noise */ 5270# define TV_TEST_MODE_PATTERN_4 (4 << 0) 5271/* Encoder test pattern 5 - linear color ramps */ 5272# define TV_TEST_MODE_PATTERN_5 (5 << 0) 5273/* 5274 * This test mode forces the DACs to 50% of full output. 5275 * 5276 * This is used for load detection in combination with TVDAC_SENSE_MASK 5277 */ 5278# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 5279# define TV_TEST_MODE_MASK (7 << 0) 5280 5281#define TV_DAC _MMIO(0x68004) 5282# define TV_DAC_SAVE 0x00ffff00 5283/* 5284 * Reports that DAC state change logic has reported change (RO). 5285 * 5286 * This gets cleared when TV_DAC_STATE_EN is cleared 5287*/ 5288# define TVDAC_STATE_CHG (1 << 31) 5289# define TVDAC_SENSE_MASK (7 << 28) 5290/* Reports that DAC A voltage is above the detect threshold */ 5291# define TVDAC_A_SENSE (1 << 30) 5292/* Reports that DAC B voltage is above the detect threshold */ 5293# define TVDAC_B_SENSE (1 << 29) 5294/* Reports that DAC C voltage is above the detect threshold */ 5295# define TVDAC_C_SENSE (1 << 28) 5296/* 5297 * Enables DAC state detection logic, for load-based TV detection. 5298 * 5299 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 5300 * to off, for load detection to work. 5301 */ 5302# define TVDAC_STATE_CHG_EN (1 << 27) 5303/* Sets the DAC A sense value to high */ 5304# define TVDAC_A_SENSE_CTL (1 << 26) 5305/* Sets the DAC B sense value to high */ 5306# define TVDAC_B_SENSE_CTL (1 << 25) 5307/* Sets the DAC C sense value to high */ 5308# define TVDAC_C_SENSE_CTL (1 << 24) 5309/* Overrides the ENC_ENABLE and DAC voltage levels */ 5310# define DAC_CTL_OVERRIDE (1 << 7) 5311/* Sets the slew rate. Must be preserved in software */ 5312# define ENC_TVDAC_SLEW_FAST (1 << 6) 5313# define DAC_A_1_3_V (0 << 4) 5314# define DAC_A_1_1_V (1 << 4) 5315# define DAC_A_0_7_V (2 << 4) 5316# define DAC_A_MASK (3 << 4) 5317# define DAC_B_1_3_V (0 << 2) 5318# define DAC_B_1_1_V (1 << 2) 5319# define DAC_B_0_7_V (2 << 2) 5320# define DAC_B_MASK (3 << 2) 5321# define DAC_C_1_3_V (0 << 0) 5322# define DAC_C_1_1_V (1 << 0) 5323# define DAC_C_0_7_V (2 << 0) 5324# define DAC_C_MASK (3 << 0) 5325 5326/* 5327 * CSC coefficients are stored in a floating point format with 9 bits of 5328 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 5329 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 5330 * -1 (0x3) being the only legal negative value. 5331 */ 5332#define TV_CSC_Y _MMIO(0x68010) 5333# define TV_RY_MASK 0x07ff0000 5334# define TV_RY_SHIFT 16 5335# define TV_GY_MASK 0x00000fff 5336# define TV_GY_SHIFT 0 5337 5338#define TV_CSC_Y2 _MMIO(0x68014) 5339# define TV_BY_MASK 0x07ff0000 5340# define TV_BY_SHIFT 16 5341/* 5342 * Y attenuation for component video. 5343 * 5344 * Stored in 1.9 fixed point. 5345 */ 5346# define TV_AY_MASK 0x000003ff 5347# define TV_AY_SHIFT 0 5348 5349#define TV_CSC_U _MMIO(0x68018) 5350# define TV_RU_MASK 0x07ff0000 5351# define TV_RU_SHIFT 16 5352# define TV_GU_MASK 0x000007ff 5353# define TV_GU_SHIFT 0 5354 5355#define TV_CSC_U2 _MMIO(0x6801c) 5356# define TV_BU_MASK 0x07ff0000 5357# define TV_BU_SHIFT 16 5358/* 5359 * U attenuation for component video. 5360 * 5361 * Stored in 1.9 fixed point. 5362 */ 5363# define TV_AU_MASK 0x000003ff 5364# define TV_AU_SHIFT 0 5365 5366#define TV_CSC_V _MMIO(0x68020) 5367# define TV_RV_MASK 0x0fff0000 5368# define TV_RV_SHIFT 16 5369# define TV_GV_MASK 0x000007ff 5370# define TV_GV_SHIFT 0 5371 5372#define TV_CSC_V2 _MMIO(0x68024) 5373# define TV_BV_MASK 0x07ff0000 5374# define TV_BV_SHIFT 16 5375/* 5376 * V attenuation for component video. 5377 * 5378 * Stored in 1.9 fixed point. 5379 */ 5380# define TV_AV_MASK 0x000007ff 5381# define TV_AV_SHIFT 0 5382 5383#define TV_CLR_KNOBS _MMIO(0x68028) 5384/* 2s-complement brightness adjustment */ 5385# define TV_BRIGHTNESS_MASK 0xff000000 5386# define TV_BRIGHTNESS_SHIFT 24 5387/* Contrast adjustment, as a 2.6 unsigned floating point number */ 5388# define TV_CONTRAST_MASK 0x00ff0000 5389# define TV_CONTRAST_SHIFT 16 5390/* Saturation adjustment, as a 2.6 unsigned floating point number */ 5391# define TV_SATURATION_MASK 0x0000ff00 5392# define TV_SATURATION_SHIFT 8 5393/* Hue adjustment, as an integer phase angle in degrees */ 5394# define TV_HUE_MASK 0x000000ff 5395# define TV_HUE_SHIFT 0 5396 5397#define TV_CLR_LEVEL _MMIO(0x6802c) 5398/* Controls the DAC level for black */ 5399# define TV_BLACK_LEVEL_MASK 0x01ff0000 5400# define TV_BLACK_LEVEL_SHIFT 16 5401/* Controls the DAC level for blanking */ 5402# define TV_BLANK_LEVEL_MASK 0x000001ff 5403# define TV_BLANK_LEVEL_SHIFT 0 5404 5405#define TV_H_CTL_1 _MMIO(0x68030) 5406/* Number of pixels in the hsync. */ 5407# define TV_HSYNC_END_MASK 0x1fff0000 5408# define TV_HSYNC_END_SHIFT 16 5409/* Total number of pixels minus one in the line (display and blanking). */ 5410# define TV_HTOTAL_MASK 0x00001fff 5411# define TV_HTOTAL_SHIFT 0 5412 5413#define TV_H_CTL_2 _MMIO(0x68034) 5414/* Enables the colorburst (needed for non-component color) */ 5415# define TV_BURST_ENA (1 << 31) 5416/* Offset of the colorburst from the start of hsync, in pixels minus one. */ 5417# define TV_HBURST_START_SHIFT 16 5418# define TV_HBURST_START_MASK 0x1fff0000 5419/* Length of the colorburst */ 5420# define TV_HBURST_LEN_SHIFT 0 5421# define TV_HBURST_LEN_MASK 0x0001fff 5422 5423#define TV_H_CTL_3 _MMIO(0x68038) 5424/* End of hblank, measured in pixels minus one from start of hsync */ 5425# define TV_HBLANK_END_SHIFT 16 5426# define TV_HBLANK_END_MASK 0x1fff0000 5427/* Start of hblank, measured in pixels minus one from start of hsync */ 5428# define TV_HBLANK_START_SHIFT 0 5429# define TV_HBLANK_START_MASK 0x0001fff 5430 5431#define TV_V_CTL_1 _MMIO(0x6803c) 5432/* XXX */ 5433# define TV_NBR_END_SHIFT 16 5434# define TV_NBR_END_MASK 0x07ff0000 5435/* XXX */ 5436# define TV_VI_END_F1_SHIFT 8 5437# define TV_VI_END_F1_MASK 0x00003f00 5438/* XXX */ 5439# define TV_VI_END_F2_SHIFT 0 5440# define TV_VI_END_F2_MASK 0x0000003f 5441 5442#define TV_V_CTL_2 _MMIO(0x68040) 5443/* Length of vsync, in half lines */ 5444# define TV_VSYNC_LEN_MASK 0x07ff0000 5445# define TV_VSYNC_LEN_SHIFT 16 5446/* Offset of the start of vsync in field 1, measured in one less than the 5447 * number of half lines. 5448 */ 5449# define TV_VSYNC_START_F1_MASK 0x00007f00 5450# define TV_VSYNC_START_F1_SHIFT 8 5451/* 5452 * Offset of the start of vsync in field 2, measured in one less than the 5453 * number of half lines. 5454 */ 5455# define TV_VSYNC_START_F2_MASK 0x0000007f 5456# define TV_VSYNC_START_F2_SHIFT 0 5457 5458#define TV_V_CTL_3 _MMIO(0x68044) 5459/* Enables generation of the equalization signal */ 5460# define TV_EQUAL_ENA (1 << 31) 5461/* Length of vsync, in half lines */ 5462# define TV_VEQ_LEN_MASK 0x007f0000 5463# define TV_VEQ_LEN_SHIFT 16 5464/* Offset of the start of equalization in field 1, measured in one less than 5465 * the number of half lines. 5466 */ 5467# define TV_VEQ_START_F1_MASK 0x0007f00 5468# define TV_VEQ_START_F1_SHIFT 8 5469/* 5470 * Offset of the start of equalization in field 2, measured in one less than 5471 * the number of half lines. 5472 */ 5473# define TV_VEQ_START_F2_MASK 0x000007f 5474# define TV_VEQ_START_F2_SHIFT 0 5475 5476#define TV_V_CTL_4 _MMIO(0x68048) 5477/* 5478 * Offset to start of vertical colorburst, measured in one less than the 5479 * number of lines from vertical start. 5480 */ 5481# define TV_VBURST_START_F1_MASK 0x003f0000 5482# define TV_VBURST_START_F1_SHIFT 16 5483/* 5484 * Offset to the end of vertical colorburst, measured in one less than the 5485 * number of lines from the start of NBR. 5486 */ 5487# define TV_VBURST_END_F1_MASK 0x000000ff 5488# define TV_VBURST_END_F1_SHIFT 0 5489 5490#define TV_V_CTL_5 _MMIO(0x6804c) 5491/* 5492 * Offset to start of vertical colorburst, measured in one less than the 5493 * number of lines from vertical start. 5494 */ 5495# define TV_VBURST_START_F2_MASK 0x003f0000 5496# define TV_VBURST_START_F2_SHIFT 16 5497/* 5498 * Offset to the end of vertical colorburst, measured in one less than the 5499 * number of lines from the start of NBR. 5500 */ 5501# define TV_VBURST_END_F2_MASK 0x000000ff 5502# define TV_VBURST_END_F2_SHIFT 0 5503 5504#define TV_V_CTL_6 _MMIO(0x68050) 5505/* 5506 * Offset to start of vertical colorburst, measured in one less than the 5507 * number of lines from vertical start. 5508 */ 5509# define TV_VBURST_START_F3_MASK 0x003f0000 5510# define TV_VBURST_START_F3_SHIFT 16 5511/* 5512 * Offset to the end of vertical colorburst, measured in one less than the 5513 * number of lines from the start of NBR. 5514 */ 5515# define TV_VBURST_END_F3_MASK 0x000000ff 5516# define TV_VBURST_END_F3_SHIFT 0 5517 5518#define TV_V_CTL_7 _MMIO(0x68054) 5519/* 5520 * Offset to start of vertical colorburst, measured in one less than the 5521 * number of lines from vertical start. 5522 */ 5523# define TV_VBURST_START_F4_MASK 0x003f0000 5524# define TV_VBURST_START_F4_SHIFT 16 5525/* 5526 * Offset to the end of vertical colorburst, measured in one less than the 5527 * number of lines from the start of NBR. 5528 */ 5529# define TV_VBURST_END_F4_MASK 0x000000ff 5530# define TV_VBURST_END_F4_SHIFT 0 5531 5532#define TV_SC_CTL_1 _MMIO(0x68060) 5533/* Turns on the first subcarrier phase generation DDA */ 5534# define TV_SC_DDA1_EN (1 << 31) 5535/* Turns on the first subcarrier phase generation DDA */ 5536# define TV_SC_DDA2_EN (1 << 30) 5537/* Turns on the first subcarrier phase generation DDA */ 5538# define TV_SC_DDA3_EN (1 << 29) 5539/* Sets the subcarrier DDA to reset frequency every other field */ 5540# define TV_SC_RESET_EVERY_2 (0 << 24) 5541/* Sets the subcarrier DDA to reset frequency every fourth field */ 5542# define TV_SC_RESET_EVERY_4 (1 << 24) 5543/* Sets the subcarrier DDA to reset frequency every eighth field */ 5544# define TV_SC_RESET_EVERY_8 (2 << 24) 5545/* Sets the subcarrier DDA to never reset the frequency */ 5546# define TV_SC_RESET_NEVER (3 << 24) 5547/* Sets the peak amplitude of the colorburst.*/ 5548# define TV_BURST_LEVEL_MASK 0x00ff0000 5549# define TV_BURST_LEVEL_SHIFT 16 5550/* Sets the increment of the first subcarrier phase generation DDA */ 5551# define TV_SCDDA1_INC_MASK 0x00000fff 5552# define TV_SCDDA1_INC_SHIFT 0 5553 5554#define TV_SC_CTL_2 _MMIO(0x68064) 5555/* Sets the rollover for the second subcarrier phase generation DDA */ 5556# define TV_SCDDA2_SIZE_MASK 0x7fff0000 5557# define TV_SCDDA2_SIZE_SHIFT 16 5558/* Sets the increent of the second subcarrier phase generation DDA */ 5559# define TV_SCDDA2_INC_MASK 0x00007fff 5560# define TV_SCDDA2_INC_SHIFT 0 5561 5562#define TV_SC_CTL_3 _MMIO(0x68068) 5563/* Sets the rollover for the third subcarrier phase generation DDA */ 5564# define TV_SCDDA3_SIZE_MASK 0x7fff0000 5565# define TV_SCDDA3_SIZE_SHIFT 16 5566/* Sets the increent of the third subcarrier phase generation DDA */ 5567# define TV_SCDDA3_INC_MASK 0x00007fff 5568# define TV_SCDDA3_INC_SHIFT 0 5569 5570#define TV_WIN_POS _MMIO(0x68070) 5571/* X coordinate of the display from the start of horizontal active */ 5572# define TV_XPOS_MASK 0x1fff0000 5573# define TV_XPOS_SHIFT 16 5574/* Y coordinate of the display from the start of vertical active (NBR) */ 5575# define TV_YPOS_MASK 0x00000fff 5576# define TV_YPOS_SHIFT 0 5577 5578#define TV_WIN_SIZE _MMIO(0x68074) 5579/* Horizontal size of the display window, measured in pixels*/ 5580# define TV_XSIZE_MASK 0x1fff0000 5581# define TV_XSIZE_SHIFT 16 5582/* 5583 * Vertical size of the display window, measured in pixels. 5584 * 5585 * Must be even for interlaced modes. 5586 */ 5587# define TV_YSIZE_MASK 0x00000fff 5588# define TV_YSIZE_SHIFT 0 5589 5590#define TV_FILTER_CTL_1 _MMIO(0x68080) 5591/* 5592 * Enables automatic scaling calculation. 5593 * 5594 * If set, the rest of the registers are ignored, and the calculated values can 5595 * be read back from the register. 5596 */ 5597# define TV_AUTO_SCALE (1 << 31) 5598/* 5599 * Disables the vertical filter. 5600 * 5601 * This is required on modes more than 1024 pixels wide */ 5602# define TV_V_FILTER_BYPASS (1 << 29) 5603/* Enables adaptive vertical filtering */ 5604# define TV_VADAPT (1 << 28) 5605# define TV_VADAPT_MODE_MASK (3 << 26) 5606/* Selects the least adaptive vertical filtering mode */ 5607# define TV_VADAPT_MODE_LEAST (0 << 26) 5608/* Selects the moderately adaptive vertical filtering mode */ 5609# define TV_VADAPT_MODE_MODERATE (1 << 26) 5610/* Selects the most adaptive vertical filtering mode */ 5611# define TV_VADAPT_MODE_MOST (3 << 26) 5612/* 5613 * Sets the horizontal scaling factor. 5614 * 5615 * This should be the fractional part of the horizontal scaling factor divided 5616 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 5617 * 5618 * (src width - 1) / ((oversample * dest width) - 1) 5619 */ 5620# define TV_HSCALE_FRAC_MASK 0x00003fff 5621# define TV_HSCALE_FRAC_SHIFT 0 5622 5623#define TV_FILTER_CTL_2 _MMIO(0x68084) 5624/* 5625 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5626 * 5627 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 5628 */ 5629# define TV_VSCALE_INT_MASK 0x00038000 5630# define TV_VSCALE_INT_SHIFT 15 5631/* 5632 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5633 * 5634 * \sa TV_VSCALE_INT_MASK 5635 */ 5636# define TV_VSCALE_FRAC_MASK 0x00007fff 5637# define TV_VSCALE_FRAC_SHIFT 0 5638 5639#define TV_FILTER_CTL_3 _MMIO(0x68088) 5640/* 5641 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 5642 * 5643 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 5644 * 5645 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5646 */ 5647# define TV_VSCALE_IP_INT_MASK 0x00038000 5648# define TV_VSCALE_IP_INT_SHIFT 15 5649/* 5650 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 5651 * 5652 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 5653 * 5654 * \sa TV_VSCALE_IP_INT_MASK 5655 */ 5656# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 5657# define TV_VSCALE_IP_FRAC_SHIFT 0 5658 5659#define TV_CC_CONTROL _MMIO(0x68090) 5660# define TV_CC_ENABLE (1 << 31) 5661/* 5662 * Specifies which field to send the CC data in. 5663 * 5664 * CC data is usually sent in field 0. 5665 */ 5666# define TV_CC_FID_MASK (1 << 27) 5667# define TV_CC_FID_SHIFT 27 5668/* Sets the horizontal position of the CC data. Usually 135. */ 5669# define TV_CC_HOFF_MASK 0x03ff0000 5670# define TV_CC_HOFF_SHIFT 16 5671/* Sets the vertical position of the CC data. Usually 21 */ 5672# define TV_CC_LINE_MASK 0x0000003f 5673# define TV_CC_LINE_SHIFT 0 5674 5675#define TV_CC_DATA _MMIO(0x68094) 5676# define TV_CC_RDY (1 << 31) 5677/* Second word of CC data to be transmitted. */ 5678# define TV_CC_DATA_2_MASK 0x007f0000 5679# define TV_CC_DATA_2_SHIFT 16 5680/* First word of CC data to be transmitted. */ 5681# define TV_CC_DATA_1_MASK 0x0000007f 5682# define TV_CC_DATA_1_SHIFT 0 5683 5684#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 5685#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 5686#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 5687#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 5688 5689/* Display Port */ 5690#define DP_A _MMIO(0x64000) /* eDP */ 5691#define DP_B _MMIO(0x64100) 5692#define DP_C _MMIO(0x64200) 5693#define DP_D _MMIO(0x64300) 5694 5695#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 5696#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 5697#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 5698 5699#define DP_PORT_EN (1 << 31) 5700#define DP_PIPE_SEL_SHIFT 30 5701#define DP_PIPE_SEL_MASK (1 << 30) 5702#define DP_PIPE_SEL(pipe) ((pipe) << 30) 5703#define DP_PIPE_SEL_SHIFT_IVB 29 5704#define DP_PIPE_SEL_MASK_IVB (3 << 29) 5705#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5706#define DP_PIPE_SEL_SHIFT_CHV 16 5707#define DP_PIPE_SEL_MASK_CHV (3 << 16) 5708#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 5709 5710/* Link training mode - select a suitable mode for each stage */ 5711#define DP_LINK_TRAIN_PAT_1 (0 << 28) 5712#define DP_LINK_TRAIN_PAT_2 (1 << 28) 5713#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 5714#define DP_LINK_TRAIN_OFF (3 << 28) 5715#define DP_LINK_TRAIN_MASK (3 << 28) 5716#define DP_LINK_TRAIN_SHIFT 28 5717 5718/* CPT Link training mode */ 5719#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 5720#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 5721#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 5722#define DP_LINK_TRAIN_OFF_CPT (3 << 8) 5723#define DP_LINK_TRAIN_MASK_CPT (7 << 8) 5724#define DP_LINK_TRAIN_SHIFT_CPT 8 5725 5726/* Signal voltages. These are mostly controlled by the other end */ 5727#define DP_VOLTAGE_0_4 (0 << 25) 5728#define DP_VOLTAGE_0_6 (1 << 25) 5729#define DP_VOLTAGE_0_8 (2 << 25) 5730#define DP_VOLTAGE_1_2 (3 << 25) 5731#define DP_VOLTAGE_MASK (7 << 25) 5732#define DP_VOLTAGE_SHIFT 25 5733 5734/* Signal pre-emphasis levels, like voltages, the other end tells us what 5735 * they want 5736 */ 5737#define DP_PRE_EMPHASIS_0 (0 << 22) 5738#define DP_PRE_EMPHASIS_3_5 (1 << 22) 5739#define DP_PRE_EMPHASIS_6 (2 << 22) 5740#define DP_PRE_EMPHASIS_9_5 (3 << 22) 5741#define DP_PRE_EMPHASIS_MASK (7 << 22) 5742#define DP_PRE_EMPHASIS_SHIFT 22 5743 5744/* How many wires to use. I guess 3 was too hard */ 5745#define DP_PORT_WIDTH(width) (((width) - 1) << 19) 5746#define DP_PORT_WIDTH_MASK (7 << 19) 5747#define DP_PORT_WIDTH_SHIFT 19 5748 5749/* Mystic DPCD version 1.1 special mode */ 5750#define DP_ENHANCED_FRAMING (1 << 18) 5751 5752/* eDP */ 5753#define DP_PLL_FREQ_270MHZ (0 << 16) 5754#define DP_PLL_FREQ_162MHZ (1 << 16) 5755#define DP_PLL_FREQ_MASK (3 << 16) 5756 5757/* locked once port is enabled */ 5758#define DP_PORT_REVERSAL (1 << 15) 5759 5760/* eDP */ 5761#define DP_PLL_ENABLE (1 << 14) 5762 5763/* sends the clock on lane 15 of the PEG for debug */ 5764#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 5765 5766#define DP_SCRAMBLING_DISABLE (1 << 12) 5767#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 5768 5769/* limit RGB values to avoid confusing TVs */ 5770#define DP_COLOR_RANGE_16_235 (1 << 8) 5771 5772/* Turn on the audio link */ 5773#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 5774 5775/* vs and hs sync polarity */ 5776#define DP_SYNC_VS_HIGH (1 << 4) 5777#define DP_SYNC_HS_HIGH (1 << 3) 5778 5779/* A fantasy */ 5780#define DP_DETECTED (1 << 2) 5781 5782/* The aux channel provides a way to talk to the 5783 * signal sink for DDC etc. Max packet size supported 5784 * is 20 bytes in each direction, hence the 5 fixed 5785 * data registers 5786 */ 5787#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 5788#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 5789 5790#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 5791#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 5792 5793#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 5794#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 5795 5796#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 5797#define DP_AUX_CH_CTL_DONE (1 << 30) 5798#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 5799#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 5800#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 5801#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 5802#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 5803#define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 5804#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 5805#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 5806#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 5807#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 5808#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 5809#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 5810#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 5811#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 5812#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 5813#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 5814#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 5815#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 5816#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 5817#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 5818#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 5819#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 5820#define DP_AUX_CH_CTL_TBT_IO (1 << 11) 5821#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 5822#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 5823#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 5824 5825/* 5826 * Computing GMCH M and N values for the Display Port link 5827 * 5828 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 5829 * 5830 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 5831 * 5832 * The GMCH value is used internally 5833 * 5834 * bytes_per_pixel is the number of bytes coming out of the plane, 5835 * which is after the LUTs, so we want the bytes for our color format. 5836 * For our current usage, this is always 3, one byte for R, G and B. 5837 */ 5838#define _PIPEA_DATA_M_G4X 0x70050 5839#define _PIPEB_DATA_M_G4X 0x71050 5840 5841/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 5842#define TU_SIZE(x) (((x) - 1) << 25) /* default size 64 */ 5843#define TU_SIZE_SHIFT 25 5844#define TU_SIZE_MASK (0x3f << 25) 5845 5846#define DATA_LINK_M_N_MASK (0xffffff) 5847#define DATA_LINK_N_MAX (0x800000) 5848 5849#define _PIPEA_DATA_N_G4X 0x70054 5850#define _PIPEB_DATA_N_G4X 0x71054 5851#define PIPE_GMCH_DATA_N_MASK (0xffffff) 5852 5853/* 5854 * Computing Link M and N values for the Display Port link 5855 * 5856 * Link M / N = pixel_clock / ls_clk 5857 * 5858 * (the DP spec calls pixel_clock the 'strm_clk') 5859 * 5860 * The Link value is transmitted in the Main Stream 5861 * Attributes and VB-ID. 5862 */ 5863 5864#define _PIPEA_LINK_M_G4X 0x70060 5865#define _PIPEB_LINK_M_G4X 0x71060 5866#define PIPEA_DP_LINK_M_MASK (0xffffff) 5867 5868#define _PIPEA_LINK_N_G4X 0x70064 5869#define _PIPEB_LINK_N_G4X 0x71064 5870#define PIPEA_DP_LINK_N_MASK (0xffffff) 5871 5872#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 5873#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 5874#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 5875#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 5876 5877/* Display & cursor control */ 5878 5879/* Pipe A */ 5880#define _PIPEADSL 0x70000 5881#define DSL_LINEMASK_GEN2 0x00000fff 5882#define DSL_LINEMASK_GEN3 0x00001fff 5883#define _PIPEACONF 0x70008 5884#define PIPECONF_ENABLE (1 << 31) 5885#define PIPECONF_DISABLE 0 5886#define PIPECONF_DOUBLE_WIDE (1 << 30) 5887#define I965_PIPECONF_ACTIVE (1 << 30) 5888#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */ 5889#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */ 5890#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */ 5891#define PIPECONF_SINGLE_WIDE 0 5892#define PIPECONF_PIPE_UNLOCKED 0 5893#define PIPECONF_PIPE_LOCKED (1 << 25) 5894#define PIPECONF_FORCE_BORDER (1 << 25) 5895#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */ 5896#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */ 5897#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */ 5898#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */ 5899#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */ 5900#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */ 5901#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */ 5902#define PIPECONF_GAMMA_MODE_SHIFT 24 5903#define PIPECONF_INTERLACE_MASK (7 << 21) 5904#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 5905/* Note that pre-gen3 does not support interlaced display directly. Panel 5906 * fitting must be disabled on pre-ilk for interlaced. */ 5907#define PIPECONF_PROGRESSIVE (0 << 21) 5908#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 5909#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 5910#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 5911#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 5912/* Ironlake and later have a complete new set of values for interlaced. PFIT 5913 * means panel fitter required, PF means progressive fetch, DBL means power 5914 * saving pixel doubling. */ 5915#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 5916#define PIPECONF_INTERLACED_ILK (3 << 21) 5917#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 5918#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 5919#define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 5920#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 5921#define PIPECONF_CXSR_DOWNCLOCK (1 << 16) 5922#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14) 5923#define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 5924#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */ 5925#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */ 5926#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */ 5927#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */ 5928#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */ 5929#define PIPECONF_BPC_MASK (0x7 << 5) 5930#define PIPECONF_8BPC (0 << 5) 5931#define PIPECONF_10BPC (1 << 5) 5932#define PIPECONF_6BPC (2 << 5) 5933#define PIPECONF_12BPC (3 << 5) 5934#define PIPECONF_DITHER_EN (1 << 4) 5935#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 5936#define PIPECONF_DITHER_TYPE_SP (0 << 2) 5937#define PIPECONF_DITHER_TYPE_ST1 (1 << 2) 5938#define PIPECONF_DITHER_TYPE_ST2 (2 << 2) 5939#define PIPECONF_DITHER_TYPE_TEMP (3 << 2) 5940#define _PIPEASTAT 0x70024 5941#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 5942#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 5943#define PIPE_CRC_ERROR_ENABLE (1UL << 29) 5944#define PIPE_CRC_DONE_ENABLE (1UL << 28) 5945#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 5946#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 5947#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 5948#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 5949#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 5950#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 5951#define PIPE_DPST_EVENT_ENABLE (1UL << 23) 5952#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 5953#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 5954#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 5955#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 5956#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 5957#define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 5958#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 5959#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 5960#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 5961#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 5962#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 5963#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 5964#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 5965#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 5966#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 5967#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 5968#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 5969#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 5970#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 5971#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 5972#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 5973#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 5974#define PIPE_DPST_EVENT_STATUS (1UL << 7) 5975#define PIPE_A_PSR_STATUS_VLV (1UL << 6) 5976#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 5977#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 5978#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 5979#define PIPE_B_PSR_STATUS_VLV (1UL << 3) 5980#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 5981#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 5982#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 5983#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 5984#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 5985#define PIPE_HBLANK_INT_STATUS (1UL << 0) 5986#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 5987 5988#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 5989#define PIPESTAT_INT_STATUS_MASK 0x0000ffff 5990 5991#define PIPE_A_OFFSET 0x70000 5992#define PIPE_B_OFFSET 0x71000 5993#define PIPE_C_OFFSET 0x72000 5994#define PIPE_D_OFFSET 0x73000 5995#define CHV_PIPE_C_OFFSET 0x74000 5996/* 5997 * There's actually no pipe EDP. Some pipe registers have 5998 * simply shifted from the pipe to the transcoder, while 5999 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 6000 * to access such registers in transcoder EDP. 6001 */ 6002#define PIPE_EDP_OFFSET 0x7f000 6003 6004/* ICL DSI 0 and 1 */ 6005#define PIPE_DSI0_OFFSET 0x7b000 6006#define PIPE_DSI1_OFFSET 0x7b800 6007 6008#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 6009#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 6010#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 6011#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 6012#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 6013 6014#define _PIPEAGCMAX 0x70010 6015#define _PIPEBGCMAX 0x71010 6016#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 6017 6018#define _PIPE_MISC_A 0x70030 6019#define _PIPE_MISC_B 0x71030 6020#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */ 6021#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */ 6022#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ 6023#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) 6024#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 6025#define PIPEMISC_DITHER_BPC_MASK (7 << 5) 6026#define PIPEMISC_DITHER_8_BPC (0 << 5) 6027#define PIPEMISC_DITHER_10_BPC (1 << 5) 6028#define PIPEMISC_DITHER_6_BPC (2 << 5) 6029#define PIPEMISC_DITHER_12_BPC (3 << 5) 6030#define PIPEMISC_DITHER_ENABLE (1 << 4) 6031#define PIPEMISC_DITHER_TYPE_MASK (3 << 2) 6032#define PIPEMISC_DITHER_TYPE_SP (0 << 2) 6033#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 6034 6035/* Skylake+ pipe bottom (background) color */ 6036#define _SKL_BOTTOM_COLOR_A 0x70034 6037#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31) 6038#define SKL_BOTTOM_COLOR_CSC_ENABLE (1 << 30) 6039#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 6040 6041#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 6042#define PIPEB_LINE_COMPARE_INT_EN (1 << 29) 6043#define PIPEB_HLINE_INT_EN (1 << 28) 6044#define PIPEB_VBLANK_INT_EN (1 << 27) 6045#define SPRITED_FLIP_DONE_INT_EN (1 << 26) 6046#define SPRITEC_FLIP_DONE_INT_EN (1 << 25) 6047#define PLANEB_FLIP_DONE_INT_EN (1 << 24) 6048#define PIPE_PSR_INT_EN (1 << 22) 6049#define PIPEA_LINE_COMPARE_INT_EN (1 << 21) 6050#define PIPEA_HLINE_INT_EN (1 << 20) 6051#define PIPEA_VBLANK_INT_EN (1 << 19) 6052#define SPRITEB_FLIP_DONE_INT_EN (1 << 18) 6053#define SPRITEA_FLIP_DONE_INT_EN (1 << 17) 6054#define PLANEA_FLIPDONE_INT_EN (1 << 16) 6055#define PIPEC_LINE_COMPARE_INT_EN (1 << 13) 6056#define PIPEC_HLINE_INT_EN (1 << 12) 6057#define PIPEC_VBLANK_INT_EN (1 << 11) 6058#define SPRITEF_FLIPDONE_INT_EN (1 << 10) 6059#define SPRITEE_FLIPDONE_INT_EN (1 << 9) 6060#define PLANEC_FLIPDONE_INT_EN (1 << 8) 6061 6062#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 6063#define SPRITEF_INVALID_GTT_INT_EN (1 << 27) 6064#define SPRITEE_INVALID_GTT_INT_EN (1 << 26) 6065#define PLANEC_INVALID_GTT_INT_EN (1 << 25) 6066#define CURSORC_INVALID_GTT_INT_EN (1 << 24) 6067#define CURSORB_INVALID_GTT_INT_EN (1 << 23) 6068#define CURSORA_INVALID_GTT_INT_EN (1 << 22) 6069#define SPRITED_INVALID_GTT_INT_EN (1 << 21) 6070#define SPRITEC_INVALID_GTT_INT_EN (1 << 20) 6071#define PLANEB_INVALID_GTT_INT_EN (1 << 19) 6072#define SPRITEB_INVALID_GTT_INT_EN (1 << 18) 6073#define SPRITEA_INVALID_GTT_INT_EN (1 << 17) 6074#define PLANEA_INVALID_GTT_INT_EN (1 << 16) 6075#define DPINVGTT_EN_MASK 0xff0000 6076#define DPINVGTT_EN_MASK_CHV 0xfff0000 6077#define SPRITEF_INVALID_GTT_STATUS (1 << 11) 6078#define SPRITEE_INVALID_GTT_STATUS (1 << 10) 6079#define PLANEC_INVALID_GTT_STATUS (1 << 9) 6080#define CURSORC_INVALID_GTT_STATUS (1 << 8) 6081#define CURSORB_INVALID_GTT_STATUS (1 << 7) 6082#define CURSORA_INVALID_GTT_STATUS (1 << 6) 6083#define SPRITED_INVALID_GTT_STATUS (1 << 5) 6084#define SPRITEC_INVALID_GTT_STATUS (1 << 4) 6085#define PLANEB_INVALID_GTT_STATUS (1 << 3) 6086#define SPRITEB_INVALID_GTT_STATUS (1 << 2) 6087#define SPRITEA_INVALID_GTT_STATUS (1 << 1) 6088#define PLANEA_INVALID_GTT_STATUS (1 << 0) 6089#define DPINVGTT_STATUS_MASK 0xff 6090#define DPINVGTT_STATUS_MASK_CHV 0xfff 6091 6092#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 6093#define DSPARB_CSTART_MASK (0x7f << 7) 6094#define DSPARB_CSTART_SHIFT 7 6095#define DSPARB_BSTART_MASK (0x7f) 6096#define DSPARB_BSTART_SHIFT 0 6097#define DSPARB_BEND_SHIFT 9 /* on 855 */ 6098#define DSPARB_AEND_SHIFT 0 6099#define DSPARB_SPRITEA_SHIFT_VLV 0 6100#define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 6101#define DSPARB_SPRITEB_SHIFT_VLV 8 6102#define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 6103#define DSPARB_SPRITEC_SHIFT_VLV 16 6104#define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 6105#define DSPARB_SPRITED_SHIFT_VLV 24 6106#define DSPARB_SPRITED_MASK_VLV (0xff << 24) 6107#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 6108#define DSPARB_SPRITEA_HI_SHIFT_VLV 0 6109#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 6110#define DSPARB_SPRITEB_HI_SHIFT_VLV 4 6111#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 6112#define DSPARB_SPRITEC_HI_SHIFT_VLV 8 6113#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 6114#define DSPARB_SPRITED_HI_SHIFT_VLV 12 6115#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 6116#define DSPARB_SPRITEE_HI_SHIFT_VLV 16 6117#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 6118#define DSPARB_SPRITEF_HI_SHIFT_VLV 20 6119#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 6120#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 6121#define DSPARB_SPRITEE_SHIFT_VLV 0 6122#define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 6123#define DSPARB_SPRITEF_SHIFT_VLV 8 6124#define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 6125 6126/* pnv/gen4/g4x/vlv/chv */ 6127#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 6128#define DSPFW_SR_SHIFT 23 6129#define DSPFW_SR_MASK (0x1ff << 23) 6130#define DSPFW_CURSORB_SHIFT 16 6131#define DSPFW_CURSORB_MASK (0x3f << 16) 6132#define DSPFW_PLANEB_SHIFT 8 6133#define DSPFW_PLANEB_MASK (0x7f << 8) 6134#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 6135#define DSPFW_PLANEA_SHIFT 0 6136#define DSPFW_PLANEA_MASK (0x7f << 0) 6137#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 6138#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 6139#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 6140#define DSPFW_FBC_SR_SHIFT 28 6141#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 6142#define DSPFW_FBC_HPLL_SR_SHIFT 24 6143#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 6144#define DSPFW_SPRITEB_SHIFT (16) 6145#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 6146#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 6147#define DSPFW_CURSORA_SHIFT 8 6148#define DSPFW_CURSORA_MASK (0x3f << 8) 6149#define DSPFW_PLANEC_OLD_SHIFT 0 6150#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 6151#define DSPFW_SPRITEA_SHIFT 0 6152#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 6153#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 6154#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 6155#define DSPFW_HPLL_SR_EN (1 << 31) 6156#define PINEVIEW_SELF_REFRESH_EN (1 << 30) 6157#define DSPFW_CURSOR_SR_SHIFT 24 6158#define DSPFW_CURSOR_SR_MASK (0x3f << 24) 6159#define DSPFW_HPLL_CURSOR_SHIFT 16 6160#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 6161#define DSPFW_HPLL_SR_SHIFT 0 6162#define DSPFW_HPLL_SR_MASK (0x1ff << 0) 6163 6164/* vlv/chv */ 6165#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 6166#define DSPFW_SPRITEB_WM1_SHIFT 16 6167#define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 6168#define DSPFW_CURSORA_WM1_SHIFT 8 6169#define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 6170#define DSPFW_SPRITEA_WM1_SHIFT 0 6171#define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 6172#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 6173#define DSPFW_PLANEB_WM1_SHIFT 24 6174#define DSPFW_PLANEB_WM1_MASK (0xff << 24) 6175#define DSPFW_PLANEA_WM1_SHIFT 16 6176#define DSPFW_PLANEA_WM1_MASK (0xff << 16) 6177#define DSPFW_CURSORB_WM1_SHIFT 8 6178#define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 6179#define DSPFW_CURSOR_SR_WM1_SHIFT 0 6180#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 6181#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 6182#define DSPFW_SR_WM1_SHIFT 0 6183#define DSPFW_SR_WM1_MASK (0x1ff << 0) 6184#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 6185#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 6186#define DSPFW_SPRITED_WM1_SHIFT 24 6187#define DSPFW_SPRITED_WM1_MASK (0xff << 24) 6188#define DSPFW_SPRITED_SHIFT 16 6189#define DSPFW_SPRITED_MASK_VLV (0xff << 16) 6190#define DSPFW_SPRITEC_WM1_SHIFT 8 6191#define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 6192#define DSPFW_SPRITEC_SHIFT 0 6193#define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 6194#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 6195#define DSPFW_SPRITEF_WM1_SHIFT 24 6196#define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 6197#define DSPFW_SPRITEF_SHIFT 16 6198#define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 6199#define DSPFW_SPRITEE_WM1_SHIFT 8 6200#define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 6201#define DSPFW_SPRITEE_SHIFT 0 6202#define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 6203#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 6204#define DSPFW_PLANEC_WM1_SHIFT 24 6205#define DSPFW_PLANEC_WM1_MASK (0xff << 24) 6206#define DSPFW_PLANEC_SHIFT 16 6207#define DSPFW_PLANEC_MASK_VLV (0xff << 16) 6208#define DSPFW_CURSORC_WM1_SHIFT 8 6209#define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 6210#define DSPFW_CURSORC_SHIFT 0 6211#define DSPFW_CURSORC_MASK (0x3f << 0) 6212 6213/* vlv/chv high order bits */ 6214#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 6215#define DSPFW_SR_HI_SHIFT 24 6216#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 6217#define DSPFW_SPRITEF_HI_SHIFT 23 6218#define DSPFW_SPRITEF_HI_MASK (1 << 23) 6219#define DSPFW_SPRITEE_HI_SHIFT 22 6220#define DSPFW_SPRITEE_HI_MASK (1 << 22) 6221#define DSPFW_PLANEC_HI_SHIFT 21 6222#define DSPFW_PLANEC_HI_MASK (1 << 21) 6223#define DSPFW_SPRITED_HI_SHIFT 20 6224#define DSPFW_SPRITED_HI_MASK (1 << 20) 6225#define DSPFW_SPRITEC_HI_SHIFT 16 6226#define DSPFW_SPRITEC_HI_MASK (1 << 16) 6227#define DSPFW_PLANEB_HI_SHIFT 12 6228#define DSPFW_PLANEB_HI_MASK (1 << 12) 6229#define DSPFW_SPRITEB_HI_SHIFT 8 6230#define DSPFW_SPRITEB_HI_MASK (1 << 8) 6231#define DSPFW_SPRITEA_HI_SHIFT 4 6232#define DSPFW_SPRITEA_HI_MASK (1 << 4) 6233#define DSPFW_PLANEA_HI_SHIFT 0 6234#define DSPFW_PLANEA_HI_MASK (1 << 0) 6235#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 6236#define DSPFW_SR_WM1_HI_SHIFT 24 6237#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 6238#define DSPFW_SPRITEF_WM1_HI_SHIFT 23 6239#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 6240#define DSPFW_SPRITEE_WM1_HI_SHIFT 22 6241#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 6242#define DSPFW_PLANEC_WM1_HI_SHIFT 21 6243#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 6244#define DSPFW_SPRITED_WM1_HI_SHIFT 20 6245#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 6246#define DSPFW_SPRITEC_WM1_HI_SHIFT 16 6247#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 6248#define DSPFW_PLANEB_WM1_HI_SHIFT 12 6249#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 6250#define DSPFW_SPRITEB_WM1_HI_SHIFT 8 6251#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 6252#define DSPFW_SPRITEA_WM1_HI_SHIFT 4 6253#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 6254#define DSPFW_PLANEA_WM1_HI_SHIFT 0 6255#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 6256 6257/* drain latency register values*/ 6258#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 6259#define DDL_CURSOR_SHIFT 24 6260#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 6261#define DDL_PLANE_SHIFT 0 6262#define DDL_PRECISION_HIGH (1 << 7) 6263#define DDL_PRECISION_LOW (0 << 7) 6264#define DRAIN_LATENCY_MASK 0x7f 6265 6266#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 6267#define CBR_PND_DEADLINE_DISABLE (1 << 31) 6268#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 6269 6270#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 6271#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 6272 6273/* FIFO watermark sizes etc */ 6274#define G4X_FIFO_LINE_SIZE 64 6275#define I915_FIFO_LINE_SIZE 64 6276#define I830_FIFO_LINE_SIZE 32 6277 6278#define VALLEYVIEW_FIFO_SIZE 255 6279#define G4X_FIFO_SIZE 127 6280#define I965_FIFO_SIZE 512 6281#define I945_FIFO_SIZE 127 6282#define I915_FIFO_SIZE 95 6283#define I855GM_FIFO_SIZE 127 /* In cachelines */ 6284#define I830_FIFO_SIZE 95 6285 6286#define VALLEYVIEW_MAX_WM 0xff 6287#define G4X_MAX_WM 0x3f 6288#define I915_MAX_WM 0x3f 6289 6290#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 6291#define PINEVIEW_FIFO_LINE_SIZE 64 6292#define PINEVIEW_MAX_WM 0x1ff 6293#define PINEVIEW_DFT_WM 0x3f 6294#define PINEVIEW_DFT_HPLLOFF_WM 0 6295#define PINEVIEW_GUARD_WM 10 6296#define PINEVIEW_CURSOR_FIFO 64 6297#define PINEVIEW_CURSOR_MAX_WM 0x3f 6298#define PINEVIEW_CURSOR_DFT_WM 0 6299#define PINEVIEW_CURSOR_GUARD_WM 5 6300 6301#define VALLEYVIEW_CURSOR_MAX_WM 64 6302#define I965_CURSOR_FIFO 64 6303#define I965_CURSOR_MAX_WM 32 6304#define I965_CURSOR_DFT_WM 8 6305 6306/* Watermark register definitions for SKL */ 6307#define _CUR_WM_A_0 0x70140 6308#define _CUR_WM_B_0 0x71140 6309#define _PLANE_WM_1_A_0 0x70240 6310#define _PLANE_WM_1_B_0 0x71240 6311#define _PLANE_WM_2_A_0 0x70340 6312#define _PLANE_WM_2_B_0 0x71340 6313#define _PLANE_WM_TRANS_1_A_0 0x70268 6314#define _PLANE_WM_TRANS_1_B_0 0x71268 6315#define _PLANE_WM_TRANS_2_A_0 0x70368 6316#define _PLANE_WM_TRANS_2_B_0 0x71368 6317#define _CUR_WM_TRANS_A_0 0x70168 6318#define _CUR_WM_TRANS_B_0 0x71168 6319#define PLANE_WM_EN (1 << 31) 6320#define PLANE_WM_IGNORE_LINES (1 << 30) 6321#define PLANE_WM_LINES_SHIFT 14 6322#define PLANE_WM_LINES_MASK 0x1f 6323#define PLANE_WM_BLOCKS_MASK 0x7ff /* skl+: 10 bits, icl+ 11 bits */ 6324 6325#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 6326#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 6327#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0) 6328 6329#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 6330#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 6331#define _PLANE_WM_BASE(pipe, plane) \ 6332 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 6333#define PLANE_WM(pipe, plane, level) \ 6334 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 6335#define _PLANE_WM_TRANS_1(pipe) \ 6336 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0) 6337#define _PLANE_WM_TRANS_2(pipe) \ 6338 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0) 6339#define PLANE_WM_TRANS(pipe, plane) \ 6340 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 6341 6342/* define the Watermark register on Ironlake */ 6343#define WM0_PIPEA_ILK _MMIO(0x45100) 6344#define WM0_PIPE_PLANE_MASK (0xffff << 16) 6345#define WM0_PIPE_PLANE_SHIFT 16 6346#define WM0_PIPE_SPRITE_MASK (0xff << 8) 6347#define WM0_PIPE_SPRITE_SHIFT 8 6348#define WM0_PIPE_CURSOR_MASK (0xff) 6349 6350#define WM0_PIPEB_ILK _MMIO(0x45104) 6351#define WM0_PIPEC_IVB _MMIO(0x45200) 6352#define WM1_LP_ILK _MMIO(0x45108) 6353#define WM1_LP_SR_EN (1 << 31) 6354#define WM1_LP_LATENCY_SHIFT 24 6355#define WM1_LP_LATENCY_MASK (0x7f << 24) 6356#define WM1_LP_FBC_MASK (0xf << 20) 6357#define WM1_LP_FBC_SHIFT 20 6358#define WM1_LP_FBC_SHIFT_BDW 19 6359#define WM1_LP_SR_MASK (0x7ff << 8) 6360#define WM1_LP_SR_SHIFT 8 6361#define WM1_LP_CURSOR_MASK (0xff) 6362#define WM2_LP_ILK _MMIO(0x4510c) 6363#define WM2_LP_EN (1 << 31) 6364#define WM3_LP_ILK _MMIO(0x45110) 6365#define WM3_LP_EN (1 << 31) 6366#define WM1S_LP_ILK _MMIO(0x45120) 6367#define WM2S_LP_IVB _MMIO(0x45124) 6368#define WM3S_LP_IVB _MMIO(0x45128) 6369#define WM1S_LP_EN (1 << 31) 6370 6371#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 6372 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 6373 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 6374 6375/* Memory latency timer register */ 6376#define MLTR_ILK _MMIO(0x11222) 6377#define MLTR_WM1_SHIFT 0 6378#define MLTR_WM2_SHIFT 8 6379/* the unit of memory self-refresh latency time is 0.5us */ 6380#define ILK_SRLT_MASK 0x3f 6381 6382 6383/* the address where we get all kinds of latency value */ 6384#define SSKPD _MMIO(0x5d10) 6385#define SSKPD_WM_MASK 0x3f 6386#define SSKPD_WM0_SHIFT 0 6387#define SSKPD_WM1_SHIFT 8 6388#define SSKPD_WM2_SHIFT 16 6389#define SSKPD_WM3_SHIFT 24 6390 6391/* 6392 * The two pipe frame counter registers are not synchronized, so 6393 * reading a stable value is somewhat tricky. The following code 6394 * should work: 6395 * 6396 * do { 6397 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6398 * PIPE_FRAME_HIGH_SHIFT; 6399 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 6400 * PIPE_FRAME_LOW_SHIFT); 6401 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 6402 * PIPE_FRAME_HIGH_SHIFT); 6403 * } while (high1 != high2); 6404 * frame = (high1 << 8) | low1; 6405 */ 6406#define _PIPEAFRAMEHIGH 0x70040 6407#define PIPE_FRAME_HIGH_MASK 0x0000ffff 6408#define PIPE_FRAME_HIGH_SHIFT 0 6409#define _PIPEAFRAMEPIXEL 0x70044 6410#define PIPE_FRAME_LOW_MASK 0xff000000 6411#define PIPE_FRAME_LOW_SHIFT 24 6412#define PIPE_PIXEL_MASK 0x00ffffff 6413#define PIPE_PIXEL_SHIFT 0 6414/* GM45+ just has to be different */ 6415#define _PIPEA_FRMCOUNT_G4X 0x70040 6416#define _PIPEA_FLIPCOUNT_G4X 0x70044 6417#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 6418#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 6419 6420/* Cursor A & B regs */ 6421#define _CURACNTR 0x70080 6422/* Old style CUR*CNTR flags (desktop 8xx) */ 6423#define CURSOR_ENABLE 0x80000000 6424#define CURSOR_GAMMA_ENABLE 0x40000000 6425#define CURSOR_STRIDE_SHIFT 28 6426#define CURSOR_STRIDE(x) ((ffs(x) - 9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 6427#define CURSOR_FORMAT_SHIFT 24 6428#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 6429#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 6430#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 6431#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 6432#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 6433#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 6434/* New style CUR*CNTR flags */ 6435#define MCURSOR_MODE 0x27 6436#define MCURSOR_MODE_DISABLE 0x00 6437#define MCURSOR_MODE_128_32B_AX 0x02 6438#define MCURSOR_MODE_256_32B_AX 0x03 6439#define MCURSOR_MODE_64_32B_AX 0x07 6440#define MCURSOR_MODE_128_ARGB_AX ((1 << 5) | MCURSOR_MODE_128_32B_AX) 6441#define MCURSOR_MODE_256_ARGB_AX ((1 << 5) | MCURSOR_MODE_256_32B_AX) 6442#define MCURSOR_MODE_64_ARGB_AX ((1 << 5) | MCURSOR_MODE_64_32B_AX) 6443#define MCURSOR_PIPE_SELECT_MASK (0x3 << 28) 6444#define MCURSOR_PIPE_SELECT_SHIFT 28 6445#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28) 6446#define MCURSOR_GAMMA_ENABLE (1 << 26) 6447#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6448#define MCURSOR_ROTATE_180 (1 << 15) 6449#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14) 6450#define _CURABASE 0x70084 6451#define _CURAPOS 0x70088 6452#define CURSOR_POS_MASK 0x007FF 6453#define CURSOR_POS_SIGN 0x8000 6454#define CURSOR_X_SHIFT 0 6455#define CURSOR_Y_SHIFT 16 6456#define CURSIZE _MMIO(0x700a0) /* 845/865 */ 6457#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 6458#define CUR_FBC_CTL_EN (1 << 31) 6459#define _CURASURFLIVE 0x700ac /* g4x+ */ 6460#define _CURBCNTR 0x700c0 6461#define _CURBBASE 0x700c4 6462#define _CURBPOS 0x700c8 6463 6464#define _CURBCNTR_IVB 0x71080 6465#define _CURBBASE_IVB 0x71084 6466#define _CURBPOS_IVB 0x71088 6467 6468#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 6469#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 6470#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 6471#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 6472#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 6473 6474#define CURSOR_A_OFFSET 0x70080 6475#define CURSOR_B_OFFSET 0x700c0 6476#define CHV_CURSOR_C_OFFSET 0x700e0 6477#define IVB_CURSOR_B_OFFSET 0x71080 6478#define IVB_CURSOR_C_OFFSET 0x72080 6479#define TGL_CURSOR_D_OFFSET 0x73080 6480 6481/* Display A control */ 6482#define _DSPACNTR 0x70180 6483#define DISPLAY_PLANE_ENABLE (1 << 31) 6484#define DISPLAY_PLANE_DISABLE 0 6485#define DISPPLANE_GAMMA_ENABLE (1 << 30) 6486#define DISPPLANE_GAMMA_DISABLE 0 6487#define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 6488#define DISPPLANE_YUV422 (0x0 << 26) 6489#define DISPPLANE_8BPP (0x2 << 26) 6490#define DISPPLANE_BGRA555 (0x3 << 26) 6491#define DISPPLANE_BGRX555 (0x4 << 26) 6492#define DISPPLANE_BGRX565 (0x5 << 26) 6493#define DISPPLANE_BGRX888 (0x6 << 26) 6494#define DISPPLANE_BGRA888 (0x7 << 26) 6495#define DISPPLANE_RGBX101010 (0x8 << 26) 6496#define DISPPLANE_RGBA101010 (0x9 << 26) 6497#define DISPPLANE_BGRX101010 (0xa << 26) 6498#define DISPPLANE_BGRA101010 (0xb << 26) 6499#define DISPPLANE_RGBX161616 (0xc << 26) 6500#define DISPPLANE_RGBX888 (0xe << 26) 6501#define DISPPLANE_RGBA888 (0xf << 26) 6502#define DISPPLANE_STEREO_ENABLE (1 << 25) 6503#define DISPPLANE_STEREO_DISABLE 0 6504#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */ 6505#define DISPPLANE_SEL_PIPE_SHIFT 24 6506#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT) 6507#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT) 6508#define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 6509#define DISPPLANE_SRC_KEY_DISABLE 0 6510#define DISPPLANE_LINE_DOUBLE (1 << 20) 6511#define DISPPLANE_NO_LINE_DOUBLE 0 6512#define DISPPLANE_STEREO_POLARITY_FIRST 0 6513#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 6514#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */ 6515#define DISPPLANE_ROTATE_180 (1 << 15) 6516#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */ 6517#define DISPPLANE_TILED (1 << 10) 6518#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */ 6519#define _DSPAADDR 0x70184 6520#define _DSPASTRIDE 0x70188 6521#define _DSPAPOS 0x7018C /* reserved */ 6522#define _DSPASIZE 0x70190 6523#define _DSPASURF 0x7019C /* 965+ only */ 6524#define _DSPATILEOFF 0x701A4 /* 965+ only */ 6525#define _DSPAOFFSET 0x701A4 /* HSW */ 6526#define _DSPASURFLIVE 0x701AC 6527#define _DSPAGAMC 0x701E0 6528 6529#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 6530#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 6531#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 6532#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 6533#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 6534#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 6535#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 6536#define DSPLINOFF(plane) DSPADDR(plane) 6537#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 6538#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 6539#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 6540 6541/* CHV pipe B blender and primary plane */ 6542#define _CHV_BLEND_A 0x60a00 6543#define CHV_BLEND_LEGACY (0 << 30) 6544#define CHV_BLEND_ANDROID (1 << 30) 6545#define CHV_BLEND_MPO (2 << 30) 6546#define CHV_BLEND_MASK (3 << 30) 6547#define _CHV_CANVAS_A 0x60a04 6548#define _PRIMPOS_A 0x60a08 6549#define _PRIMSIZE_A 0x60a0c 6550#define _PRIMCNSTALPHA_A 0x60a10 6551#define PRIM_CONST_ALPHA_ENABLE (1 << 31) 6552 6553#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 6554#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 6555#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 6556#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 6557#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 6558 6559/* Display/Sprite base address macros */ 6560#define DISP_BASEADDR_MASK (0xfffff000) 6561#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 6562#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 6563 6564/* 6565 * VBIOS flags 6566 * gen2: 6567 * [00:06] alm,mgm 6568 * [10:16] all 6569 * [30:32] alm,mgm 6570 * gen3+: 6571 * [00:0f] all 6572 * [10:1f] all 6573 * [30:32] all 6574 */ 6575#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 6576#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 6577#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 6578#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 6579 6580/* Pipe B */ 6581#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 6582#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 6583#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 6584#define _PIPEBFRAMEHIGH 0x71040 6585#define _PIPEBFRAMEPIXEL 0x71044 6586#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 6587#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 6588 6589 6590/* Display B control */ 6591#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 6592#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 6593#define DISPPLANE_ALPHA_TRANS_DISABLE 0 6594#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 6595#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 6596#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 6597#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 6598#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 6599#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 6600#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 6601#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6602#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 6603#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 6604 6605/* ICL DSI 0 and 1 */ 6606#define _PIPEDSI0CONF 0x7b008 6607#define _PIPEDSI1CONF 0x7b808 6608 6609/* Sprite A control */ 6610#define _DVSACNTR 0x72180 6611#define DVS_ENABLE (1 << 31) 6612#define DVS_GAMMA_ENABLE (1 << 30) 6613#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27) 6614#define DVS_PIXFORMAT_MASK (3 << 25) 6615#define DVS_FORMAT_YUV422 (0 << 25) 6616#define DVS_FORMAT_RGBX101010 (1 << 25) 6617#define DVS_FORMAT_RGBX888 (2 << 25) 6618#define DVS_FORMAT_RGBX161616 (3 << 25) 6619#define DVS_PIPE_CSC_ENABLE (1 << 24) 6620#define DVS_SOURCE_KEY (1 << 22) 6621#define DVS_RGB_ORDER_XBGR (1 << 20) 6622#define DVS_YUV_FORMAT_BT709 (1 << 18) 6623#define DVS_YUV_BYTE_ORDER_MASK (3 << 16) 6624#define DVS_YUV_ORDER_YUYV (0 << 16) 6625#define DVS_YUV_ORDER_UYVY (1 << 16) 6626#define DVS_YUV_ORDER_YVYU (2 << 16) 6627#define DVS_YUV_ORDER_VYUY (3 << 16) 6628#define DVS_ROTATE_180 (1 << 15) 6629#define DVS_DEST_KEY (1 << 2) 6630#define DVS_TRICKLE_FEED_DISABLE (1 << 14) 6631#define DVS_TILED (1 << 10) 6632#define _DVSALINOFF 0x72184 6633#define _DVSASTRIDE 0x72188 6634#define _DVSAPOS 0x7218c 6635#define _DVSASIZE 0x72190 6636#define _DVSAKEYVAL 0x72194 6637#define _DVSAKEYMSK 0x72198 6638#define _DVSASURF 0x7219c 6639#define _DVSAKEYMAXVAL 0x721a0 6640#define _DVSATILEOFF 0x721a4 6641#define _DVSASURFLIVE 0x721ac 6642#define _DVSAGAMC_G4X 0x721e0 /* g4x */ 6643#define _DVSASCALE 0x72204 6644#define DVS_SCALE_ENABLE (1 << 31) 6645#define DVS_FILTER_MASK (3 << 29) 6646#define DVS_FILTER_MEDIUM (0 << 29) 6647#define DVS_FILTER_ENHANCING (1 << 29) 6648#define DVS_FILTER_SOFTENING (2 << 29) 6649#define DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6650#define DVS_VERTICAL_OFFSET_ENABLE (1 << 27) 6651#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 6652#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 6653 6654#define _DVSBCNTR 0x73180 6655#define _DVSBLINOFF 0x73184 6656#define _DVSBSTRIDE 0x73188 6657#define _DVSBPOS 0x7318c 6658#define _DVSBSIZE 0x73190 6659#define _DVSBKEYVAL 0x73194 6660#define _DVSBKEYMSK 0x73198 6661#define _DVSBSURF 0x7319c 6662#define _DVSBKEYMAXVAL 0x731a0 6663#define _DVSBTILEOFF 0x731a4 6664#define _DVSBSURFLIVE 0x731ac 6665#define _DVSBGAMC_G4X 0x731e0 /* g4x */ 6666#define _DVSBSCALE 0x73204 6667#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 6668#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 6669 6670#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 6671#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 6672#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 6673#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 6674#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 6675#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 6676#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 6677#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 6678#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 6679#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 6680#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 6681#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 6682#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 6683#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 6684#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 6685 6686#define _SPRA_CTL 0x70280 6687#define SPRITE_ENABLE (1 << 31) 6688#define SPRITE_GAMMA_ENABLE (1 << 30) 6689#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6690#define SPRITE_PIXFORMAT_MASK (7 << 25) 6691#define SPRITE_FORMAT_YUV422 (0 << 25) 6692#define SPRITE_FORMAT_RGBX101010 (1 << 25) 6693#define SPRITE_FORMAT_RGBX888 (2 << 25) 6694#define SPRITE_FORMAT_RGBX161616 (3 << 25) 6695#define SPRITE_FORMAT_YUV444 (4 << 25) 6696#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */ 6697#define SPRITE_PIPE_CSC_ENABLE (1 << 24) 6698#define SPRITE_SOURCE_KEY (1 << 22) 6699#define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and 161616 */ 6700#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19) 6701#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */ 6702#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16) 6703#define SPRITE_YUV_ORDER_YUYV (0 << 16) 6704#define SPRITE_YUV_ORDER_UYVY (1 << 16) 6705#define SPRITE_YUV_ORDER_YVYU (2 << 16) 6706#define SPRITE_YUV_ORDER_VYUY (3 << 16) 6707#define SPRITE_ROTATE_180 (1 << 15) 6708#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14) 6709#define SPRITE_INT_GAMMA_DISABLE (1 << 13) 6710#define SPRITE_TILED (1 << 10) 6711#define SPRITE_DEST_KEY (1 << 2) 6712#define _SPRA_LINOFF 0x70284 6713#define _SPRA_STRIDE 0x70288 6714#define _SPRA_POS 0x7028c 6715#define _SPRA_SIZE 0x70290 6716#define _SPRA_KEYVAL 0x70294 6717#define _SPRA_KEYMSK 0x70298 6718#define _SPRA_SURF 0x7029c 6719#define _SPRA_KEYMAX 0x702a0 6720#define _SPRA_TILEOFF 0x702a4 6721#define _SPRA_OFFSET 0x702a4 6722#define _SPRA_SURFLIVE 0x702ac 6723#define _SPRA_SCALE 0x70304 6724#define SPRITE_SCALE_ENABLE (1 << 31) 6725#define SPRITE_FILTER_MASK (3 << 29) 6726#define SPRITE_FILTER_MEDIUM (0 << 29) 6727#define SPRITE_FILTER_ENHANCING (1 << 29) 6728#define SPRITE_FILTER_SOFTENING (2 << 29) 6729#define SPRITE_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */ 6730#define SPRITE_VERTICAL_OFFSET_ENABLE (1 << 27) 6731#define _SPRA_GAMC 0x70400 6732#define _SPRA_GAMC16 0x70440 6733#define _SPRA_GAMC17 0x7044c 6734 6735#define _SPRB_CTL 0x71280 6736#define _SPRB_LINOFF 0x71284 6737#define _SPRB_STRIDE 0x71288 6738#define _SPRB_POS 0x7128c 6739#define _SPRB_SIZE 0x71290 6740#define _SPRB_KEYVAL 0x71294 6741#define _SPRB_KEYMSK 0x71298 6742#define _SPRB_SURF 0x7129c 6743#define _SPRB_KEYMAX 0x712a0 6744#define _SPRB_TILEOFF 0x712a4 6745#define _SPRB_OFFSET 0x712a4 6746#define _SPRB_SURFLIVE 0x712ac 6747#define _SPRB_SCALE 0x71304 6748#define _SPRB_GAMC 0x71400 6749#define _SPRB_GAMC16 0x71440 6750#define _SPRB_GAMC17 0x7144c 6751 6752#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 6753#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 6754#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 6755#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 6756#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 6757#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 6758#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 6759#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 6760#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 6761#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 6762#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 6763#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 6764#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 6765#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 6766#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 6767#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 6768 6769#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 6770#define SP_ENABLE (1 << 31) 6771#define SP_GAMMA_ENABLE (1 << 30) 6772#define SP_PIXFORMAT_MASK (0xf << 26) 6773#define SP_FORMAT_YUV422 (0x0 << 26) 6774#define SP_FORMAT_8BPP (0x2 << 26) 6775#define SP_FORMAT_BGR565 (0x5 << 26) 6776#define SP_FORMAT_BGRX8888 (0x6 << 26) 6777#define SP_FORMAT_BGRA8888 (0x7 << 26) 6778#define SP_FORMAT_RGBX1010102 (0x8 << 26) 6779#define SP_FORMAT_RGBA1010102 (0x9 << 26) 6780#define SP_FORMAT_BGRX1010102 (0xa << 26) /* CHV pipe B */ 6781#define SP_FORMAT_BGRA1010102 (0xb << 26) /* CHV pipe B */ 6782#define SP_FORMAT_RGBX8888 (0xe << 26) 6783#define SP_FORMAT_RGBA8888 (0xf << 26) 6784#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */ 6785#define SP_SOURCE_KEY (1 << 22) 6786#define SP_YUV_FORMAT_BT709 (1 << 18) 6787#define SP_YUV_BYTE_ORDER_MASK (3 << 16) 6788#define SP_YUV_ORDER_YUYV (0 << 16) 6789#define SP_YUV_ORDER_UYVY (1 << 16) 6790#define SP_YUV_ORDER_YVYU (2 << 16) 6791#define SP_YUV_ORDER_VYUY (3 << 16) 6792#define SP_ROTATE_180 (1 << 15) 6793#define SP_TILED (1 << 10) 6794#define SP_MIRROR (1 << 8) /* CHV pipe B */ 6795#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 6796#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 6797#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 6798#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 6799#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 6800#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 6801#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 6802#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 6803#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 6804#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 6805#define SP_CONST_ALPHA_ENABLE (1 << 31) 6806#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 6807#define SP_CONTRAST(x) ((x) << 18) /* u3.6 */ 6808#define SP_BRIGHTNESS(x) ((x) & 0xff) /* s8 */ 6809#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 6810#define SP_SH_SIN(x) (((x) & 0x7ff) << 16) /* s4.7 */ 6811#define SP_SH_COS(x) (x) /* u3.7 */ 6812#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 6813 6814#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 6815#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 6816#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 6817#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 6818#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 6819#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 6820#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 6821#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 6822#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 6823#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 6824#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 6825#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 6826#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 6827#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 6828 6829#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6830 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 6831#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 6832 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 6833 6834#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 6835#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 6836#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 6837#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 6838#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 6839#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 6840#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 6841#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 6842#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 6843#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 6844#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 6845#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 6846#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 6847#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 6848 6849/* 6850 * CHV pipe B sprite CSC 6851 * 6852 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 6853 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 6854 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 6855 */ 6856#define _MMIO_CHV_SPCSC(plane_id, reg) \ 6857 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 6858 6859#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 6860#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 6861#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 6862#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */ 6863#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */ 6864 6865#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 6866#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 6867#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 6868#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 6869#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 6870#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */ 6871#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */ 6872 6873#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 6874#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 6875#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 6876#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */ 6877#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */ 6878 6879#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 6880#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 6881#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 6882#define SPCSC_OMAX(x) ((x) << 16) /* u10 */ 6883#define SPCSC_OMIN(x) ((x) << 0) /* u10 */ 6884 6885/* Skylake plane registers */ 6886 6887#define _PLANE_CTL_1_A 0x70180 6888#define _PLANE_CTL_2_A 0x70280 6889#define _PLANE_CTL_3_A 0x70380 6890#define PLANE_CTL_ENABLE (1 << 31) 6891#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-GLK */ 6892#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6893/* 6894 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 6895 * expanded to include bit 23 as well. However, the shift-24 based values 6896 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 6897 */ 6898#define PLANE_CTL_FORMAT_MASK (0xf << 24) 6899#define PLANE_CTL_FORMAT_YUV422 (0 << 24) 6900#define PLANE_CTL_FORMAT_NV12 (1 << 24) 6901#define PLANE_CTL_FORMAT_XRGB_2101010 (2 << 24) 6902#define PLANE_CTL_FORMAT_P010 (3 << 24) 6903#define PLANE_CTL_FORMAT_XRGB_8888 (4 << 24) 6904#define PLANE_CTL_FORMAT_P012 (5 << 24) 6905#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24) 6906#define PLANE_CTL_FORMAT_P016 (7 << 24) 6907#define PLANE_CTL_FORMAT_XYUV (8 << 24) 6908#define PLANE_CTL_FORMAT_INDEXED (12 << 24) 6909#define PLANE_CTL_FORMAT_RGB_565 (14 << 24) 6910#define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) 6911#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ 6912#define PLANE_CTL_FORMAT_Y210 (1 << 23) 6913#define PLANE_CTL_FORMAT_Y212 (3 << 23) 6914#define PLANE_CTL_FORMAT_Y216 (5 << 23) 6915#define PLANE_CTL_FORMAT_Y410 (7 << 23) 6916#define PLANE_CTL_FORMAT_Y412 (9 << 23) 6917#define PLANE_CTL_FORMAT_Y416 (0xb << 23) 6918#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) 6919#define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) 6920#define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21) 6921#define PLANE_CTL_ORDER_BGRX (0 << 20) 6922#define PLANE_CTL_ORDER_RGBX (1 << 20) 6923#define PLANE_CTL_YUV420_Y_PLANE (1 << 19) 6924#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) 6925#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) 6926#define PLANE_CTL_YUV422_YUYV (0 << 16) 6927#define PLANE_CTL_YUV422_UYVY (1 << 16) 6928#define PLANE_CTL_YUV422_YVYU (2 << 16) 6929#define PLANE_CTL_YUV422_VYUY (3 << 16) 6930#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15) 6931#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14) 6932#define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */ 6933#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13) /* Pre-GLK */ 6934#define PLANE_CTL_TILED_MASK (0x7 << 10) 6935#define PLANE_CTL_TILED_LINEAR (0 << 10) 6936#define PLANE_CTL_TILED_X (1 << 10) 6937#define PLANE_CTL_TILED_Y (4 << 10) 6938#define PLANE_CTL_TILED_YF (5 << 10) 6939#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) 6940#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ 6941#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ 6942#define PLANE_CTL_ALPHA_DISABLE (0 << 4) 6943#define PLANE_CTL_ALPHA_SW_PREMULTIPLY (2 << 4) 6944#define PLANE_CTL_ALPHA_HW_PREMULTIPLY (3 << 4) 6945#define PLANE_CTL_ROTATE_MASK 0x3 6946#define PLANE_CTL_ROTATE_0 0x0 6947#define PLANE_CTL_ROTATE_90 0x1 6948#define PLANE_CTL_ROTATE_180 0x2 6949#define PLANE_CTL_ROTATE_270 0x3 6950#define _PLANE_STRIDE_1_A 0x70188 6951#define _PLANE_STRIDE_2_A 0x70288 6952#define _PLANE_STRIDE_3_A 0x70388 6953#define _PLANE_POS_1_A 0x7018c 6954#define _PLANE_POS_2_A 0x7028c 6955#define _PLANE_POS_3_A 0x7038c 6956#define _PLANE_SIZE_1_A 0x70190 6957#define _PLANE_SIZE_2_A 0x70290 6958#define _PLANE_SIZE_3_A 0x70390 6959#define _PLANE_SURF_1_A 0x7019c 6960#define _PLANE_SURF_2_A 0x7029c 6961#define _PLANE_SURF_3_A 0x7039c 6962#define _PLANE_OFFSET_1_A 0x701a4 6963#define _PLANE_OFFSET_2_A 0x702a4 6964#define _PLANE_OFFSET_3_A 0x703a4 6965#define _PLANE_KEYVAL_1_A 0x70194 6966#define _PLANE_KEYVAL_2_A 0x70294 6967#define _PLANE_KEYMSK_1_A 0x70198 6968#define _PLANE_KEYMSK_2_A 0x70298 6969#define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 6970#define _PLANE_KEYMAX_1_A 0x701a0 6971#define _PLANE_KEYMAX_2_A 0x702a0 6972#define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 6973#define _PLANE_AUX_DIST_1_A 0x701c0 6974#define _PLANE_AUX_DIST_2_A 0x702c0 6975#define _PLANE_AUX_OFFSET_1_A 0x701c4 6976#define _PLANE_AUX_OFFSET_2_A 0x702c4 6977#define _PLANE_CUS_CTL_1_A 0x701c8 6978#define _PLANE_CUS_CTL_2_A 0x702c8 6979#define PLANE_CUS_ENABLE (1 << 31) 6980#define PLANE_CUS_PLANE_4_RKL (0 << 30) 6981#define PLANE_CUS_PLANE_5_RKL (1 << 30) 6982#define PLANE_CUS_PLANE_6 (0 << 30) 6983#define PLANE_CUS_PLANE_7 (1 << 30) 6984#define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19) 6985#define PLANE_CUS_HPHASE_0 (0 << 16) 6986#define PLANE_CUS_HPHASE_0_25 (1 << 16) 6987#define PLANE_CUS_HPHASE_0_5 (2 << 16) 6988#define PLANE_CUS_VPHASE_SIGN_NEGATIVE (1 << 15) 6989#define PLANE_CUS_VPHASE_0 (0 << 12) 6990#define PLANE_CUS_VPHASE_0_25 (1 << 12) 6991#define PLANE_CUS_VPHASE_0_5 (2 << 12) 6992#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 6993#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 6994#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 6995#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */ 6996#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28) 6997#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */ 6998#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */ 6999#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17) 7000#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 (1 << 17) 7001#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 (2 << 17) 7002#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 (3 << 17) 7003#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 (4 << 17) 7004#define PLANE_COLOR_PLANE_GAMMA_DISABLE (1 << 13) 7005#define PLANE_COLOR_ALPHA_MASK (0x3 << 4) 7006#define PLANE_COLOR_ALPHA_DISABLE (0 << 4) 7007#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4) 7008#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4) 7009#define _PLANE_BUF_CFG_1_A 0x7027c 7010#define _PLANE_BUF_CFG_2_A 0x7037c 7011#define _PLANE_NV12_BUF_CFG_1_A 0x70278 7012#define _PLANE_NV12_BUF_CFG_2_A 0x70378 7013 7014/* Input CSC Register Definitions */ 7015#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 7016#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 7017 7018#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 7019#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 7020 7021#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 7022 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 7023 _PLANE_INPUT_CSC_RY_GY_1_B) 7024#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 7025 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 7026 _PLANE_INPUT_CSC_RY_GY_2_B) 7027 7028#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 7029 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 7030 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 7031 7032#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 7033#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 7034 7035#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 7036#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 7037 7038#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 7039 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 7040 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 7041#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 7042 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 7043 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 7044#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 7045 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 7046 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 7047 7048#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 7049#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 7050 7051#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 7052#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 7053 7054#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 7055 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 7056 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 7057#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 7058 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 7059 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 7060#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 7061 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 7062 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 7063 7064#define _PLANE_CTL_1_B 0x71180 7065#define _PLANE_CTL_2_B 0x71280 7066#define _PLANE_CTL_3_B 0x71380 7067#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 7068#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 7069#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 7070#define PLANE_CTL(pipe, plane) \ 7071 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 7072 7073#define _PLANE_STRIDE_1_B 0x71188 7074#define _PLANE_STRIDE_2_B 0x71288 7075#define _PLANE_STRIDE_3_B 0x71388 7076#define _PLANE_STRIDE_1(pipe) \ 7077 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 7078#define _PLANE_STRIDE_2(pipe) \ 7079 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 7080#define _PLANE_STRIDE_3(pipe) \ 7081 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 7082#define PLANE_STRIDE(pipe, plane) \ 7083 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 7084 7085#define _PLANE_POS_1_B 0x7118c 7086#define _PLANE_POS_2_B 0x7128c 7087#define _PLANE_POS_3_B 0x7138c 7088#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 7089#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 7090#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 7091#define PLANE_POS(pipe, plane) \ 7092 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 7093 7094#define _PLANE_SIZE_1_B 0x71190 7095#define _PLANE_SIZE_2_B 0x71290 7096#define _PLANE_SIZE_3_B 0x71390 7097#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 7098#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 7099#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 7100#define PLANE_SIZE(pipe, plane) \ 7101 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 7102 7103#define _PLANE_SURF_1_B 0x7119c 7104#define _PLANE_SURF_2_B 0x7129c 7105#define _PLANE_SURF_3_B 0x7139c 7106#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 7107#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 7108#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 7109#define PLANE_SURF(pipe, plane) \ 7110 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 7111 7112#define _PLANE_OFFSET_1_B 0x711a4 7113#define _PLANE_OFFSET_2_B 0x712a4 7114#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 7115#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 7116#define PLANE_OFFSET(pipe, plane) \ 7117 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 7118 7119#define _PLANE_KEYVAL_1_B 0x71194 7120#define _PLANE_KEYVAL_2_B 0x71294 7121#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 7122#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 7123#define PLANE_KEYVAL(pipe, plane) \ 7124 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 7125 7126#define _PLANE_KEYMSK_1_B 0x71198 7127#define _PLANE_KEYMSK_2_B 0x71298 7128#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 7129#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 7130#define PLANE_KEYMSK(pipe, plane) \ 7131 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 7132 7133#define _PLANE_KEYMAX_1_B 0x711a0 7134#define _PLANE_KEYMAX_2_B 0x712a0 7135#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 7136#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 7137#define PLANE_KEYMAX(pipe, plane) \ 7138 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 7139 7140#define _PLANE_BUF_CFG_1_B 0x7127c 7141#define _PLANE_BUF_CFG_2_B 0x7137c 7142#define DDB_ENTRY_MASK 0x7FF /* skl+: 10 bits, icl+ 11 bits */ 7143#define DDB_ENTRY_END_SHIFT 16 7144#define _PLANE_BUF_CFG_1(pipe) \ 7145 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 7146#define _PLANE_BUF_CFG_2(pipe) \ 7147 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 7148#define PLANE_BUF_CFG(pipe, plane) \ 7149 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 7150 7151#define _PLANE_NV12_BUF_CFG_1_B 0x71278 7152#define _PLANE_NV12_BUF_CFG_2_B 0x71378 7153#define _PLANE_NV12_BUF_CFG_1(pipe) \ 7154 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 7155#define _PLANE_NV12_BUF_CFG_2(pipe) \ 7156 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 7157#define PLANE_NV12_BUF_CFG(pipe, plane) \ 7158 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 7159 7160#define _PLANE_AUX_DIST_1_B 0x711c0 7161#define _PLANE_AUX_DIST_2_B 0x712c0 7162#define _PLANE_AUX_DIST_1(pipe) \ 7163 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 7164#define _PLANE_AUX_DIST_2(pipe) \ 7165 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 7166#define PLANE_AUX_DIST(pipe, plane) \ 7167 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 7168 7169#define _PLANE_AUX_OFFSET_1_B 0x711c4 7170#define _PLANE_AUX_OFFSET_2_B 0x712c4 7171#define _PLANE_AUX_OFFSET_1(pipe) \ 7172 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 7173#define _PLANE_AUX_OFFSET_2(pipe) \ 7174 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 7175#define PLANE_AUX_OFFSET(pipe, plane) \ 7176 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 7177 7178#define _PLANE_CUS_CTL_1_B 0x711c8 7179#define _PLANE_CUS_CTL_2_B 0x712c8 7180#define _PLANE_CUS_CTL_1(pipe) \ 7181 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 7182#define _PLANE_CUS_CTL_2(pipe) \ 7183 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 7184#define PLANE_CUS_CTL(pipe, plane) \ 7185 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 7186 7187#define _PLANE_COLOR_CTL_1_B 0x711CC 7188#define _PLANE_COLOR_CTL_2_B 0x712CC 7189#define _PLANE_COLOR_CTL_3_B 0x713CC 7190#define _PLANE_COLOR_CTL_1(pipe) \ 7191 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 7192#define _PLANE_COLOR_CTL_2(pipe) \ 7193 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 7194#define PLANE_COLOR_CTL(pipe, plane) \ 7195 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 7196 7197#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 7198#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 7199#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 7200#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 7201#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 7202#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 7203#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 7204#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 7205#define _SEL_FETCH_PLANE_BASE_1_B 0x71890 7206 7207#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 7208 _SEL_FETCH_PLANE_BASE_1_A, \ 7209 _SEL_FETCH_PLANE_BASE_2_A, \ 7210 _SEL_FETCH_PLANE_BASE_3_A, \ 7211 _SEL_FETCH_PLANE_BASE_4_A, \ 7212 _SEL_FETCH_PLANE_BASE_5_A, \ 7213 _SEL_FETCH_PLANE_BASE_6_A, \ 7214 _SEL_FETCH_PLANE_BASE_7_A, \ 7215 _SEL_FETCH_PLANE_BASE_CUR_A) 7216#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 7217#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 7218 _SEL_FETCH_PLANE_BASE_1_A + \ 7219 _SEL_FETCH_PLANE_BASE_A(plane)) 7220 7221#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 7222#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7223 _SEL_FETCH_PLANE_CTL_1_A - \ 7224 _SEL_FETCH_PLANE_BASE_1_A) 7225#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 7226 7227#define _SEL_FETCH_PLANE_POS_1_A 0x70894 7228#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7229 _SEL_FETCH_PLANE_POS_1_A - \ 7230 _SEL_FETCH_PLANE_BASE_1_A) 7231 7232#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 7233#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7234 _SEL_FETCH_PLANE_SIZE_1_A - \ 7235 _SEL_FETCH_PLANE_BASE_1_A) 7236 7237#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 7238#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 7239 _SEL_FETCH_PLANE_OFFSET_1_A - \ 7240 _SEL_FETCH_PLANE_BASE_1_A) 7241 7242/* SKL new cursor registers */ 7243#define _CUR_BUF_CFG_A 0x7017c 7244#define _CUR_BUF_CFG_B 0x7117c 7245#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 7246 7247/* VBIOS regs */ 7248#define VGACNTRL _MMIO(0x71400) 7249# define VGA_DISP_DISABLE (1 << 31) 7250# define VGA_2X_MODE (1 << 30) 7251# define VGA_PIPE_B_SELECT (1 << 29) 7252 7253#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 7254 7255/* Ironlake */ 7256 7257#define CPU_VGACNTRL _MMIO(0x41000) 7258 7259#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 7260#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 7261#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 7262#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 7263#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 7264#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 7265#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 7266#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 7267#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 7268#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 7269#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 7270 7271/* refresh rate hardware control */ 7272#define RR_HW_CTL _MMIO(0x45300) 7273#define RR_HW_LOW_POWER_FRAMES_MASK 0xff 7274#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 7275 7276#define FDI_PLL_BIOS_0 _MMIO(0x46000) 7277#define FDI_PLL_FB_CLOCK_MASK 0xff 7278#define FDI_PLL_BIOS_1 _MMIO(0x46004) 7279#define FDI_PLL_BIOS_2 _MMIO(0x46008) 7280#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 7281#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 7282#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 7283 7284#define PCH_3DCGDIS0 _MMIO(0x46020) 7285# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 7286# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 7287 7288#define PCH_3DCGDIS1 _MMIO(0x46024) 7289# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 7290 7291#define FDI_PLL_FREQ_CTL _MMIO(0x46030) 7292#define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 7293#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 7294#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 7295 7296 7297#define _PIPEA_DATA_M1 0x60030 7298#define PIPE_DATA_M1_OFFSET 0 7299#define _PIPEA_DATA_N1 0x60034 7300#define PIPE_DATA_N1_OFFSET 0 7301 7302#define _PIPEA_DATA_M2 0x60038 7303#define PIPE_DATA_M2_OFFSET 0 7304#define _PIPEA_DATA_N2 0x6003c 7305#define PIPE_DATA_N2_OFFSET 0 7306 7307#define _PIPEA_LINK_M1 0x60040 7308#define PIPE_LINK_M1_OFFSET 0 7309#define _PIPEA_LINK_N1 0x60044 7310#define PIPE_LINK_N1_OFFSET 0 7311 7312#define _PIPEA_LINK_M2 0x60048 7313#define PIPE_LINK_M2_OFFSET 0 7314#define _PIPEA_LINK_N2 0x6004c 7315#define PIPE_LINK_N2_OFFSET 0 7316 7317/* PIPEB timing regs are same start from 0x61000 */ 7318 7319#define _PIPEB_DATA_M1 0x61030 7320#define _PIPEB_DATA_N1 0x61034 7321#define _PIPEB_DATA_M2 0x61038 7322#define _PIPEB_DATA_N2 0x6103c 7323#define _PIPEB_LINK_M1 0x61040 7324#define _PIPEB_LINK_N1 0x61044 7325#define _PIPEB_LINK_M2 0x61048 7326#define _PIPEB_LINK_N2 0x6104c 7327 7328#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 7329#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 7330#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 7331#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 7332#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 7333#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 7334#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 7335#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 7336 7337/* CPU panel fitter */ 7338/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 7339#define _PFA_CTL_1 0x68080 7340#define _PFB_CTL_1 0x68880 7341#define PF_ENABLE (1 << 31) 7342#define PF_PIPE_SEL_MASK_IVB (3 << 29) 7343#define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 7344#define PF_FILTER_MASK (3 << 23) 7345#define PF_FILTER_PROGRAMMED (0 << 23) 7346#define PF_FILTER_MED_3x3 (1 << 23) 7347#define PF_FILTER_EDGE_ENHANCE (2 << 23) 7348#define PF_FILTER_EDGE_SOFTEN (3 << 23) 7349#define _PFA_WIN_SZ 0x68074 7350#define _PFB_WIN_SZ 0x68874 7351#define _PFA_WIN_POS 0x68070 7352#define _PFB_WIN_POS 0x68870 7353#define _PFA_VSCALE 0x68084 7354#define _PFB_VSCALE 0x68884 7355#define _PFA_HSCALE 0x68090 7356#define _PFB_HSCALE 0x68890 7357 7358#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 7359#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 7360#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 7361#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 7362#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 7363 7364#define _PSA_CTL 0x68180 7365#define _PSB_CTL 0x68980 7366#define PS_ENABLE (1 << 31) 7367#define _PSA_WIN_SZ 0x68174 7368#define _PSB_WIN_SZ 0x68974 7369#define _PSA_WIN_POS 0x68170 7370#define _PSB_WIN_POS 0x68970 7371 7372#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 7373#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 7374#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 7375 7376/* 7377 * Skylake scalers 7378 */ 7379#define _PS_1A_CTRL 0x68180 7380#define _PS_2A_CTRL 0x68280 7381#define _PS_1B_CTRL 0x68980 7382#define _PS_2B_CTRL 0x68A80 7383#define _PS_1C_CTRL 0x69180 7384#define PS_SCALER_EN (1 << 31) 7385#define SKL_PS_SCALER_MODE_MASK (3 << 28) 7386#define SKL_PS_SCALER_MODE_DYN (0 << 28) 7387#define SKL_PS_SCALER_MODE_HQ (1 << 28) 7388#define SKL_PS_SCALER_MODE_NV12 (2 << 28) 7389#define PS_SCALER_MODE_PLANAR (1 << 29) 7390#define PS_SCALER_MODE_NORMAL (0 << 29) 7391#define PS_PLANE_SEL_MASK (7 << 25) 7392#define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 7393#define PS_FILTER_MASK (3 << 23) 7394#define PS_FILTER_MEDIUM (0 << 23) 7395#define PS_FILTER_EDGE_ENHANCE (2 << 23) 7396#define PS_FILTER_BILINEAR (3 << 23) 7397#define PS_VERT3TAP (1 << 21) 7398#define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 7399#define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 7400#define PS_PWRUP_PROGRESS (1 << 17) 7401#define PS_V_FILTER_BYPASS (1 << 8) 7402#define PS_VADAPT_EN (1 << 7) 7403#define PS_VADAPT_MODE_MASK (3 << 5) 7404#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 7405#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 7406#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 7407#define PS_PLANE_Y_SEL_MASK (7 << 5) 7408#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 7409 7410#define _PS_PWR_GATE_1A 0x68160 7411#define _PS_PWR_GATE_2A 0x68260 7412#define _PS_PWR_GATE_1B 0x68960 7413#define _PS_PWR_GATE_2B 0x68A60 7414#define _PS_PWR_GATE_1C 0x69160 7415#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 7416#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 7417#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 7418#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 7419#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 7420#define PS_PWR_GATE_SLPEN_8 0 7421#define PS_PWR_GATE_SLPEN_16 1 7422#define PS_PWR_GATE_SLPEN_24 2 7423#define PS_PWR_GATE_SLPEN_32 3 7424 7425#define _PS_WIN_POS_1A 0x68170 7426#define _PS_WIN_POS_2A 0x68270 7427#define _PS_WIN_POS_1B 0x68970 7428#define _PS_WIN_POS_2B 0x68A70 7429#define _PS_WIN_POS_1C 0x69170 7430 7431#define _PS_WIN_SZ_1A 0x68174 7432#define _PS_WIN_SZ_2A 0x68274 7433#define _PS_WIN_SZ_1B 0x68974 7434#define _PS_WIN_SZ_2B 0x68A74 7435#define _PS_WIN_SZ_1C 0x69174 7436 7437#define _PS_VSCALE_1A 0x68184 7438#define _PS_VSCALE_2A 0x68284 7439#define _PS_VSCALE_1B 0x68984 7440#define _PS_VSCALE_2B 0x68A84 7441#define _PS_VSCALE_1C 0x69184 7442 7443#define _PS_HSCALE_1A 0x68190 7444#define _PS_HSCALE_2A 0x68290 7445#define _PS_HSCALE_1B 0x68990 7446#define _PS_HSCALE_2B 0x68A90 7447#define _PS_HSCALE_1C 0x69190 7448 7449#define _PS_VPHASE_1A 0x68188 7450#define _PS_VPHASE_2A 0x68288 7451#define _PS_VPHASE_1B 0x68988 7452#define _PS_VPHASE_2B 0x68A88 7453#define _PS_VPHASE_1C 0x69188 7454#define PS_Y_PHASE(x) ((x) << 16) 7455#define PS_UV_RGB_PHASE(x) ((x) << 0) 7456#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 7457#define PS_PHASE_TRIP (1 << 0) 7458 7459#define _PS_HPHASE_1A 0x68194 7460#define _PS_HPHASE_2A 0x68294 7461#define _PS_HPHASE_1B 0x68994 7462#define _PS_HPHASE_2B 0x68A94 7463#define _PS_HPHASE_1C 0x69194 7464 7465#define _PS_ECC_STAT_1A 0x681D0 7466#define _PS_ECC_STAT_2A 0x682D0 7467#define _PS_ECC_STAT_1B 0x689D0 7468#define _PS_ECC_STAT_2B 0x68AD0 7469#define _PS_ECC_STAT_1C 0x691D0 7470 7471#define _ID(id, a, b) _PICK_EVEN(id, a, b) 7472#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 7473 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 7474 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 7475#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 7476 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 7477 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 7478#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 7479 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 7480 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 7481#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 7482 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 7483 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 7484#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7485 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 7486 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 7487#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 7488 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 7489 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 7490#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7491 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 7492 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 7493#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 7494 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 7495 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 7496#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 7497 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 7498 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 7499 7500/* legacy palette */ 7501#define _LGC_PALETTE_A 0x4a000 7502#define _LGC_PALETTE_B 0x4a800 7503#define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 7504#define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 7505#define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 7506#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 7507 7508/* ilk/snb precision palette */ 7509#define _PREC_PALETTE_A 0x4b000 7510#define _PREC_PALETTE_B 0x4c000 7511#define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 7512#define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 7513#define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 7514#define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 7515 7516#define _PREC_PIPEAGCMAX 0x4d000 7517#define _PREC_PIPEBGCMAX 0x4d010 7518#define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 7519 7520#define _GAMMA_MODE_A 0x4a480 7521#define _GAMMA_MODE_B 0x4ac80 7522#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 7523#define PRE_CSC_GAMMA_ENABLE (1 << 31) 7524#define POST_CSC_GAMMA_ENABLE (1 << 30) 7525#define GAMMA_MODE_MODE_MASK (3 << 0) 7526#define GAMMA_MODE_MODE_8BIT (0 << 0) 7527#define GAMMA_MODE_MODE_10BIT (1 << 0) 7528#define GAMMA_MODE_MODE_12BIT (2 << 0) 7529#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 7530#define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 7531 7532/* DMC/CSR */ 7533#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) 7534#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0 7535#define CSR_HTP_ADDR_SKL 0x00500034 7536#define CSR_SSP_BASE _MMIO(0x8F074) 7537#define CSR_HTP_SKL _MMIO(0x8F004) 7538#define CSR_LAST_WRITE _MMIO(0x8F034) 7539#define CSR_LAST_WRITE_VALUE 0xc003b400 7540/* MMIO address range for CSR program (0x80000 - 0x82FFF) */ 7541#define CSR_MMIO_START_RANGE 0x80000 7542#define CSR_MMIO_END_RANGE 0x8FFFF 7543#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030) 7544#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) 7545#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) 7546#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) 7547#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) 7548 7549#define TGL_DMC_DEBUG3 _MMIO(0x101090) 7550#define DG1_DMC_DEBUG3 _MMIO(0x13415c) 7551 7552/* Display Internal Timeout Register */ 7553#define RM_TIMEOUT _MMIO(0x42060) 7554#define MMIO_TIMEOUT_US(us) ((us) << 0) 7555 7556/* interrupts */ 7557#define DE_MASTER_IRQ_CONTROL (1 << 31) 7558#define DE_SPRITEB_FLIP_DONE (1 << 29) 7559#define DE_SPRITEA_FLIP_DONE (1 << 28) 7560#define DE_PLANEB_FLIP_DONE (1 << 27) 7561#define DE_PLANEA_FLIP_DONE (1 << 26) 7562#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 7563#define DE_PCU_EVENT (1 << 25) 7564#define DE_GTT_FAULT (1 << 24) 7565#define DE_POISON (1 << 23) 7566#define DE_PERFORM_COUNTER (1 << 22) 7567#define DE_PCH_EVENT (1 << 21) 7568#define DE_AUX_CHANNEL_A (1 << 20) 7569#define DE_DP_A_HOTPLUG (1 << 19) 7570#define DE_GSE (1 << 18) 7571#define DE_PIPEB_VBLANK (1 << 15) 7572#define DE_PIPEB_EVEN_FIELD (1 << 14) 7573#define DE_PIPEB_ODD_FIELD (1 << 13) 7574#define DE_PIPEB_LINE_COMPARE (1 << 12) 7575#define DE_PIPEB_VSYNC (1 << 11) 7576#define DE_PIPEB_CRC_DONE (1 << 10) 7577#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 7578#define DE_PIPEA_VBLANK (1 << 7) 7579#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 7580#define DE_PIPEA_EVEN_FIELD (1 << 6) 7581#define DE_PIPEA_ODD_FIELD (1 << 5) 7582#define DE_PIPEA_LINE_COMPARE (1 << 4) 7583#define DE_PIPEA_VSYNC (1 << 3) 7584#define DE_PIPEA_CRC_DONE (1 << 2) 7585#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 7586#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 7587#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 7588 7589/* More Ivybridge lolz */ 7590#define DE_ERR_INT_IVB (1 << 30) 7591#define DE_GSE_IVB (1 << 29) 7592#define DE_PCH_EVENT_IVB (1 << 28) 7593#define DE_DP_A_HOTPLUG_IVB (1 << 27) 7594#define DE_AUX_CHANNEL_A_IVB (1 << 26) 7595#define DE_EDP_PSR_INT_HSW (1 << 19) 7596#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 7597#define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 7598#define DE_PIPEC_VBLANK_IVB (1 << 10) 7599#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 7600#define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 7601#define DE_PIPEB_VBLANK_IVB (1 << 5) 7602#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 7603#define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 7604#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 7605#define DE_PIPEA_VBLANK_IVB (1 << 0) 7606#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 7607 7608#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 7609#define MASTER_INTERRUPT_ENABLE (1 << 31) 7610 7611#define DEISR _MMIO(0x44000) 7612#define DEIMR _MMIO(0x44004) 7613#define DEIIR _MMIO(0x44008) 7614#define DEIER _MMIO(0x4400c) 7615 7616#define GTISR _MMIO(0x44010) 7617#define GTIMR _MMIO(0x44014) 7618#define GTIIR _MMIO(0x44018) 7619#define GTIER _MMIO(0x4401c) 7620 7621#define GEN8_MASTER_IRQ _MMIO(0x44200) 7622#define GEN8_MASTER_IRQ_CONTROL (1 << 31) 7623#define GEN8_PCU_IRQ (1 << 30) 7624#define GEN8_DE_PCH_IRQ (1 << 23) 7625#define GEN8_DE_MISC_IRQ (1 << 22) 7626#define GEN8_DE_PORT_IRQ (1 << 20) 7627#define GEN8_DE_PIPE_C_IRQ (1 << 18) 7628#define GEN8_DE_PIPE_B_IRQ (1 << 17) 7629#define GEN8_DE_PIPE_A_IRQ (1 << 16) 7630#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 7631#define GEN8_GT_VECS_IRQ (1 << 6) 7632#define GEN8_GT_GUC_IRQ (1 << 5) 7633#define GEN8_GT_PM_IRQ (1 << 4) 7634#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 7635#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 7636#define GEN8_GT_BCS_IRQ (1 << 1) 7637#define GEN8_GT_RCS_IRQ (1 << 0) 7638 7639#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 7640#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 7641#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 7642#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 7643 7644#define GEN8_RCS_IRQ_SHIFT 0 7645#define GEN8_BCS_IRQ_SHIFT 16 7646#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 7647#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 7648#define GEN8_VECS_IRQ_SHIFT 0 7649#define GEN8_WD_IRQ_SHIFT 16 7650 7651#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 7652#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 7653#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 7654#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 7655#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 7656#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 7657#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 7658#define GEN8_PIPE_CURSOR_FAULT (1 << 10) 7659#define GEN8_PIPE_SPRITE_FAULT (1 << 9) 7660#define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 7661#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 7662#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 7663#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 7664#define GEN8_PIPE_VSYNC (1 << 1) 7665#define GEN8_PIPE_VBLANK (1 << 0) 7666#define GEN9_PIPE_CURSOR_FAULT (1 << 11) 7667#define GEN11_PIPE_PLANE7_FAULT (1 << 22) 7668#define GEN11_PIPE_PLANE6_FAULT (1 << 21) 7669#define GEN11_PIPE_PLANE5_FAULT (1 << 20) 7670#define GEN9_PIPE_PLANE4_FAULT (1 << 10) 7671#define GEN9_PIPE_PLANE3_FAULT (1 << 9) 7672#define GEN9_PIPE_PLANE2_FAULT (1 << 8) 7673#define GEN9_PIPE_PLANE1_FAULT (1 << 7) 7674#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 7675#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 7676#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 7677#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 7678#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 7679#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 7680 (GEN8_PIPE_CURSOR_FAULT | \ 7681 GEN8_PIPE_SPRITE_FAULT | \ 7682 GEN8_PIPE_PRIMARY_FAULT) 7683#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 7684 (GEN9_PIPE_CURSOR_FAULT | \ 7685 GEN9_PIPE_PLANE4_FAULT | \ 7686 GEN9_PIPE_PLANE3_FAULT | \ 7687 GEN9_PIPE_PLANE2_FAULT | \ 7688 GEN9_PIPE_PLANE1_FAULT) 7689#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 7690 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 7691 GEN11_PIPE_PLANE7_FAULT | \ 7692 GEN11_PIPE_PLANE6_FAULT | \ 7693 GEN11_PIPE_PLANE5_FAULT) 7694#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 7695 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 7696 GEN11_PIPE_PLANE5_FAULT) 7697 7698#define GEN8_DE_PORT_ISR _MMIO(0x44440) 7699#define GEN8_DE_PORT_IMR _MMIO(0x44444) 7700#define GEN8_DE_PORT_IIR _MMIO(0x44448) 7701#define GEN8_DE_PORT_IER _MMIO(0x4444c) 7702#define DSI1_NON_TE (1 << 31) 7703#define DSI0_NON_TE (1 << 30) 7704#define ICL_AUX_CHANNEL_E (1 << 29) 7705#define CNL_AUX_CHANNEL_F (1 << 28) 7706#define GEN9_AUX_CHANNEL_D (1 << 27) 7707#define GEN9_AUX_CHANNEL_C (1 << 26) 7708#define GEN9_AUX_CHANNEL_B (1 << 25) 7709#define DSI1_TE (1 << 24) 7710#define DSI0_TE (1 << 23) 7711#define BXT_DE_PORT_HP_DDIC (1 << 5) 7712#define BXT_DE_PORT_HP_DDIB (1 << 4) 7713#define BXT_DE_PORT_HP_DDIA (1 << 3) 7714#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \ 7715 BXT_DE_PORT_HP_DDIB | \ 7716 BXT_DE_PORT_HP_DDIC) 7717#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 7718#define BXT_DE_PORT_GMBUS (1 << 1) 7719#define GEN8_AUX_CHANNEL_A (1 << 0) 7720#define TGL_DE_PORT_AUX_USBC6 (1 << 13) 7721#define TGL_DE_PORT_AUX_USBC5 (1 << 12) 7722#define TGL_DE_PORT_AUX_USBC4 (1 << 11) 7723#define TGL_DE_PORT_AUX_USBC3 (1 << 10) 7724#define TGL_DE_PORT_AUX_USBC2 (1 << 9) 7725#define TGL_DE_PORT_AUX_USBC1 (1 << 8) 7726#define TGL_DE_PORT_AUX_DDIC (1 << 2) 7727#define TGL_DE_PORT_AUX_DDIB (1 << 1) 7728#define TGL_DE_PORT_AUX_DDIA (1 << 0) 7729 7730#define GEN8_DE_MISC_ISR _MMIO(0x44460) 7731#define GEN8_DE_MISC_IMR _MMIO(0x44464) 7732#define GEN8_DE_MISC_IIR _MMIO(0x44468) 7733#define GEN8_DE_MISC_IER _MMIO(0x4446c) 7734#define GEN8_DE_MISC_GSE (1 << 27) 7735#define GEN8_DE_EDP_PSR (1 << 19) 7736 7737#define GEN8_PCU_ISR _MMIO(0x444e0) 7738#define GEN8_PCU_IMR _MMIO(0x444e4) 7739#define GEN8_PCU_IIR _MMIO(0x444e8) 7740#define GEN8_PCU_IER _MMIO(0x444ec) 7741 7742#define GEN11_GU_MISC_ISR _MMIO(0x444f0) 7743#define GEN11_GU_MISC_IMR _MMIO(0x444f4) 7744#define GEN11_GU_MISC_IIR _MMIO(0x444f8) 7745#define GEN11_GU_MISC_IER _MMIO(0x444fc) 7746#define GEN11_GU_MISC_GSE (1 << 27) 7747 7748#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 7749#define GEN11_MASTER_IRQ (1 << 31) 7750#define GEN11_PCU_IRQ (1 << 30) 7751#define GEN11_GU_MISC_IRQ (1 << 29) 7752#define GEN11_DISPLAY_IRQ (1 << 16) 7753#define GEN11_GT_DW_IRQ(x) (1 << (x)) 7754#define GEN11_GT_DW1_IRQ (1 << 1) 7755#define GEN11_GT_DW0_IRQ (1 << 0) 7756 7757#define DG1_MSTR_UNIT_INTR _MMIO(0x190008) 7758#define DG1_MSTR_IRQ REG_BIT(31) 7759#define DG1_MSTR_UNIT(u) REG_BIT(u) 7760 7761#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 7762#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 7763#define GEN11_AUDIO_CODEC_IRQ (1 << 24) 7764#define GEN11_DE_PCH_IRQ (1 << 23) 7765#define GEN11_DE_MISC_IRQ (1 << 22) 7766#define GEN11_DE_HPD_IRQ (1 << 21) 7767#define GEN11_DE_PORT_IRQ (1 << 20) 7768#define GEN11_DE_PIPE_C (1 << 18) 7769#define GEN11_DE_PIPE_B (1 << 17) 7770#define GEN11_DE_PIPE_A (1 << 16) 7771 7772#define GEN11_DE_HPD_ISR _MMIO(0x44470) 7773#define GEN11_DE_HPD_IMR _MMIO(0x44474) 7774#define GEN11_DE_HPD_IIR _MMIO(0x44478) 7775#define GEN11_DE_HPD_IER _MMIO(0x4447c) 7776#define GEN11_TC_HOTPLUG(tc_port) (1 << ((tc_port) + 16)) 7777#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(PORT_TC6) | \ 7778 GEN11_TC_HOTPLUG(PORT_TC5) | \ 7779 GEN11_TC_HOTPLUG(PORT_TC4) | \ 7780 GEN11_TC_HOTPLUG(PORT_TC3) | \ 7781 GEN11_TC_HOTPLUG(PORT_TC2) | \ 7782 GEN11_TC_HOTPLUG(PORT_TC1)) 7783#define GEN11_TBT_HOTPLUG(tc_port) (1 << (tc_port)) 7784#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(PORT_TC6) | \ 7785 GEN11_TBT_HOTPLUG(PORT_TC5) | \ 7786 GEN11_TBT_HOTPLUG(PORT_TC4) | \ 7787 GEN11_TBT_HOTPLUG(PORT_TC3) | \ 7788 GEN11_TBT_HOTPLUG(PORT_TC2) | \ 7789 GEN11_TBT_HOTPLUG(PORT_TC1)) 7790 7791#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 7792#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 7793#define GEN11_HOTPLUG_CTL_ENABLE(tc_port) (8 << (tc_port) * 4) 7794#define GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 7795#define GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 7796#define GEN11_HOTPLUG_CTL_NO_DETECT(tc_port) (0 << (tc_port) * 4) 7797 7798#define GEN11_GT_INTR_DW0 _MMIO(0x190018) 7799#define GEN11_CSME (31) 7800#define GEN11_GUNIT (28) 7801#define GEN11_GUC (25) 7802#define GEN11_WDPERF (20) 7803#define GEN11_KCR (19) 7804#define GEN11_GTPM (16) 7805#define GEN11_BCS (15) 7806#define GEN11_RCS0 (0) 7807 7808#define GEN11_GT_INTR_DW1 _MMIO(0x19001c) 7809#define GEN11_VECS(x) (31 - (x)) 7810#define GEN11_VCS(x) (x) 7811 7812#define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 7813 7814#define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) 7815#define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) 7816#define GEN11_INTR_DATA_VALID (1 << 31) 7817#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 7818#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 7819#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 7820/* irq instances for OTHER_CLASS */ 7821#define OTHER_GUC_INSTANCE 0 7822#define OTHER_GTPM_INSTANCE 1 7823 7824#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 7825 7826#define GEN11_IIR_REG0_SELECTOR _MMIO(0x190070) 7827#define GEN11_IIR_REG1_SELECTOR _MMIO(0x190074) 7828 7829#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 7830 7831#define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 7832#define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 7833#define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 7834#define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 7835#define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 7836#define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 7837 7838#define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 7839#define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 7840#define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 7841#define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 7842#define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 7843#define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 7844#define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 7845#define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 7846#define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 7847 7848#define ENGINE1_MASK REG_GENMASK(31, 16) 7849#define ENGINE0_MASK REG_GENMASK(15, 0) 7850 7851#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 7852/* Required on all Ironlake and Sandybridge according to the B-Spec. */ 7853#define ILK_ELPIN_409_SELECT (1 << 25) 7854#define ILK_DPARB_GATE (1 << 22) 7855#define ILK_VSDPFD_FULL (1 << 21) 7856#define FUSE_STRAP _MMIO(0x42014) 7857#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 7858#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 7859#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 7860#define IVB_PIPE_C_DISABLE (1 << 28) 7861#define ILK_HDCP_DISABLE (1 << 25) 7862#define ILK_eDP_A_DISABLE (1 << 24) 7863#define HSW_CDCLK_LIMIT (1 << 24) 7864#define ILK_DESKTOP (1 << 23) 7865#define HSW_CPU_SSC_ENABLE (1 << 21) 7866 7867#define FUSE_STRAP3 _MMIO(0x42020) 7868#define HSW_REF_CLK_SELECT (1 << 1) 7869 7870#define ILK_DSPCLK_GATE_D _MMIO(0x42020) 7871#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 7872#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 7873#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 7874#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 7875#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 7876 7877#define IVB_CHICKEN3 _MMIO(0x4200c) 7878# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 7879# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 7880 7881#define CHICKEN_PAR1_1 _MMIO(0x42080) 7882#define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 7883#define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 7884#define DPA_MASK_VBLANK_SRD (1 << 15) 7885#define FORCE_ARB_IDLE_PLANES (1 << 14) 7886#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 7887#define IGNORE_PSR2_HW_TRACKING (1 << 1) 7888 7889#define CHICKEN_PAR2_1 _MMIO(0x42090) 7890#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 7891 7892#define CHICKEN_MISC_2 _MMIO(0x42084) 7893#define CNL_COMP_PWR_DOWN (1 << 23) 7894#define GLK_CL2_PWR_DOWN (1 << 12) 7895#define GLK_CL1_PWR_DOWN (1 << 11) 7896#define GLK_CL0_PWR_DOWN (1 << 10) 7897 7898#define CHICKEN_MISC_4 _MMIO(0x4208c) 7899#define FBC_STRIDE_OVERRIDE (1 << 13) 7900#define FBC_STRIDE_MASK 0x1FFF 7901 7902#define _CHICKEN_PIPESL_1_A 0x420b0 7903#define _CHICKEN_PIPESL_1_B 0x420b4 7904#define HSW_FBCQ_DIS (1 << 22) 7905#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 7906#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 7907 7908#define _CHICKEN_TRANS_A 0x420c0 7909#define _CHICKEN_TRANS_B 0x420c4 7910#define _CHICKEN_TRANS_C 0x420c8 7911#define _CHICKEN_TRANS_EDP 0x420cc 7912#define _CHICKEN_TRANS_D 0x420d8 7913#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 7914 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 7915 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 7916 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 7917 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 7918 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 7919#define HSW_FRAME_START_DELAY_MASK (3 << 27) 7920#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 7921#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */ 7922#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19) 7923#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18) 7924#define DDIE_TRAINING_OVERRIDE_ENABLE (1 << 17) /* CHICKEN_TRANS_A only */ 7925#define DDIE_TRAINING_OVERRIDE_VALUE (1 << 16) /* CHICKEN_TRANS_A only */ 7926#define PSR2_ADD_VERTICAL_LINE_COUNT (1 << 15) 7927#define PSR2_VSC_ENABLE_PROG_HEADER (1 << 12) 7928 7929#define DISP_ARB_CTL _MMIO(0x45000) 7930#define DISP_FBC_MEMORY_WAKE (1 << 31) 7931#define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 7932#define DISP_FBC_WM_DIS (1 << 15) 7933#define DISP_ARB_CTL2 _MMIO(0x45004) 7934#define DISP_DATA_PARTITION_5_6 (1 << 6) 7935#define DISP_IPC_ENABLE (1 << 3) 7936#define _DBUF_CTL_S1 0x45008 7937#define _DBUF_CTL_S2 0x44FE8 7938#define DBUF_CTL_S(slice) _MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2)) 7939#define DBUF_POWER_REQUEST (1 << 31) 7940#define DBUF_POWER_STATE (1 << 30) 7941#define GEN7_MSG_CTL _MMIO(0x45010) 7942#define WAIT_FOR_PCH_RESET_ACK (1 << 1) 7943#define WAIT_FOR_PCH_FLR_ACK (1 << 0) 7944 7945#define _BW_BUDDY0_CTL 0x45130 7946#define _BW_BUDDY1_CTL 0x45140 7947#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 7948 _BW_BUDDY0_CTL, \ 7949 _BW_BUDDY1_CTL)) 7950#define BW_BUDDY_DISABLE REG_BIT(31) 7951#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 7952#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 7953 7954#define _BW_BUDDY0_PAGE_MASK 0x45134 7955#define _BW_BUDDY1_PAGE_MASK 0x45144 7956#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 7957 _BW_BUDDY0_PAGE_MASK, \ 7958 _BW_BUDDY1_PAGE_MASK)) 7959 7960#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 7961#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 7962 7963#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 7964#define SKL_SELECT_ALTERNATE_DC_EXIT (1 << 30) 7965#define CNL_DELAY_PMRSP (1 << 22) 7966#define MASK_WAKEMEM (1 << 13) 7967#define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7) 7968 7969#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 7970#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 7971#define DCPR_MASK_LPMODE REG_BIT(26) 7972#define DCPR_SEND_RESP_IMM REG_BIT(25) 7973#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 7974 7975#define SKL_DFSM _MMIO(0x51000) 7976#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 7977#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 7978#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 7979#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 7980#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 7981#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 7982#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 7983#define ICL_DFSM_DMC_DISABLE (1 << 23) 7984#define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 7985#define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 7986#define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 7987#define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 7988#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 7989 7990#define SKL_DSSM _MMIO(0x51004) 7991#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) 7992#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 7993#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 7994#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 7995#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 7996 7997#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 7998#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 7999 8000#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 8001#define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 8002#define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 8003 8004#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 8005#define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 8006#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 8007#define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11) 8008 8009#define GEN8_CS_CHICKEN1 _MMIO(0x2580) 8010#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 8011#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 8012#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 8013#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 8014#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 8015#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 8016 8017/* GEN7 chicken */ 8018#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 8019 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) 8020 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 8021 8022#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 8023 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 8024 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 8025 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 8026 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 8027 8028#define GEN8_L3CNTLREG _MMIO(0x7034) 8029 #define GEN8_ERRDETBCTRL (1 << 9) 8030 8031#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 8032 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) 8033 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE (1 << 9) 8034 8035#define HIZ_CHICKEN _MMIO(0x7018) 8036# define CHV_HZ_8X8_MODE_IN_1X (1 << 15) 8037# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1 << 3) 8038 8039#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308) 8040#define DISABLE_PIXEL_MASK_CAMMING (1 << 14) 8041 8042#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 8043#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 8044 8045#define GEN7_SARCHKMD _MMIO(0xB000) 8046#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 8047#define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 8048 8049#define GEN7_L3SQCREG1 _MMIO(0xB010) 8050#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 8051 8052#define GEN8_L3SQCREG1 _MMIO(0xB100) 8053/* 8054 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 8055 * Using the formula in BSpec leads to a hang, while the formula here works 8056 * fine and matches the formulas for all other platforms. A BSpec change 8057 * request has been filed to clarify this. 8058 */ 8059#define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 8060#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 8061#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 8062 8063#define GEN7_L3CNTLREG1 _MMIO(0xB01C) 8064#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 8065#define GEN7_L3AGDIS (1 << 19) 8066#define GEN7_L3CNTLREG2 _MMIO(0xB020) 8067#define GEN7_L3CNTLREG3 _MMIO(0xB024) 8068 8069#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030) 8070#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 8071#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xB114) 8072#define GEN11_I2M_WRITE_DISABLE (1 << 28) 8073 8074#define GEN7_L3SQCREG4 _MMIO(0xb034) 8075#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 8076 8077#define GEN11_SCRATCH2 _MMIO(0xb140) 8078#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19) 8079 8080#define GEN8_L3SQCREG4 _MMIO(0xb118) 8081#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 8082#define GEN8_LQSC_RO_PERF_DIS (1 << 27) 8083#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 8084 8085/* GEN8 chicken */ 8086#define HDC_CHICKEN0 _MMIO(0x7300) 8087#define CNL_HDC_CHICKEN0 _MMIO(0xE5F0) 8088#define ICL_HDC_MODE _MMIO(0xE5F4) 8089#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 8090#define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 8091#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 8092#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 8093#define HDC_FORCE_NON_COHERENT (1 << 4) 8094#define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 8095 8096#define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 8097 8098/* GEN9 chicken */ 8099#define SLICE_ECO_CHICKEN0 _MMIO(0x7308) 8100#define PIXEL_MASK_CAMMING_DISABLE (1 << 14) 8101 8102#define GEN9_WM_CHICKEN3 _MMIO(0x5588) 8103#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 8104 8105/* WaCatErrorRejectionIssue */ 8106#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 8107#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 8108 8109#define HSW_SCRATCH1 _MMIO(0xb038) 8110#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 8111 8112#define BDW_SCRATCH1 _MMIO(0xb11c) 8113#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 8114 8115/*GEN11 chicken */ 8116#define _PIPEA_CHICKEN 0x70038 8117#define _PIPEB_CHICKEN 0x71038 8118#define _PIPEC_CHICKEN 0x72038 8119#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 8120 _PIPEB_CHICKEN) 8121#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) 8122#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) 8123 8124#define FF_MODE2 _MMIO(0x6604) 8125#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 8126#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 8127#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 8128#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 8129 8130/* PCH */ 8131 8132#define PCH_DISPLAY_BASE 0xc0000u 8133 8134/* south display engine interrupt: IBX */ 8135#define SDE_AUDIO_POWER_D (1 << 27) 8136#define SDE_AUDIO_POWER_C (1 << 26) 8137#define SDE_AUDIO_POWER_B (1 << 25) 8138#define SDE_AUDIO_POWER_SHIFT (25) 8139#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 8140#define SDE_GMBUS (1 << 24) 8141#define SDE_AUDIO_HDCP_TRANSB (1 << 23) 8142#define SDE_AUDIO_HDCP_TRANSA (1 << 22) 8143#define SDE_AUDIO_HDCP_MASK (3 << 22) 8144#define SDE_AUDIO_TRANSB (1 << 21) 8145#define SDE_AUDIO_TRANSA (1 << 20) 8146#define SDE_AUDIO_TRANS_MASK (3 << 20) 8147#define SDE_POISON (1 << 19) 8148/* 18 reserved */ 8149#define SDE_FDI_RXB (1 << 17) 8150#define SDE_FDI_RXA (1 << 16) 8151#define SDE_FDI_MASK (3 << 16) 8152#define SDE_AUXD (1 << 15) 8153#define SDE_AUXC (1 << 14) 8154#define SDE_AUXB (1 << 13) 8155#define SDE_AUX_MASK (7 << 13) 8156/* 12 reserved */ 8157#define SDE_CRT_HOTPLUG (1 << 11) 8158#define SDE_PORTD_HOTPLUG (1 << 10) 8159#define SDE_PORTC_HOTPLUG (1 << 9) 8160#define SDE_PORTB_HOTPLUG (1 << 8) 8161#define SDE_SDVOB_HOTPLUG (1 << 6) 8162#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 8163 SDE_SDVOB_HOTPLUG | \ 8164 SDE_PORTB_HOTPLUG | \ 8165 SDE_PORTC_HOTPLUG | \ 8166 SDE_PORTD_HOTPLUG) 8167#define SDE_TRANSB_CRC_DONE (1 << 5) 8168#define SDE_TRANSB_CRC_ERR (1 << 4) 8169#define SDE_TRANSB_FIFO_UNDER (1 << 3) 8170#define SDE_TRANSA_CRC_DONE (1 << 2) 8171#define SDE_TRANSA_CRC_ERR (1 << 1) 8172#define SDE_TRANSA_FIFO_UNDER (1 << 0) 8173#define SDE_TRANS_MASK (0x3f) 8174 8175/* south display engine interrupt: CPT - CNP */ 8176#define SDE_AUDIO_POWER_D_CPT (1 << 31) 8177#define SDE_AUDIO_POWER_C_CPT (1 << 30) 8178#define SDE_AUDIO_POWER_B_CPT (1 << 29) 8179#define SDE_AUDIO_POWER_SHIFT_CPT 29 8180#define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 8181#define SDE_AUXD_CPT (1 << 27) 8182#define SDE_AUXC_CPT (1 << 26) 8183#define SDE_AUXB_CPT (1 << 25) 8184#define SDE_AUX_MASK_CPT (7 << 25) 8185#define SDE_PORTE_HOTPLUG_SPT (1 << 25) 8186#define SDE_PORTA_HOTPLUG_SPT (1 << 24) 8187#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 8188#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 8189#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 8190#define SDE_CRT_HOTPLUG_CPT (1 << 19) 8191#define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 8192#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 8193 SDE_SDVOB_HOTPLUG_CPT | \ 8194 SDE_PORTD_HOTPLUG_CPT | \ 8195 SDE_PORTC_HOTPLUG_CPT | \ 8196 SDE_PORTB_HOTPLUG_CPT) 8197#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 8198 SDE_PORTD_HOTPLUG_CPT | \ 8199 SDE_PORTC_HOTPLUG_CPT | \ 8200 SDE_PORTB_HOTPLUG_CPT | \ 8201 SDE_PORTA_HOTPLUG_SPT) 8202#define SDE_GMBUS_CPT (1 << 17) 8203#define SDE_ERROR_CPT (1 << 16) 8204#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 8205#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 8206#define SDE_FDI_RXC_CPT (1 << 8) 8207#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 8208#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 8209#define SDE_FDI_RXB_CPT (1 << 4) 8210#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 8211#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 8212#define SDE_FDI_RXA_CPT (1 << 0) 8213#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 8214 SDE_AUDIO_CP_REQ_B_CPT | \ 8215 SDE_AUDIO_CP_REQ_A_CPT) 8216#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 8217 SDE_AUDIO_CP_CHG_B_CPT | \ 8218 SDE_AUDIO_CP_CHG_A_CPT) 8219#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 8220 SDE_FDI_RXB_CPT | \ 8221 SDE_FDI_RXA_CPT) 8222 8223/* south display engine interrupt: ICP/TGP */ 8224#define SDE_GMBUS_ICP (1 << 23) 8225#define SDE_TC_HOTPLUG_ICP(tc_port) (1 << ((tc_port) + 24)) 8226#define SDE_DDI_HOTPLUG_ICP(port) (1 << ((port) + 16)) 8227#define SDE_DDI_MASK_ICP (SDE_DDI_HOTPLUG_ICP(PORT_B) | \ 8228 SDE_DDI_HOTPLUG_ICP(PORT_A)) 8229#define SDE_TC_MASK_ICP (SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ 8230 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ 8231 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ 8232 SDE_TC_HOTPLUG_ICP(PORT_TC1)) 8233#define SDE_DDI_MASK_TGP (SDE_DDI_HOTPLUG_ICP(PORT_C) | \ 8234 SDE_DDI_HOTPLUG_ICP(PORT_B) | \ 8235 SDE_DDI_HOTPLUG_ICP(PORT_A)) 8236#define SDE_TC_MASK_TGP (SDE_TC_HOTPLUG_ICP(PORT_TC6) | \ 8237 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \ 8238 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \ 8239 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \ 8240 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \ 8241 SDE_TC_HOTPLUG_ICP(PORT_TC1)) 8242 8243#define SDEISR _MMIO(0xc4000) 8244#define SDEIMR _MMIO(0xc4004) 8245#define SDEIIR _MMIO(0xc4008) 8246#define SDEIER _MMIO(0xc400c) 8247 8248#define SERR_INT _MMIO(0xc4040) 8249#define SERR_INT_POISON (1 << 31) 8250#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 8251 8252/* digital port hotplug */ 8253#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 8254#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 8255#define BXT_DDIA_HPD_INVERT (1 << 27) 8256#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 8257#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 8258#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 8259#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 8260#define PORTD_HOTPLUG_ENABLE (1 << 20) 8261#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 8262#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 8263#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 8264#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 8265#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 8266#define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 8267#define PORTD_HOTPLUG_NO_DETECT (0 << 16) 8268#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 8269#define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 8270#define PORTC_HOTPLUG_ENABLE (1 << 12) 8271#define BXT_DDIC_HPD_INVERT (1 << 11) 8272#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 8273#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 8274#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 8275#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 8276#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 8277#define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 8278#define PORTC_HOTPLUG_NO_DETECT (0 << 8) 8279#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 8280#define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 8281#define PORTB_HOTPLUG_ENABLE (1 << 4) 8282#define BXT_DDIB_HPD_INVERT (1 << 3) 8283#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 8284#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 8285#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 8286#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 8287#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 8288#define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 8289#define PORTB_HOTPLUG_NO_DETECT (0 << 0) 8290#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 8291#define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 8292#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 8293 BXT_DDIB_HPD_INVERT | \ 8294 BXT_DDIC_HPD_INVERT) 8295 8296#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 8297#define PORTE_HOTPLUG_ENABLE (1 << 4) 8298#define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 8299#define PORTE_HOTPLUG_NO_DETECT (0 << 0) 8300#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 8301#define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 8302 8303/* This register is a reuse of PCH_PORT_HOTPLUG register. The 8304 * functionality covered in PCH_PORT_HOTPLUG is split into 8305 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 8306 */ 8307 8308#define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 8309#define SHOTPLUG_CTL_DDI_HPD_ENABLE(port) (0x8 << (4 * (port))) 8310#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port) (0x3 << (4 * (port))) 8311#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port) (0x0 << (4 * (port))) 8312#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port) (0x1 << (4 * (port))) 8313#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port) (0x2 << (4 * (port))) 8314#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port) (0x3 << (4 * (port))) 8315 8316#define SHOTPLUG_CTL_TC _MMIO(0xc4034) 8317#define ICP_TC_HPD_ENABLE(tc_port) (8 << (tc_port) * 4) 8318 8319#define SHPD_FILTER_CNT _MMIO(0xc4038) 8320#define SHPD_FILTER_CNT_500_ADJ 0x001D9 8321 8322/* Icelake DSC Rate Control Range Parameter Registers */ 8323#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 8324#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 8325#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 8326#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 8327#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 8328#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 8329#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 8330#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 8331#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 8332#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 8333#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 8334#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 8335#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8336 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 8337 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 8338#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8339 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 8340 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 8341#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8342 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 8343 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 8344#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8345 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 8346 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 8347#define RC_BPG_OFFSET_SHIFT 10 8348#define RC_MAX_QP_SHIFT 5 8349#define RC_MIN_QP_SHIFT 0 8350 8351#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 8352#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 8353#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 8354#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 8355#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 8356#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 8357#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 8358#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 8359#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 8360#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 8361#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 8362#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 8363#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8364 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 8365 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 8366#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8367 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 8368 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 8369#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8370 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 8371 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 8372#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8373 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 8374 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 8375 8376#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 8377#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 8378#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 8379#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 8380#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 8381#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 8382#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 8383#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 8384#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 8385#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 8386#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 8387#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 8388#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8389 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 8390 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 8391#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8392 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8393 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 8394#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8395 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 8396 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 8397#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8398 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 8399 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 8400 8401#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 8402#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 8403#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 8404#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 8405#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 8406#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 8407#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 8408#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 8409#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 8410#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 8411#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 8412#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 8413#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8414 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 8415 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 8416#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8417 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8418 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 8419#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8420 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 8421 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 8422#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8423 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 8424 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 8425 8426#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) 8427#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) 8428 8429#define ICP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ 8430 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) 8431#define ICP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC4) | \ 8432 ICP_TC_HPD_ENABLE(PORT_TC3) | \ 8433 ICP_TC_HPD_ENABLE(PORT_TC2) | \ 8434 ICP_TC_HPD_ENABLE(PORT_TC1)) 8435#define TGP_DDI_HPD_ENABLE_MASK (SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \ 8436 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \ 8437 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A)) 8438#define TGP_TC_HPD_ENABLE_MASK (ICP_TC_HPD_ENABLE(PORT_TC6) | \ 8439 ICP_TC_HPD_ENABLE(PORT_TC5) | \ 8440 ICP_TC_HPD_ENABLE_MASK) 8441 8442#define _PCH_DPLL_A 0xc6014 8443#define _PCH_DPLL_B 0xc6018 8444#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 8445 8446#define _PCH_FPA0 0xc6040 8447#define FP_CB_TUNE (0x3 << 22) 8448#define _PCH_FPA1 0xc6044 8449#define _PCH_FPB0 0xc6048 8450#define _PCH_FPB1 0xc604c 8451#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 8452#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 8453 8454#define PCH_DPLL_TEST _MMIO(0xc606c) 8455 8456#define PCH_DREF_CONTROL _MMIO(0xC6200) 8457#define DREF_CONTROL_MASK 0x7fc3 8458#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 8459#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 8460#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 8461#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 8462#define DREF_SSC_SOURCE_DISABLE (0 << 11) 8463#define DREF_SSC_SOURCE_ENABLE (2 << 11) 8464#define DREF_SSC_SOURCE_MASK (3 << 11) 8465#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 8466#define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 8467#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 8468#define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 8469#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 8470#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 8471#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 8472#define DREF_SSC4_DOWNSPREAD (0 << 6) 8473#define DREF_SSC4_CENTERSPREAD (1 << 6) 8474#define DREF_SSC1_DISABLE (0 << 1) 8475#define DREF_SSC1_ENABLE (1 << 1) 8476#define DREF_SSC4_DISABLE (0) 8477#define DREF_SSC4_ENABLE (1) 8478 8479#define PCH_RAWCLK_FREQ _MMIO(0xc6204) 8480#define FDL_TP1_TIMER_SHIFT 12 8481#define FDL_TP1_TIMER_MASK (3 << 12) 8482#define FDL_TP2_TIMER_SHIFT 10 8483#define FDL_TP2_TIMER_MASK (3 << 10) 8484#define RAWCLK_FREQ_MASK 0x3ff 8485#define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 8486#define CNP_RAWCLK_DIV(div) ((div) << 16) 8487#define CNP_RAWCLK_FRAC_MASK (0xf << 26) 8488#define CNP_RAWCLK_DEN(den) ((den) << 26) 8489#define ICP_RAWCLK_NUM(num) ((num) << 11) 8490 8491#define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 8492 8493#define PCH_SSC4_PARMS _MMIO(0xc6210) 8494#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 8495 8496#define PCH_DPLL_SEL _MMIO(0xc7000) 8497#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 8498#define TRANS_DPLLA_SEL(pipe) 0 8499#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 8500 8501/* transcoder */ 8502 8503#define _PCH_TRANS_HTOTAL_A 0xe0000 8504#define TRANS_HTOTAL_SHIFT 16 8505#define TRANS_HACTIVE_SHIFT 0 8506#define _PCH_TRANS_HBLANK_A 0xe0004 8507#define TRANS_HBLANK_END_SHIFT 16 8508#define TRANS_HBLANK_START_SHIFT 0 8509#define _PCH_TRANS_HSYNC_A 0xe0008 8510#define TRANS_HSYNC_END_SHIFT 16 8511#define TRANS_HSYNC_START_SHIFT 0 8512#define _PCH_TRANS_VTOTAL_A 0xe000c 8513#define TRANS_VTOTAL_SHIFT 16 8514#define TRANS_VACTIVE_SHIFT 0 8515#define _PCH_TRANS_VBLANK_A 0xe0010 8516#define TRANS_VBLANK_END_SHIFT 16 8517#define TRANS_VBLANK_START_SHIFT 0 8518#define _PCH_TRANS_VSYNC_A 0xe0014 8519#define TRANS_VSYNC_END_SHIFT 16 8520#define TRANS_VSYNC_START_SHIFT 0 8521#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 8522 8523#define _PCH_TRANSA_DATA_M1 0xe0030 8524#define _PCH_TRANSA_DATA_N1 0xe0034 8525#define _PCH_TRANSA_DATA_M2 0xe0038 8526#define _PCH_TRANSA_DATA_N2 0xe003c 8527#define _PCH_TRANSA_LINK_M1 0xe0040 8528#define _PCH_TRANSA_LINK_N1 0xe0044 8529#define _PCH_TRANSA_LINK_M2 0xe0048 8530#define _PCH_TRANSA_LINK_N2 0xe004c 8531 8532/* Per-transcoder DIP controls (PCH) */ 8533#define _VIDEO_DIP_CTL_A 0xe0200 8534#define _VIDEO_DIP_DATA_A 0xe0208 8535#define _VIDEO_DIP_GCP_A 0xe0210 8536#define GCP_COLOR_INDICATION (1 << 2) 8537#define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 8538#define GCP_AV_MUTE (1 << 0) 8539 8540#define _VIDEO_DIP_CTL_B 0xe1200 8541#define _VIDEO_DIP_DATA_B 0xe1208 8542#define _VIDEO_DIP_GCP_B 0xe1210 8543 8544#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 8545#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 8546#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 8547 8548/* Per-transcoder DIP controls (VLV) */ 8549#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 8550#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 8551#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 8552 8553#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 8554#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 8555#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 8556 8557#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 8558#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 8559#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 8560 8561#define VLV_TVIDEO_DIP_CTL(pipe) \ 8562 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 8563 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 8564#define VLV_TVIDEO_DIP_DATA(pipe) \ 8565 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 8566 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 8567#define VLV_TVIDEO_DIP_GCP(pipe) \ 8568 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 8569 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 8570 8571/* Haswell DIP controls */ 8572 8573#define _HSW_VIDEO_DIP_CTL_A 0x60200 8574#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 8575#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 8576#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 8577#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 8578#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 8579#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 8580#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 8581#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 8582#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 8583#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 8584#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 8585#define _HSW_VIDEO_DIP_GCP_A 0x60210 8586 8587#define _HSW_VIDEO_DIP_CTL_B 0x61200 8588#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 8589#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 8590#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 8591#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 8592#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 8593#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 8594#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 8595#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 8596#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 8597#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 8598#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 8599#define _HSW_VIDEO_DIP_GCP_B 0x61210 8600 8601/* Icelake PPS_DATA and _ECC DIP Registers. 8602 * These are available for transcoders B,C and eDP. 8603 * Adding the _A so as to reuse the _MMIO_TRANS2 8604 * definition, with which it offsets to the right location. 8605 */ 8606 8607#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 8608#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 8609#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 8610#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 8611 8612#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 8613#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 8614#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 8615#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 8616#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 8617#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 8618#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 8619#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 8620#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 8621#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 8622 8623#define _HSW_STEREO_3D_CTL_A 0x70020 8624#define S3D_ENABLE (1 << 31) 8625#define _HSW_STEREO_3D_CTL_B 0x71020 8626 8627#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 8628 8629#define _PCH_TRANS_HTOTAL_B 0xe1000 8630#define _PCH_TRANS_HBLANK_B 0xe1004 8631#define _PCH_TRANS_HSYNC_B 0xe1008 8632#define _PCH_TRANS_VTOTAL_B 0xe100c 8633#define _PCH_TRANS_VBLANK_B 0xe1010 8634#define _PCH_TRANS_VSYNC_B 0xe1014 8635#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 8636 8637#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 8638#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 8639#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 8640#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 8641#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 8642#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 8643#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 8644 8645#define _PCH_TRANSB_DATA_M1 0xe1030 8646#define _PCH_TRANSB_DATA_N1 0xe1034 8647#define _PCH_TRANSB_DATA_M2 0xe1038 8648#define _PCH_TRANSB_DATA_N2 0xe103c 8649#define _PCH_TRANSB_LINK_M1 0xe1040 8650#define _PCH_TRANSB_LINK_N1 0xe1044 8651#define _PCH_TRANSB_LINK_M2 0xe1048 8652#define _PCH_TRANSB_LINK_N2 0xe104c 8653 8654#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 8655#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 8656#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 8657#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 8658#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 8659#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 8660#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 8661#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 8662 8663#define _PCH_TRANSACONF 0xf0008 8664#define _PCH_TRANSBCONF 0xf1008 8665#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 8666#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 8667#define TRANS_DISABLE (0 << 31) 8668#define TRANS_ENABLE (1 << 31) 8669#define TRANS_STATE_MASK (1 << 30) 8670#define TRANS_STATE_DISABLE (0 << 30) 8671#define TRANS_STATE_ENABLE (1 << 30) 8672#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */ 8673#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */ 8674#define TRANS_INTERLACE_MASK (7 << 21) 8675#define TRANS_PROGRESSIVE (0 << 21) 8676#define TRANS_INTERLACED (3 << 21) 8677#define TRANS_LEGACY_INTERLACED_ILK (2 << 21) 8678#define TRANS_8BPC (0 << 5) 8679#define TRANS_10BPC (1 << 5) 8680#define TRANS_6BPC (2 << 5) 8681#define TRANS_12BPC (3 << 5) 8682 8683#define _TRANSA_CHICKEN1 0xf0060 8684#define _TRANSB_CHICKEN1 0xf1060 8685#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 8686#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 8687#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 8688#define _TRANSA_CHICKEN2 0xf0064 8689#define _TRANSB_CHICKEN2 0xf1064 8690#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 8691#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 8692#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 8693#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 8694#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 8695#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 8696#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 8697 8698#define SOUTH_CHICKEN1 _MMIO(0xc2000) 8699#define FDIA_PHASE_SYNC_SHIFT_OVR 19 8700#define FDIA_PHASE_SYNC_SHIFT_EN 18 8701#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 8702#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 8703#define FDI_BC_BIFURCATION_SELECT (1 << 12) 8704#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 8705#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 8706#define SBCLK_RUN_REFCLK_DIS (1 << 7) 8707#define SPT_PWM_GRANULARITY (1 << 0) 8708#define SOUTH_CHICKEN2 _MMIO(0xc2004) 8709#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 8710#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 8711#define LPT_PWM_GRANULARITY (1 << 5) 8712#define DPLS_EDP_PPS_FIX_DIS (1 << 0) 8713 8714#define _FDI_RXA_CHICKEN 0xc200c 8715#define _FDI_RXB_CHICKEN 0xc2010 8716#define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 8717#define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 8718#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 8719 8720#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 8721#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 8722#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 8723#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 8724#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 8725#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 8726#define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 8727#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 8728 8729/* CPU: FDI_TX */ 8730#define _FDI_TXA_CTL 0x60100 8731#define _FDI_TXB_CTL 0x61100 8732#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 8733#define FDI_TX_DISABLE (0 << 31) 8734#define FDI_TX_ENABLE (1 << 31) 8735#define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 8736#define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 8737#define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 8738#define FDI_LINK_TRAIN_NONE (3 << 28) 8739#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 8740#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 8741#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 8742#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 8743#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 8744#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 8745#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 8746#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 8747/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 8748 SNB has different settings. */ 8749/* SNB A-stepping */ 8750#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8751#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8752#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8753#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8754/* SNB B-stepping */ 8755#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 8756#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 8757#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 8758#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 8759#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 8760#define FDI_DP_PORT_WIDTH_SHIFT 19 8761#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 8762#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 8763#define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 8764/* Ironlake: hardwired to 1 */ 8765#define FDI_TX_PLL_ENABLE (1 << 14) 8766 8767/* Ivybridge has different bits for lolz */ 8768#define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 8769#define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 8770#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 8771#define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 8772 8773/* both Tx and Rx */ 8774#define FDI_COMPOSITE_SYNC (1 << 11) 8775#define FDI_LINK_TRAIN_AUTO (1 << 10) 8776#define FDI_SCRAMBLING_ENABLE (0 << 7) 8777#define FDI_SCRAMBLING_DISABLE (1 << 7) 8778 8779/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 8780#define _FDI_RXA_CTL 0xf000c 8781#define _FDI_RXB_CTL 0xf100c 8782#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 8783#define FDI_RX_ENABLE (1 << 31) 8784/* train, dp width same as FDI_TX */ 8785#define FDI_FS_ERRC_ENABLE (1 << 27) 8786#define FDI_FE_ERRC_ENABLE (1 << 26) 8787#define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 8788#define FDI_8BPC (0 << 16) 8789#define FDI_10BPC (1 << 16) 8790#define FDI_6BPC (2 << 16) 8791#define FDI_12BPC (3 << 16) 8792#define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 8793#define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 8794#define FDI_RX_PLL_ENABLE (1 << 13) 8795#define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 8796#define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 8797#define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 8798#define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 8799#define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 8800#define FDI_PCDCLK (1 << 4) 8801/* CPT */ 8802#define FDI_AUTO_TRAINING (1 << 10) 8803#define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 8804#define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 8805#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 8806#define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 8807#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 8808 8809#define _FDI_RXA_MISC 0xf0010 8810#define _FDI_RXB_MISC 0xf1010 8811#define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 8812#define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 8813#define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 8814#define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 8815#define FDI_RX_TP1_TO_TP2_48 (2 << 20) 8816#define FDI_RX_TP1_TO_TP2_64 (3 << 20) 8817#define FDI_RX_FDI_DELAY_90 (0x90 << 0) 8818#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 8819 8820#define _FDI_RXA_TUSIZE1 0xf0030 8821#define _FDI_RXA_TUSIZE2 0xf0038 8822#define _FDI_RXB_TUSIZE1 0xf1030 8823#define _FDI_RXB_TUSIZE2 0xf1038 8824#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 8825#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 8826 8827/* FDI_RX interrupt register format */ 8828#define FDI_RX_INTER_LANE_ALIGN (1 << 10) 8829#define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 8830#define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 8831#define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 8832#define FDI_RX_FS_CODE_ERR (1 << 6) 8833#define FDI_RX_FE_CODE_ERR (1 << 5) 8834#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 8835#define FDI_RX_HDCP_LINK_FAIL (1 << 3) 8836#define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 8837#define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 8838#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 8839 8840#define _FDI_RXA_IIR 0xf0014 8841#define _FDI_RXA_IMR 0xf0018 8842#define _FDI_RXB_IIR 0xf1014 8843#define _FDI_RXB_IMR 0xf1018 8844#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 8845#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 8846 8847#define FDI_PLL_CTL_1 _MMIO(0xfe000) 8848#define FDI_PLL_CTL_2 _MMIO(0xfe004) 8849 8850#define PCH_LVDS _MMIO(0xe1180) 8851#define LVDS_DETECTED (1 << 1) 8852 8853#define _PCH_DP_B 0xe4100 8854#define PCH_DP_B _MMIO(_PCH_DP_B) 8855#define _PCH_DPB_AUX_CH_CTL 0xe4110 8856#define _PCH_DPB_AUX_CH_DATA1 0xe4114 8857#define _PCH_DPB_AUX_CH_DATA2 0xe4118 8858#define _PCH_DPB_AUX_CH_DATA3 0xe411c 8859#define _PCH_DPB_AUX_CH_DATA4 0xe4120 8860#define _PCH_DPB_AUX_CH_DATA5 0xe4124 8861 8862#define _PCH_DP_C 0xe4200 8863#define PCH_DP_C _MMIO(_PCH_DP_C) 8864#define _PCH_DPC_AUX_CH_CTL 0xe4210 8865#define _PCH_DPC_AUX_CH_DATA1 0xe4214 8866#define _PCH_DPC_AUX_CH_DATA2 0xe4218 8867#define _PCH_DPC_AUX_CH_DATA3 0xe421c 8868#define _PCH_DPC_AUX_CH_DATA4 0xe4220 8869#define _PCH_DPC_AUX_CH_DATA5 0xe4224 8870 8871#define _PCH_DP_D 0xe4300 8872#define PCH_DP_D _MMIO(_PCH_DP_D) 8873#define _PCH_DPD_AUX_CH_CTL 0xe4310 8874#define _PCH_DPD_AUX_CH_DATA1 0xe4314 8875#define _PCH_DPD_AUX_CH_DATA2 0xe4318 8876#define _PCH_DPD_AUX_CH_DATA3 0xe431c 8877#define _PCH_DPD_AUX_CH_DATA4 0xe4320 8878#define _PCH_DPD_AUX_CH_DATA5 0xe4324 8879 8880#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 8881#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 8882 8883/* CPT */ 8884#define _TRANS_DP_CTL_A 0xe0300 8885#define _TRANS_DP_CTL_B 0xe1300 8886#define _TRANS_DP_CTL_C 0xe2300 8887#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 8888#define TRANS_DP_OUTPUT_ENABLE (1 << 31) 8889#define TRANS_DP_PORT_SEL_MASK (3 << 29) 8890#define TRANS_DP_PORT_SEL_NONE (3 << 29) 8891#define TRANS_DP_PORT_SEL(port) (((port) - PORT_B) << 29) 8892#define TRANS_DP_AUDIO_ONLY (1 << 26) 8893#define TRANS_DP_ENH_FRAMING (1 << 18) 8894#define TRANS_DP_8BPC (0 << 9) 8895#define TRANS_DP_10BPC (1 << 9) 8896#define TRANS_DP_6BPC (2 << 9) 8897#define TRANS_DP_12BPC (3 << 9) 8898#define TRANS_DP_BPC_MASK (3 << 9) 8899#define TRANS_DP_VSYNC_ACTIVE_HIGH (1 << 4) 8900#define TRANS_DP_VSYNC_ACTIVE_LOW 0 8901#define TRANS_DP_HSYNC_ACTIVE_HIGH (1 << 3) 8902#define TRANS_DP_HSYNC_ACTIVE_LOW 0 8903#define TRANS_DP_SYNC_MASK (3 << 3) 8904 8905/* SNB eDP training params */ 8906/* SNB A-stepping */ 8907#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 8908#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 8909#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 8910#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 8911/* SNB B-stepping */ 8912#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 8913#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 8914#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 8915#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 8916#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 8917#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 8918 8919/* IVB */ 8920#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 8921#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 8922#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 8923#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 8924#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 8925#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 8926#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 8927 8928/* legacy values */ 8929#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 8930#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 8931#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 8932#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 8933#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 8934 8935#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 8936 8937#define VLV_PMWGICZ _MMIO(0x1300a4) 8938 8939#define RC6_LOCATION _MMIO(0xD40) 8940#define RC6_CTX_IN_DRAM (1 << 0) 8941#define RC6_CTX_BASE _MMIO(0xD48) 8942#define RC6_CTX_BASE_MASK 0xFFFFFFF0 8943#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054) 8944#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054) 8945#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054) 8946#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054) 8947#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054) 8948#define IDLE_TIME_MASK 0xFFFFF 8949#define FORCEWAKE _MMIO(0xA18C) 8950#define FORCEWAKE_VLV _MMIO(0x1300b0) 8951#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 8952#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 8953#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 8954#define FORCEWAKE_ACK_HSW _MMIO(0x130044) 8955#define FORCEWAKE_ACK _MMIO(0x130090) 8956#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 8957#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 8958#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 8959#define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 8960 8961#define VLV_GTLC_PW_STATUS _MMIO(0x130094) 8962#define VLV_GTLC_ALLOWWAKEACK (1 << 0) 8963#define VLV_GTLC_ALLOWWAKEERR (1 << 1) 8964#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 8965#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 8966#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 8967#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 8968#define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 8969#define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 8970#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 8971#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188) 8972#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88) 8973#define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0x0D50 + (n) * 4) 8974#define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0x0D70 + (n) * 4) 8975#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84) 8976#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044) 8977#define FORCEWAKE_KERNEL BIT(0) 8978#define FORCEWAKE_USER BIT(1) 8979#define FORCEWAKE_KERNEL_FALLBACK BIT(15) 8980#define FORCEWAKE_MT_ACK _MMIO(0x130040) 8981#define ECOBUS _MMIO(0xa180) 8982#define FORCEWAKE_MT_ENABLE (1 << 5) 8983#define VLV_SPAREG2H _MMIO(0xA194) 8984#define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xA2A0) 8985#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 8986#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 8987 8988#define GTFIFODBG _MMIO(0x120000) 8989#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 8990#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 8991#define GT_FIFO_SBDROPERR (1 << 6) 8992#define GT_FIFO_BLOBDROPERR (1 << 5) 8993#define GT_FIFO_SB_READ_ABORTERR (1 << 4) 8994#define GT_FIFO_DROPERR (1 << 3) 8995#define GT_FIFO_OVFERR (1 << 2) 8996#define GT_FIFO_IAWRERR (1 << 1) 8997#define GT_FIFO_IARDERR (1 << 0) 8998 8999#define GTFIFOCTL _MMIO(0x120008) 9000#define GT_FIFO_FREE_ENTRIES_MASK 0x7f 9001#define GT_FIFO_NUM_RESERVED_ENTRIES 20 9002#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 9003#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 9004 9005#define HSW_IDICR _MMIO(0x9008) 9006#define IDIHASHMSK(x) (((x) & 0x3f) << 16) 9007#define HSW_EDRAM_CAP _MMIO(0x120010) 9008#define EDRAM_ENABLED 0x1 9009#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 9010#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 9011#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 9012 9013#define GEN6_UCGCTL1 _MMIO(0x9400) 9014# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 9015# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 9016# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 9017# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 9018 9019#define GEN6_UCGCTL2 _MMIO(0x9404) 9020# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 9021# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 9022# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 9023# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 9024# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 9025# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 9026 9027#define GEN6_UCGCTL3 _MMIO(0x9408) 9028# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 9029 9030#define GEN7_UCGCTL4 _MMIO(0x940c) 9031#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 9032#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 9033 9034#define GEN6_RCGCTL1 _MMIO(0x9410) 9035#define GEN6_RCGCTL2 _MMIO(0x9414) 9036#define GEN6_RSTCTL _MMIO(0x9420) 9037 9038#define GEN8_UCGCTL6 _MMIO(0x9430) 9039#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 9040#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 9041#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 9042 9043#define GEN6_GFXPAUSE _MMIO(0xA000) 9044#define GEN6_RPNSWREQ _MMIO(0xA008) 9045#define GEN6_TURBO_DISABLE (1 << 31) 9046#define GEN6_FREQUENCY(x) ((x) << 25) 9047#define HSW_FREQUENCY(x) ((x) << 24) 9048#define GEN9_FREQUENCY(x) ((x) << 23) 9049#define GEN6_OFFSET(x) ((x) << 19) 9050#define GEN6_AGGRESSIVE_TURBO (0 << 15) 9051#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) 9052#define GEN6_RC_CONTROL _MMIO(0xA090) 9053#define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 9054#define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 9055#define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 9056#define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 9057#define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 9058#define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 9059#define GEN7_RC_CTL_TO_MODE (1 << 28) 9060#define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 9061#define GEN6_RC_CTL_HW_ENABLE (1 << 31) 9062#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010) 9063#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014) 9064#define GEN6_RPSTAT1 _MMIO(0xA01C) 9065#define GEN6_CAGF_SHIFT 8 9066#define HSW_CAGF_SHIFT 7 9067#define GEN9_CAGF_SHIFT 23 9068#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 9069#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 9070#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT) 9071#define GEN6_RP_CONTROL _MMIO(0xA024) 9072#define GEN6_RP_MEDIA_TURBO (1 << 11) 9073#define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 9074#define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 9075#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 9076#define GEN6_RP_MEDIA_HW_MODE (1 << 9) 9077#define GEN6_RP_MEDIA_SW_MODE (0 << 9) 9078#define GEN6_RP_MEDIA_IS_GFX (1 << 8) 9079#define GEN6_RP_ENABLE (1 << 7) 9080#define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 9081#define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 9082#define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 9083#define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 9084#define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 9085#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) 9086#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) 9087#define GEN6_RP_CUR_UP_EI _MMIO(0xA050) 9088#define GEN6_RP_EI_MASK 0xffffff 9089#define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 9090#define GEN6_RP_CUR_UP _MMIO(0xA054) 9091#define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 9092#define GEN6_RP_PREV_UP _MMIO(0xA058) 9093#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C) 9094#define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 9095#define GEN6_RP_CUR_DOWN _MMIO(0xA060) 9096#define GEN6_RP_PREV_DOWN _MMIO(0xA064) 9097#define GEN6_RP_UP_EI _MMIO(0xA068) 9098#define GEN6_RP_DOWN_EI _MMIO(0xA06C) 9099#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070) 9100#define GEN6_RPDEUHWTC _MMIO(0xA080) 9101#define GEN6_RPDEUC _MMIO(0xA084) 9102#define GEN6_RPDEUCSW _MMIO(0xA088) 9103#define GEN6_RC_STATE _MMIO(0xA094) 9104#define RC_SW_TARGET_STATE_SHIFT 16 9105#define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 9106#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098) 9107#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C) 9108#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0) 9109#define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xA0A0) 9110#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8) 9111#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC) 9112#define GEN6_RC_SLEEP _MMIO(0xA0B0) 9113#define GEN6_RCUBMABDTMR _MMIO(0xA0B0) 9114#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4) 9115#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8) 9116#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC) 9117#define VLV_RCEDATA _MMIO(0xA0BC) 9118#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0) 9119#define GEN6_PMINTRMSK _MMIO(0xA168) 9120#define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 9121#define ARAT_EXPIRED_INTRMSK (1 << 9) 9122#define GEN8_MISC_CTRL0 _MMIO(0xA180) 9123#define VLV_PWRDWNUPCTL _MMIO(0xA294) 9124#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4) 9125#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8) 9126#define GEN9_PG_ENABLE _MMIO(0xA210) 9127#define GEN9_RENDER_PG_ENABLE REG_BIT(0) 9128#define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 9129#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 9130#define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 9131#define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 9132#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248) 9133#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250) 9134#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C) 9135 9136#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 9137#define PIXEL_OVERLAP_CNT_MASK (3 << 30) 9138#define PIXEL_OVERLAP_CNT_SHIFT 30 9139 9140#define GEN6_PMISR _MMIO(0x44020) 9141#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 9142#define GEN6_PMIIR _MMIO(0x44028) 9143#define GEN6_PMIER _MMIO(0x4402C) 9144#define GEN6_PM_MBOX_EVENT (1 << 25) 9145#define GEN6_PM_THERMAL_EVENT (1 << 24) 9146 9147/* 9148 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 9149 * registers. Shifting is handled on accessing the imr and ier. 9150 */ 9151#define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 9152#define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 9153#define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 9154#define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 9155#define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 9156#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 9157 GEN6_PM_RP_UP_THRESHOLD | \ 9158 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 9159 GEN6_PM_RP_DOWN_THRESHOLD | \ 9160 GEN6_PM_RP_DOWN_TIMEOUT) 9161 9162#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4) 9163#define GEN7_GT_SCRATCH_REG_NUM 8 9164 9165#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 9166#define VLV_GFX_CLK_STATUS_BIT (1 << 3) 9167#define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 9168 9169#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 9170#define VLV_COUNTER_CONTROL _MMIO(0x138104) 9171#define VLV_COUNT_RANGE_HIGH (1 << 15) 9172#define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 9173#define VLV_RENDER_RC0_COUNT_EN (1 << 4) 9174#define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 9175#define VLV_RENDER_RC6_COUNT_EN (1 << 0) 9176#define GEN6_GT_GFX_RC6 _MMIO(0x138108) 9177#define VLV_GT_RENDER_RC6 _MMIO(0x138108) 9178#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C) 9179 9180#define GEN6_GT_GFX_RC6p _MMIO(0x13810C) 9181#define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 9182#define VLV_RENDER_C0_COUNT _MMIO(0x138118) 9183#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) 9184 9185#define GEN6_PCODE_MAILBOX _MMIO(0x138124) 9186#define GEN6_PCODE_READY (1 << 31) 9187#define GEN6_PCODE_ERROR_MASK 0xFF 9188#define GEN6_PCODE_SUCCESS 0x0 9189#define GEN6_PCODE_ILLEGAL_CMD 0x1 9190#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 9191#define GEN6_PCODE_TIMEOUT 0x3 9192#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 9193#define GEN7_PCODE_TIMEOUT 0x2 9194#define GEN7_PCODE_ILLEGAL_DATA 0x3 9195#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 9196#define GEN11_PCODE_LOCKED 0x6 9197#define GEN11_PCODE_REJECTED 0x11 9198#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 9199#define GEN6_PCODE_WRITE_RC6VIDS 0x4 9200#define GEN6_PCODE_READ_RC6VIDS 0x5 9201#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 9202#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 9203#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 9204#define GEN9_PCODE_READ_MEM_LATENCY 0x6 9205#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 9206#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 9207#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 9208#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 9209#define SKL_PCODE_LOAD_HDCP_KEYS 0x5 9210#define SKL_PCODE_CDCLK_CONTROL 0x7 9211#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 9212#define SKL_CDCLK_READY_FOR_CHANGE 0x1 9213#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 9214#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 9215#define GEN6_READ_OC_PARAMS 0xc 9216#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 9217#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 9218#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 9219#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 9220#define ICL_PCODE_POINTS_RESTRICTED 0x0 9221#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1 9222#define GEN6_PCODE_READ_D_COMP 0x10 9223#define GEN6_PCODE_WRITE_D_COMP 0x11 9224#define ICL_PCODE_EXIT_TCCOLD 0x12 9225#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 9226#define DISPLAY_IPS_CONTROL 0x19 9227#define TGL_PCODE_TCCOLD 0x26 9228#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 9229#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 9230#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 9231 /* See also IPS_CTL */ 9232#define IPS_PCODE_CONTROL (1 << 30) 9233#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 9234#define GEN9_PCODE_SAGV_CONTROL 0x21 9235#define GEN9_SAGV_DISABLE 0x0 9236#define GEN9_SAGV_IS_DISABLED 0x1 9237#define GEN9_SAGV_ENABLE 0x3 9238#define DG1_PCODE_STATUS 0x7E 9239#define DG1_UNCORE_GET_INIT_STATUS 0x0 9240#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 9241#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 9242#define GEN6_PCODE_DATA _MMIO(0x138128) 9243#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 9244#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 9245#define GEN6_PCODE_DATA1 _MMIO(0x13812C) 9246 9247#define GEN6_GT_CORE_STATUS _MMIO(0x138060) 9248#define GEN6_CORE_CPD_STATE_MASK (7 << 4) 9249#define GEN6_RCn_MASK 7 9250#define GEN6_RC0 0 9251#define GEN6_RC3 2 9252#define GEN6_RC6 3 9253#define GEN6_RC7 4 9254 9255#define GEN8_GT_SLICE_INFO _MMIO(0x138064) 9256#define GEN8_LSLICESTAT_MASK 0x7 9257 9258#define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 9259#define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 9260#define CHV_SS_PG_ENABLE (1 << 1) 9261#define CHV_EU08_PG_ENABLE (1 << 9) 9262#define CHV_EU19_PG_ENABLE (1 << 17) 9263#define CHV_EU210_PG_ENABLE (1 << 25) 9264 9265#define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 9266#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 9267#define CHV_EU311_PG_ENABLE (1 << 1) 9268 9269#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 9270#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 9271 ((slice) % 3) * 0x4) 9272#define GEN9_PGCTL_SLICE_ACK (1 << 0) 9273#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 9274#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 9275 9276#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 9277#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 9278 ((slice) % 3) * 0x8) 9279#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 9280#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 9281 ((slice) % 3) * 0x8) 9282#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 9283#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 9284#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 9285#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 9286#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 9287#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 9288#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 9289#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 9290 9291#define GEN7_MISCCPCTL _MMIO(0x9424) 9292#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) 9293#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 9294#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 9295#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 9296 9297#define GEN8_GARBCNTL _MMIO(0xB004) 9298#define GEN9_GAPS_TSV_CREDIT_DISABLE (1 << 7) 9299#define GEN11_ARBITRATION_PRIO_ORDER_MASK (0x3f << 22) 9300#define GEN11_HASH_CTRL_EXCL_MASK (0x7f << 0) 9301#define GEN11_HASH_CTRL_EXCL_BIT0 (1 << 0) 9302 9303#define GEN11_GLBLINVL _MMIO(0xB404) 9304#define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 9305#define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 9306 9307#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550) 9308#define DFR_DISABLE (1 << 9) 9309 9310#define GEN11_GACB_PERF_CTRL _MMIO(0x4B80) 9311#define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 9312#define GEN11_HASH_CTRL_BIT0 (1 << 0) 9313#define GEN11_HASH_CTRL_BIT4 (1 << 12) 9314 9315#define GEN11_LSN_UNSLCVC _MMIO(0xB43C) 9316#define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 9317#define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 9318 9319#define GEN10_SAMPLER_MODE _MMIO(0xE18C) 9320#define ENABLE_SMALLPL REG_BIT(15) 9321#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 9322 9323/* IVYBRIDGE DPF */ 9324#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 9325#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 9326#define GEN7_PARITY_ERROR_VALID (1 << 13) 9327#define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 9328#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 9329#define GEN7_PARITY_ERROR_ROW(reg) \ 9330 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 9331#define GEN7_PARITY_ERROR_BANK(reg) \ 9332 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 9333#define GEN7_PARITY_ERROR_SUBBANK(reg) \ 9334 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 9335#define GEN7_L3CDERRST1_ENABLE (1 << 7) 9336 9337#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4) 9338#define GEN7_L3LOG_SIZE 0x80 9339 9340#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 9341#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100) 9342#define GEN7_MAX_PS_THREAD_DEP (8 << 12) 9343#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 9344#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 9345#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 9346 9347#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188) 9348#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 9349#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 9350 9351#define GEN8_ROW_CHICKEN _MMIO(0xe4f0) 9352#define FLOW_CONTROL_ENABLE (1 << 15) 9353#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1 << 8) 9354#define STALL_DOP_GATING_DISABLE (1 << 5) 9355#define THROTTLE_12_5 (7 << 2) 9356#define DISABLE_EARLY_EOT (1 << 1) 9357 9358#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 9359#define GEN12_DISABLE_EARLY_READ REG_BIT(14) 9360#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 9361 9362#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 9363#define DOP_CLOCK_GATING_DISABLE (1 << 0) 9364#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 9365#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 9366 9367#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c) 9368#define GEN12_DISABLE_TDL_PUSH REG_BIT(9) 9369#define GEN11_DIS_PICK_2ND_EU REG_BIT(7) 9370 9371#define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 9372#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 9373 9374#define HALF_SLICE_CHICKEN2 _MMIO(0xe180) 9375#define GEN8_ST_PO_DISABLE (1 << 13) 9376 9377#define HALF_SLICE_CHICKEN3 _MMIO(0xe184) 9378#define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 9379#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 9380#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 9381#define CNL_FAST_ANISO_L1_BANKING_FIX (1 << 4) 9382#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 9383 9384#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) 9385#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR (1 << 8) 9386#define GEN9_ENABLE_YV12_BUGFIX (1 << 4) 9387#define GEN9_ENABLE_GPGPU_PREEMPTION (1 << 2) 9388 9389/* Audio */ 9390#define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 9391#define INTEL_AUDIO_DEVCL 0x808629FB 9392#define INTEL_AUDIO_DEVBLC 0x80862801 9393#define INTEL_AUDIO_DEVCTG 0x80862802 9394 9395#define G4X_AUD_CNTL_ST _MMIO(0x620B4) 9396#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 9397#define G4X_ELDV_DEVCTG (1 << 14) 9398#define G4X_ELD_ADDR_MASK (0xf << 5) 9399#define G4X_ELD_ACK (1 << 4) 9400#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 9401 9402#define _IBX_HDMIW_HDMIEDID_A 0xE2050 9403#define _IBX_HDMIW_HDMIEDID_B 0xE2150 9404#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 9405 _IBX_HDMIW_HDMIEDID_B) 9406#define _IBX_AUD_CNTL_ST_A 0xE20B4 9407#define _IBX_AUD_CNTL_ST_B 0xE21B4 9408#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 9409 _IBX_AUD_CNTL_ST_B) 9410#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 9411#define IBX_ELD_ADDRESS_MASK (0x1f << 5) 9412#define IBX_ELD_ACK (1 << 4) 9413#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 9414#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 9415#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 9416 9417#define _CPT_HDMIW_HDMIEDID_A 0xE5050 9418#define _CPT_HDMIW_HDMIEDID_B 0xE5150 9419#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 9420#define _CPT_AUD_CNTL_ST_A 0xE50B4 9421#define _CPT_AUD_CNTL_ST_B 0xE51B4 9422#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 9423#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 9424 9425#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 9426#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 9427#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 9428#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 9429#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 9430#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 9431#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 9432 9433/* These are the 4 32-bit write offset registers for each stream 9434 * output buffer. It determines the offset from the 9435 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 9436 */ 9437#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 9438 9439#define _IBX_AUD_CONFIG_A 0xe2000 9440#define _IBX_AUD_CONFIG_B 0xe2100 9441#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 9442#define _CPT_AUD_CONFIG_A 0xe5000 9443#define _CPT_AUD_CONFIG_B 0xe5100 9444#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 9445#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 9446#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 9447#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 9448 9449#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 9450#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 9451#define AUD_CONFIG_UPPER_N_SHIFT 20 9452#define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 9453#define AUD_CONFIG_LOWER_N_SHIFT 4 9454#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 9455#define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 9456#define AUD_CONFIG_N(n) \ 9457 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 9458 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 9459#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 9460#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 9461#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 9462#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 9463#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 9464#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 9465#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 9466#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 9467#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 9468#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 9469#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 9470#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 9471#define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) 9472#define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) 9473#define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) 9474#define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) 9475#define AUD_CONFIG_DISABLE_NCTS (1 << 3) 9476 9477/* HSW Audio */ 9478#define _HSW_AUD_CONFIG_A 0x65000 9479#define _HSW_AUD_CONFIG_B 0x65100 9480#define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 9481 9482#define _HSW_AUD_MISC_CTRL_A 0x65010 9483#define _HSW_AUD_MISC_CTRL_B 0x65110 9484#define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 9485 9486#define _HSW_AUD_M_CTS_ENABLE_A 0x65028 9487#define _HSW_AUD_M_CTS_ENABLE_B 0x65128 9488#define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 9489#define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 9490#define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 9491#define AUD_CONFIG_M_MASK 0xfffff 9492 9493#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 9494#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 9495#define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 9496 9497/* Audio Digital Converter */ 9498#define _HSW_AUD_DIG_CNVT_1 0x65080 9499#define _HSW_AUD_DIG_CNVT_2 0x65180 9500#define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 9501#define DIP_PORT_SEL_MASK 0x3 9502 9503#define _HSW_AUD_EDID_DATA_A 0x65050 9504#define _HSW_AUD_EDID_DATA_B 0x65150 9505#define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 9506 9507#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 9508#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 9509#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 9510#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 9511#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 9512#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 9513 9514#define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 9515#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 9516 9517#define AUD_FREQ_CNTRL _MMIO(0x65900) 9518#define AUD_PIN_BUF_CTL _MMIO(0x48414) 9519#define AUD_PIN_BUF_ENABLE REG_BIT(31) 9520 9521/* Display Audio Config Reg */ 9522#define AUD_CONFIG_BE _MMIO(0x65ef0) 9523#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 9524#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 9525#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 9526#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 9527#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 9528#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 9529 9530#define HBLANK_START_COUNT_8 0 9531#define HBLANK_START_COUNT_16 1 9532#define HBLANK_START_COUNT_32 2 9533#define HBLANK_START_COUNT_64 3 9534#define HBLANK_START_COUNT_96 4 9535#define HBLANK_START_COUNT_128 5 9536 9537/* 9538 * HSW - ICL power wells 9539 * 9540 * Platforms have up to 3 power well control register sets, each set 9541 * controlling up to 16 power wells via a request/status HW flag tuple: 9542 * - main (HSW_PWR_WELL_CTL[1-4]) 9543 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 9544 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 9545 * Each control register set consists of up to 4 registers used by different 9546 * sources that can request a power well to be enabled: 9547 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 9548 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 9549 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 9550 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 9551 */ 9552#define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 9553#define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 9554#define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 9555#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 9556#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 9557#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 9558 9559/* HSW/BDW power well */ 9560#define HSW_PW_CTL_IDX_GLOBAL 15 9561 9562/* SKL/BXT/GLK/CNL power wells */ 9563#define SKL_PW_CTL_IDX_PW_2 15 9564#define SKL_PW_CTL_IDX_PW_1 14 9565#define CNL_PW_CTL_IDX_AUX_F 12 9566#define CNL_PW_CTL_IDX_AUX_D 11 9567#define GLK_PW_CTL_IDX_AUX_C 10 9568#define GLK_PW_CTL_IDX_AUX_B 9 9569#define GLK_PW_CTL_IDX_AUX_A 8 9570#define CNL_PW_CTL_IDX_DDI_F 6 9571#define SKL_PW_CTL_IDX_DDI_D 4 9572#define SKL_PW_CTL_IDX_DDI_C 3 9573#define SKL_PW_CTL_IDX_DDI_B 2 9574#define SKL_PW_CTL_IDX_DDI_A_E 1 9575#define GLK_PW_CTL_IDX_DDI_A 1 9576#define SKL_PW_CTL_IDX_MISC_IO 0 9577 9578/* ICL/TGL - power wells */ 9579#define TGL_PW_CTL_IDX_PW_5 4 9580#define ICL_PW_CTL_IDX_PW_4 3 9581#define ICL_PW_CTL_IDX_PW_3 2 9582#define ICL_PW_CTL_IDX_PW_2 1 9583#define ICL_PW_CTL_IDX_PW_1 0 9584 9585#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 9586#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 9587#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 9588#define TGL_PW_CTL_IDX_AUX_TBT6 14 9589#define TGL_PW_CTL_IDX_AUX_TBT5 13 9590#define TGL_PW_CTL_IDX_AUX_TBT4 12 9591#define ICL_PW_CTL_IDX_AUX_TBT4 11 9592#define TGL_PW_CTL_IDX_AUX_TBT3 11 9593#define ICL_PW_CTL_IDX_AUX_TBT3 10 9594#define TGL_PW_CTL_IDX_AUX_TBT2 10 9595#define ICL_PW_CTL_IDX_AUX_TBT2 9 9596#define TGL_PW_CTL_IDX_AUX_TBT1 9 9597#define ICL_PW_CTL_IDX_AUX_TBT1 8 9598#define TGL_PW_CTL_IDX_AUX_TC6 8 9599#define TGL_PW_CTL_IDX_AUX_TC5 7 9600#define TGL_PW_CTL_IDX_AUX_TC4 6 9601#define ICL_PW_CTL_IDX_AUX_F 5 9602#define TGL_PW_CTL_IDX_AUX_TC3 5 9603#define ICL_PW_CTL_IDX_AUX_E 4 9604#define TGL_PW_CTL_IDX_AUX_TC2 4 9605#define ICL_PW_CTL_IDX_AUX_D 3 9606#define TGL_PW_CTL_IDX_AUX_TC1 3 9607#define ICL_PW_CTL_IDX_AUX_C 2 9608#define ICL_PW_CTL_IDX_AUX_B 1 9609#define ICL_PW_CTL_IDX_AUX_A 0 9610 9611#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 9612#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 9613#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 9614#define TGL_PW_CTL_IDX_DDI_TC6 8 9615#define TGL_PW_CTL_IDX_DDI_TC5 7 9616#define TGL_PW_CTL_IDX_DDI_TC4 6 9617#define ICL_PW_CTL_IDX_DDI_F 5 9618#define TGL_PW_CTL_IDX_DDI_TC3 5 9619#define ICL_PW_CTL_IDX_DDI_E 4 9620#define TGL_PW_CTL_IDX_DDI_TC2 4 9621#define ICL_PW_CTL_IDX_DDI_D 3 9622#define TGL_PW_CTL_IDX_DDI_TC1 3 9623#define ICL_PW_CTL_IDX_DDI_C 2 9624#define ICL_PW_CTL_IDX_DDI_B 1 9625#define ICL_PW_CTL_IDX_DDI_A 0 9626 9627/* HSW - power well misc debug registers */ 9628#define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 9629#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 9630#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 9631#define HSW_PWR_WELL_FORCE_ON (1 << 19) 9632#define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 9633 9634/* SKL Fuse Status */ 9635enum skl_power_gate { 9636 SKL_PG0, 9637 SKL_PG1, 9638 SKL_PG2, 9639 ICL_PG3, 9640 ICL_PG4, 9641}; 9642 9643#define SKL_FUSE_STATUS _MMIO(0x42000) 9644#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 9645/* 9646 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9647 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 9648 */ 9649#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 9650 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 9651/* 9652 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 9653 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 9654 */ 9655#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 9656 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 9657#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 9658 9659#define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) 9660#define _CNL_AUX_ANAOVRD1_B 0x162250 9661#define _CNL_AUX_ANAOVRD1_C 0x162210 9662#define _CNL_AUX_ANAOVRD1_D 0x1622D0 9663#define _CNL_AUX_ANAOVRD1_F 0x162A90 9664#define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ 9665 _CNL_AUX_ANAOVRD1_B, \ 9666 _CNL_AUX_ANAOVRD1_C, \ 9667 _CNL_AUX_ANAOVRD1_D, \ 9668 _CNL_AUX_ANAOVRD1_F)) 9669#define CNL_AUX_ANAOVRD1_ENABLE (1 << 16) 9670#define CNL_AUX_ANAOVRD1_LDO_BYPASS (1 << 23) 9671 9672#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 9673#define _ICL_AUX_ANAOVRD1_A 0x162398 9674#define _ICL_AUX_ANAOVRD1_B 0x6C398 9675#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 9676 _ICL_AUX_ANAOVRD1_A, \ 9677 _ICL_AUX_ANAOVRD1_B)) 9678#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 9679#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 9680 9681/* HDCP Key Registers */ 9682#define HDCP_KEY_CONF _MMIO(0x66c00) 9683#define HDCP_AKSV_SEND_TRIGGER BIT(31) 9684#define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 9685#define HDCP_KEY_LOAD_TRIGGER BIT(8) 9686#define HDCP_KEY_STATUS _MMIO(0x66c04) 9687#define HDCP_FUSE_IN_PROGRESS BIT(7) 9688#define HDCP_FUSE_ERROR BIT(6) 9689#define HDCP_FUSE_DONE BIT(5) 9690#define HDCP_KEY_LOAD_STATUS BIT(1) 9691#define HDCP_KEY_LOAD_DONE BIT(0) 9692#define HDCP_AKSV_LO _MMIO(0x66c10) 9693#define HDCP_AKSV_HI _MMIO(0x66c14) 9694 9695/* HDCP Repeater Registers */ 9696#define HDCP_REP_CTL _MMIO(0x66d00) 9697#define HDCP_TRANSA_REP_PRESENT BIT(31) 9698#define HDCP_TRANSB_REP_PRESENT BIT(30) 9699#define HDCP_TRANSC_REP_PRESENT BIT(29) 9700#define HDCP_TRANSD_REP_PRESENT BIT(28) 9701#define HDCP_DDIB_REP_PRESENT BIT(30) 9702#define HDCP_DDIA_REP_PRESENT BIT(29) 9703#define HDCP_DDIC_REP_PRESENT BIT(28) 9704#define HDCP_DDID_REP_PRESENT BIT(27) 9705#define HDCP_DDIF_REP_PRESENT BIT(26) 9706#define HDCP_DDIE_REP_PRESENT BIT(25) 9707#define HDCP_TRANSA_SHA1_M0 (1 << 20) 9708#define HDCP_TRANSB_SHA1_M0 (2 << 20) 9709#define HDCP_TRANSC_SHA1_M0 (3 << 20) 9710#define HDCP_TRANSD_SHA1_M0 (4 << 20) 9711#define HDCP_DDIB_SHA1_M0 (1 << 20) 9712#define HDCP_DDIA_SHA1_M0 (2 << 20) 9713#define HDCP_DDIC_SHA1_M0 (3 << 20) 9714#define HDCP_DDID_SHA1_M0 (4 << 20) 9715#define HDCP_DDIF_SHA1_M0 (5 << 20) 9716#define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 9717#define HDCP_SHA1_BUSY BIT(16) 9718#define HDCP_SHA1_READY BIT(17) 9719#define HDCP_SHA1_COMPLETE BIT(18) 9720#define HDCP_SHA1_V_MATCH BIT(19) 9721#define HDCP_SHA1_TEXT_32 (1 << 1) 9722#define HDCP_SHA1_COMPLETE_HASH (2 << 1) 9723#define HDCP_SHA1_TEXT_24 (4 << 1) 9724#define HDCP_SHA1_TEXT_16 (5 << 1) 9725#define HDCP_SHA1_TEXT_8 (6 << 1) 9726#define HDCP_SHA1_TEXT_0 (7 << 1) 9727#define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 9728#define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 9729#define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 9730#define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 9731#define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 9732#define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 9733#define HDCP_SHA_TEXT _MMIO(0x66d18) 9734 9735/* HDCP Auth Registers */ 9736#define _PORTA_HDCP_AUTHENC 0x66800 9737#define _PORTB_HDCP_AUTHENC 0x66500 9738#define _PORTC_HDCP_AUTHENC 0x66600 9739#define _PORTD_HDCP_AUTHENC 0x66700 9740#define _PORTE_HDCP_AUTHENC 0x66A00 9741#define _PORTF_HDCP_AUTHENC 0x66900 9742#define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 9743 _PORTA_HDCP_AUTHENC, \ 9744 _PORTB_HDCP_AUTHENC, \ 9745 _PORTC_HDCP_AUTHENC, \ 9746 _PORTD_HDCP_AUTHENC, \ 9747 _PORTE_HDCP_AUTHENC, \ 9748 _PORTF_HDCP_AUTHENC) + (x)) 9749#define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 9750#define _TRANSA_HDCP_CONF 0x66400 9751#define _TRANSB_HDCP_CONF 0x66500 9752#define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \ 9753 _TRANSB_HDCP_CONF) 9754#define HDCP_CONF(dev_priv, trans, port) \ 9755 (INTEL_GEN(dev_priv) >= 12 ? \ 9756 TRANS_HDCP_CONF(trans) : \ 9757 PORT_HDCP_CONF(port)) 9758 9759#define HDCP_CONF_CAPTURE_AN BIT(0) 9760#define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 9761#define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 9762#define _TRANSA_HDCP_ANINIT 0x66404 9763#define _TRANSB_HDCP_ANINIT 0x66504 9764#define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \ 9765 _TRANSA_HDCP_ANINIT, \ 9766 _TRANSB_HDCP_ANINIT) 9767#define HDCP_ANINIT(dev_priv, trans, port) \ 9768 (INTEL_GEN(dev_priv) >= 12 ? \ 9769 TRANS_HDCP_ANINIT(trans) : \ 9770 PORT_HDCP_ANINIT(port)) 9771 9772#define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 9773#define _TRANSA_HDCP_ANLO 0x66408 9774#define _TRANSB_HDCP_ANLO 0x66508 9775#define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \ 9776 _TRANSB_HDCP_ANLO) 9777#define HDCP_ANLO(dev_priv, trans, port) \ 9778 (INTEL_GEN(dev_priv) >= 12 ? \ 9779 TRANS_HDCP_ANLO(trans) : \ 9780 PORT_HDCP_ANLO(port)) 9781 9782#define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 9783#define _TRANSA_HDCP_ANHI 0x6640C 9784#define _TRANSB_HDCP_ANHI 0x6650C 9785#define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \ 9786 _TRANSB_HDCP_ANHI) 9787#define HDCP_ANHI(dev_priv, trans, port) \ 9788 (INTEL_GEN(dev_priv) >= 12 ? \ 9789 TRANS_HDCP_ANHI(trans) : \ 9790 PORT_HDCP_ANHI(port)) 9791 9792#define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 9793#define _TRANSA_HDCP_BKSVLO 0x66410 9794#define _TRANSB_HDCP_BKSVLO 0x66510 9795#define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \ 9796 _TRANSA_HDCP_BKSVLO, \ 9797 _TRANSB_HDCP_BKSVLO) 9798#define HDCP_BKSVLO(dev_priv, trans, port) \ 9799 (INTEL_GEN(dev_priv) >= 12 ? \ 9800 TRANS_HDCP_BKSVLO(trans) : \ 9801 PORT_HDCP_BKSVLO(port)) 9802 9803#define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 9804#define _TRANSA_HDCP_BKSVHI 0x66414 9805#define _TRANSB_HDCP_BKSVHI 0x66514 9806#define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \ 9807 _TRANSA_HDCP_BKSVHI, \ 9808 _TRANSB_HDCP_BKSVHI) 9809#define HDCP_BKSVHI(dev_priv, trans, port) \ 9810 (INTEL_GEN(dev_priv) >= 12 ? \ 9811 TRANS_HDCP_BKSVHI(trans) : \ 9812 PORT_HDCP_BKSVHI(port)) 9813 9814#define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 9815#define _TRANSA_HDCP_RPRIME 0x66418 9816#define _TRANSB_HDCP_RPRIME 0x66518 9817#define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \ 9818 _TRANSA_HDCP_RPRIME, \ 9819 _TRANSB_HDCP_RPRIME) 9820#define HDCP_RPRIME(dev_priv, trans, port) \ 9821 (INTEL_GEN(dev_priv) >= 12 ? \ 9822 TRANS_HDCP_RPRIME(trans) : \ 9823 PORT_HDCP_RPRIME(port)) 9824 9825#define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 9826#define _TRANSA_HDCP_STATUS 0x6641C 9827#define _TRANSB_HDCP_STATUS 0x6651C 9828#define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \ 9829 _TRANSA_HDCP_STATUS, \ 9830 _TRANSB_HDCP_STATUS) 9831#define HDCP_STATUS(dev_priv, trans, port) \ 9832 (INTEL_GEN(dev_priv) >= 12 ? \ 9833 TRANS_HDCP_STATUS(trans) : \ 9834 PORT_HDCP_STATUS(port)) 9835 9836#define HDCP_STATUS_STREAM_A_ENC BIT(31) 9837#define HDCP_STATUS_STREAM_B_ENC BIT(30) 9838#define HDCP_STATUS_STREAM_C_ENC BIT(29) 9839#define HDCP_STATUS_STREAM_D_ENC BIT(28) 9840#define HDCP_STATUS_AUTH BIT(21) 9841#define HDCP_STATUS_ENC BIT(20) 9842#define HDCP_STATUS_RI_MATCH BIT(19) 9843#define HDCP_STATUS_R0_READY BIT(18) 9844#define HDCP_STATUS_AN_READY BIT(17) 9845#define HDCP_STATUS_CIPHER BIT(16) 9846#define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 9847 9848/* HDCP2.2 Registers */ 9849#define _PORTA_HDCP2_BASE 0x66800 9850#define _PORTB_HDCP2_BASE 0x66500 9851#define _PORTC_HDCP2_BASE 0x66600 9852#define _PORTD_HDCP2_BASE 0x66700 9853#define _PORTE_HDCP2_BASE 0x66A00 9854#define _PORTF_HDCP2_BASE 0x66900 9855#define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 9856 _PORTA_HDCP2_BASE, \ 9857 _PORTB_HDCP2_BASE, \ 9858 _PORTC_HDCP2_BASE, \ 9859 _PORTD_HDCP2_BASE, \ 9860 _PORTE_HDCP2_BASE, \ 9861 _PORTF_HDCP2_BASE) + (x)) 9862#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) 9863#define _TRANSA_HDCP2_AUTH 0x66498 9864#define _TRANSB_HDCP2_AUTH 0x66598 9865#define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \ 9866 _TRANSB_HDCP2_AUTH) 9867#define AUTH_LINK_AUTHENTICATED BIT(31) 9868#define AUTH_LINK_TYPE BIT(30) 9869#define AUTH_FORCE_CLR_INPUTCTR BIT(19) 9870#define AUTH_CLR_KEYS BIT(18) 9871#define HDCP2_AUTH(dev_priv, trans, port) \ 9872 (INTEL_GEN(dev_priv) >= 12 ? \ 9873 TRANS_HDCP2_AUTH(trans) : \ 9874 PORT_HDCP2_AUTH(port)) 9875 9876#define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0) 9877#define _TRANSA_HDCP2_CTL 0x664B0 9878#define _TRANSB_HDCP2_CTL 0x665B0 9879#define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \ 9880 _TRANSB_HDCP2_CTL) 9881#define CTL_LINK_ENCRYPTION_REQ BIT(31) 9882#define HDCP2_CTL(dev_priv, trans, port) \ 9883 (INTEL_GEN(dev_priv) >= 12 ? \ 9884 TRANS_HDCP2_CTL(trans) : \ 9885 PORT_HDCP2_CTL(port)) 9886 9887#define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4) 9888#define _TRANSA_HDCP2_STATUS 0x664B4 9889#define _TRANSB_HDCP2_STATUS 0x665B4 9890#define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \ 9891 _TRANSA_HDCP2_STATUS, \ 9892 _TRANSB_HDCP2_STATUS) 9893#define LINK_TYPE_STATUS BIT(22) 9894#define LINK_AUTH_STATUS BIT(21) 9895#define LINK_ENCRYPTION_STATUS BIT(20) 9896#define HDCP2_STATUS(dev_priv, trans, port) \ 9897 (INTEL_GEN(dev_priv) >= 12 ? \ 9898 TRANS_HDCP2_STATUS(trans) : \ 9899 PORT_HDCP2_STATUS(port)) 9900 9901/* Per-pipe DDI Function Control */ 9902#define _TRANS_DDI_FUNC_CTL_A 0x60400 9903#define _TRANS_DDI_FUNC_CTL_B 0x61400 9904#define _TRANS_DDI_FUNC_CTL_C 0x62400 9905#define _TRANS_DDI_FUNC_CTL_D 0x63400 9906#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 9907#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 9908#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 9909#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 9910 9911#define TRANS_DDI_FUNC_ENABLE (1 << 31) 9912/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 9913#define TRANS_DDI_PORT_SHIFT 28 9914#define TGL_TRANS_DDI_PORT_SHIFT 27 9915#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 9916#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 9917#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 9918#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 9919#define TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) (((val) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT) 9920#define TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(val) ((((val) & TGL_TRANS_DDI_PORT_MASK) >> TGL_TRANS_DDI_PORT_SHIFT) - 1) 9921#define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 9922#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 9923#define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 9924#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 9925#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 9926#define TRANS_DDI_MODE_SELECT_FDI (4 << 24) 9927#define TRANS_DDI_BPC_MASK (7 << 20) 9928#define TRANS_DDI_BPC_8 (0 << 20) 9929#define TRANS_DDI_BPC_10 (1 << 20) 9930#define TRANS_DDI_BPC_6 (2 << 20) 9931#define TRANS_DDI_BPC_12 (3 << 20) 9932#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) /* bdw-cnl */ 9933#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 9934#define TRANS_DDI_PVSYNC (1 << 17) 9935#define TRANS_DDI_PHSYNC (1 << 16) 9936#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) /* bdw-cnl */ 9937#define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 9938#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 9939#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 9940#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 9941#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 9942#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 9943#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 9944#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 9945 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 9946#define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 9947#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 9948#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 9949#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 9950#define TRANS_DDI_BFI_ENABLE (1 << 4) 9951#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 9952#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 9953#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 9954 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 9955 | TRANS_DDI_HDMI_SCRAMBLING) 9956 9957#define _TRANS_DDI_FUNC_CTL2_A 0x60404 9958#define _TRANS_DDI_FUNC_CTL2_B 0x61404 9959#define _TRANS_DDI_FUNC_CTL2_C 0x62404 9960#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 9961#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 9962#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 9963#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 9964#define PORT_SYNC_MODE_ENABLE REG_BIT(4) 9965#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 9966#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 9967 9968/* DisplayPort Transport Control */ 9969#define _DP_TP_CTL_A 0x64040 9970#define _DP_TP_CTL_B 0x64140 9971#define _TGL_DP_TP_CTL_A 0x60540 9972#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 9973#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 9974#define DP_TP_CTL_ENABLE (1 << 31) 9975#define DP_TP_CTL_FEC_ENABLE (1 << 30) 9976#define DP_TP_CTL_MODE_SST (0 << 27) 9977#define DP_TP_CTL_MODE_MST (1 << 27) 9978#define DP_TP_CTL_FORCE_ACT (1 << 25) 9979#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 9980#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 9981#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 9982#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 9983#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 9984#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 9985#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 9986#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 9987#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 9988#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 9989 9990/* DisplayPort Transport Status */ 9991#define _DP_TP_STATUS_A 0x64044 9992#define _DP_TP_STATUS_B 0x64144 9993#define _TGL_DP_TP_STATUS_A 0x60544 9994#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 9995#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 9996#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 9997#define DP_TP_STATUS_IDLE_DONE (1 << 25) 9998#define DP_TP_STATUS_ACT_SENT (1 << 24) 9999#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 10000#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 10001#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 10002#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 10003#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 10004 10005/* DDI Buffer Control */ 10006#define _DDI_BUF_CTL_A 0x64000 10007#define _DDI_BUF_CTL_B 0x64100 10008#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 10009#define DDI_BUF_CTL_ENABLE (1 << 31) 10010#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 10011#define DDI_BUF_EMP_MASK (0xf << 24) 10012#define DDI_BUF_PORT_REVERSAL (1 << 16) 10013#define DDI_BUF_IS_IDLE (1 << 7) 10014#define DDI_A_4_LANES (1 << 4) 10015#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 10016#define DDI_PORT_WIDTH_MASK (7 << 1) 10017#define DDI_PORT_WIDTH_SHIFT 1 10018#define DDI_INIT_DISPLAY_DETECTED (1 << 0) 10019 10020/* DDI Buffer Translations */ 10021#define _DDI_BUF_TRANS_A 0x64E00 10022#define _DDI_BUF_TRANS_B 0x64E60 10023#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 10024#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 10025#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 10026 10027/* DDI DP Compliance Control */ 10028#define _DDI_DP_COMP_CTL_A 0x605F0 10029#define _DDI_DP_COMP_CTL_B 0x615F0 10030#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 10031#define DDI_DP_COMP_CTL_ENABLE (1 << 31) 10032#define DDI_DP_COMP_CTL_D10_2 (0 << 28) 10033#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 10034#define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 10035#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 10036#define DDI_DP_COMP_CTL_HBR2 (4 << 28) 10037#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 10038#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 10039 10040/* DDI DP Compliance Pattern */ 10041#define _DDI_DP_COMP_PAT_A 0x605F4 10042#define _DDI_DP_COMP_PAT_B 0x615F4 10043#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 10044 10045/* Sideband Interface (SBI) is programmed indirectly, via 10046 * SBI_ADDR, which contains the register offset; and SBI_DATA, 10047 * which contains the payload */ 10048#define SBI_ADDR _MMIO(0xC6000) 10049#define SBI_DATA _MMIO(0xC6004) 10050#define SBI_CTL_STAT _MMIO(0xC6008) 10051#define SBI_CTL_DEST_ICLK (0x0 << 16) 10052#define SBI_CTL_DEST_MPHY (0x1 << 16) 10053#define SBI_CTL_OP_IORD (0x2 << 8) 10054#define SBI_CTL_OP_IOWR (0x3 << 8) 10055#define SBI_CTL_OP_CRRD (0x6 << 8) 10056#define SBI_CTL_OP_CRWR (0x7 << 8) 10057#define SBI_RESPONSE_FAIL (0x1 << 1) 10058#define SBI_RESPONSE_SUCCESS (0x0 << 1) 10059#define SBI_BUSY (0x1 << 0) 10060#define SBI_READY (0x0 << 0) 10061 10062/* SBI offsets */ 10063#define SBI_SSCDIVINTPHASE 0x0200 10064#define SBI_SSCDIVINTPHASE6 0x0600 10065#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 10066#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 10067#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 10068#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 10069#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 10070#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 10071#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 10072#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 10073#define SBI_SSCDITHPHASE 0x0204 10074#define SBI_SSCCTL 0x020c 10075#define SBI_SSCCTL6 0x060C 10076#define SBI_SSCCTL_PATHALT (1 << 3) 10077#define SBI_SSCCTL_DISABLE (1 << 0) 10078#define SBI_SSCAUXDIV6 0x0610 10079#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 10080#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 10081#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 10082#define SBI_DBUFF0 0x2a00 10083#define SBI_GEN0 0x1f00 10084#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 10085 10086/* LPT PIXCLK_GATE */ 10087#define PIXCLK_GATE _MMIO(0xC6020) 10088#define PIXCLK_GATE_UNGATE (1 << 0) 10089#define PIXCLK_GATE_GATE (0 << 0) 10090 10091/* SPLL */ 10092#define SPLL_CTL _MMIO(0x46020) 10093#define SPLL_PLL_ENABLE (1 << 31) 10094#define SPLL_REF_BCLK (0 << 28) 10095#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 10096#define SPLL_REF_NON_SSC_HSW (2 << 28) 10097#define SPLL_REF_PCH_SSC_BDW (2 << 28) 10098#define SPLL_REF_LCPLL (3 << 28) 10099#define SPLL_REF_MASK (3 << 28) 10100#define SPLL_FREQ_810MHz (0 << 26) 10101#define SPLL_FREQ_1350MHz (1 << 26) 10102#define SPLL_FREQ_2700MHz (2 << 26) 10103#define SPLL_FREQ_MASK (3 << 26) 10104 10105/* WRPLL */ 10106#define _WRPLL_CTL1 0x46040 10107#define _WRPLL_CTL2 0x46060 10108#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 10109#define WRPLL_PLL_ENABLE (1 << 31) 10110#define WRPLL_REF_BCLK (0 << 28) 10111#define WRPLL_REF_PCH_SSC (1 << 28) 10112#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 10113#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 10114#define WRPLL_REF_LCPLL (3 << 28) 10115#define WRPLL_REF_MASK (3 << 28) 10116/* WRPLL divider programming */ 10117#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 10118#define WRPLL_DIVIDER_REF_MASK (0xff) 10119#define WRPLL_DIVIDER_POST(x) ((x) << 8) 10120#define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 10121#define WRPLL_DIVIDER_POST_SHIFT 8 10122#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 10123#define WRPLL_DIVIDER_FB_SHIFT 16 10124#define WRPLL_DIVIDER_FB_MASK (0xff << 16) 10125 10126/* Port clock selection */ 10127#define _PORT_CLK_SEL_A 0x46100 10128#define _PORT_CLK_SEL_B 0x46104 10129#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 10130#define PORT_CLK_SEL_LCPLL_2700 (0 << 29) 10131#define PORT_CLK_SEL_LCPLL_1350 (1 << 29) 10132#define PORT_CLK_SEL_LCPLL_810 (2 << 29) 10133#define PORT_CLK_SEL_SPLL (3 << 29) 10134#define PORT_CLK_SEL_WRPLL(pll) (((pll) + 4) << 29) 10135#define PORT_CLK_SEL_WRPLL1 (4 << 29) 10136#define PORT_CLK_SEL_WRPLL2 (5 << 29) 10137#define PORT_CLK_SEL_NONE (7 << 29) 10138#define PORT_CLK_SEL_MASK (7 << 29) 10139 10140/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 10141#define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 10142#define DDI_CLK_SEL_NONE (0x0 << 28) 10143#define DDI_CLK_SEL_MG (0x8 << 28) 10144#define DDI_CLK_SEL_TBT_162 (0xC << 28) 10145#define DDI_CLK_SEL_TBT_270 (0xD << 28) 10146#define DDI_CLK_SEL_TBT_540 (0xE << 28) 10147#define DDI_CLK_SEL_TBT_810 (0xF << 28) 10148#define DDI_CLK_SEL_MASK (0xF << 28) 10149 10150/* Transcoder clock selection */ 10151#define _TRANS_CLK_SEL_A 0x46140 10152#define _TRANS_CLK_SEL_B 0x46144 10153#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 10154/* For each transcoder, we need to select the corresponding port clock */ 10155#define TRANS_CLK_SEL_DISABLED (0x0 << 29) 10156#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 10157#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 10158#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 10159 10160 10161#define CDCLK_FREQ _MMIO(0x46200) 10162 10163#define _TRANSA_MSA_MISC 0x60410 10164#define _TRANSB_MSA_MISC 0x61410 10165#define _TRANSC_MSA_MISC 0x62410 10166#define _TRANS_EDP_MSA_MISC 0x6f410 10167#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 10168/* See DP_MSA_MISC_* for the bit definitions */ 10169 10170/* LCPLL Control */ 10171#define LCPLL_CTL _MMIO(0x130040) 10172#define LCPLL_PLL_DISABLE (1 << 31) 10173#define LCPLL_PLL_LOCK (1 << 30) 10174#define LCPLL_REF_NON_SSC (0 << 28) 10175#define LCPLL_REF_BCLK (2 << 28) 10176#define LCPLL_REF_PCH_SSC (3 << 28) 10177#define LCPLL_REF_MASK (3 << 28) 10178#define LCPLL_CLK_FREQ_MASK (3 << 26) 10179#define LCPLL_CLK_FREQ_450 (0 << 26) 10180#define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 10181#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 10182#define LCPLL_CLK_FREQ_675_BDW (3 << 26) 10183#define LCPLL_CD_CLOCK_DISABLE (1 << 25) 10184#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 10185#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 10186#define LCPLL_POWER_DOWN_ALLOW (1 << 22) 10187#define LCPLL_CD_SOURCE_FCLK (1 << 21) 10188#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 10189 10190/* 10191 * SKL Clocks 10192 */ 10193 10194/* CDCLK_CTL */ 10195#define CDCLK_CTL _MMIO(0x46000) 10196#define CDCLK_FREQ_SEL_MASK (3 << 26) 10197#define CDCLK_FREQ_450_432 (0 << 26) 10198#define CDCLK_FREQ_540 (1 << 26) 10199#define CDCLK_FREQ_337_308 (2 << 26) 10200#define CDCLK_FREQ_675_617 (3 << 26) 10201#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 10202#define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 10203#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 10204#define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 10205#define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 10206#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 10207#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 10208#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 10209#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 10210#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 10211#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 10212#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 10213#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 10214#define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 10215 10216/* LCPLL_CTL */ 10217#define LCPLL1_CTL _MMIO(0x46010) 10218#define LCPLL2_CTL _MMIO(0x46014) 10219#define LCPLL_PLL_ENABLE (1 << 31) 10220 10221/* DPLL control1 */ 10222#define DPLL_CTRL1 _MMIO(0x6C058) 10223#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 10224#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 10225#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 10226#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 10227#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 10228#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 10229#define DPLL_CTRL1_LINK_RATE_2700 0 10230#define DPLL_CTRL1_LINK_RATE_1350 1 10231#define DPLL_CTRL1_LINK_RATE_810 2 10232#define DPLL_CTRL1_LINK_RATE_1620 3 10233#define DPLL_CTRL1_LINK_RATE_1080 4 10234#define DPLL_CTRL1_LINK_RATE_2160 5 10235 10236/* DPLL control2 */ 10237#define DPLL_CTRL2 _MMIO(0x6C05C) 10238#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 10239#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 10240#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 10241#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 10242#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 10243 10244/* DPLL Status */ 10245#define DPLL_STATUS _MMIO(0x6C060) 10246#define DPLL_LOCK(id) (1 << ((id) * 8)) 10247 10248/* DPLL cfg */ 10249#define _DPLL1_CFGCR1 0x6C040 10250#define _DPLL2_CFGCR1 0x6C048 10251#define _DPLL3_CFGCR1 0x6C050 10252#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 10253#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 10254#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 10255#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 10256 10257#define _DPLL1_CFGCR2 0x6C044 10258#define _DPLL2_CFGCR2 0x6C04C 10259#define _DPLL3_CFGCR2 0x6C054 10260#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 10261#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 10262#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 10263#define DPLL_CFGCR2_KDIV_MASK (3 << 5) 10264#define DPLL_CFGCR2_KDIV(x) ((x) << 5) 10265#define DPLL_CFGCR2_KDIV_5 (0 << 5) 10266#define DPLL_CFGCR2_KDIV_2 (1 << 5) 10267#define DPLL_CFGCR2_KDIV_3 (2 << 5) 10268#define DPLL_CFGCR2_KDIV_1 (3 << 5) 10269#define DPLL_CFGCR2_PDIV_MASK (7 << 2) 10270#define DPLL_CFGCR2_PDIV(x) ((x) << 2) 10271#define DPLL_CFGCR2_PDIV_1 (0 << 2) 10272#define DPLL_CFGCR2_PDIV_2 (1 << 2) 10273#define DPLL_CFGCR2_PDIV_3 (2 << 2) 10274#define DPLL_CFGCR2_PDIV_7 (4 << 2) 10275#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 10276 10277#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 10278#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 10279 10280/* 10281 * CNL Clocks 10282 */ 10283#define DPCLKA_CFGCR0 _MMIO(0x6C200) 10284#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \ 10285 (port) + 10)) 10286#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \ 10287 (port) * 2) 10288#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 10289#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)) 10290 10291#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 10292#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24)) 10293#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 10294#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ 10295 (tc_port) + 12 : \ 10296 (tc_port) - PORT_TC4 + 21)) 10297#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 10298#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10299#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10300#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 10301#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 10302 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10303#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 10304 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 10305 10306/* CNL PLL */ 10307#define DPLL0_ENABLE 0x46010 10308#define DPLL1_ENABLE 0x46014 10309#define PLL_ENABLE (1 << 31) 10310#define PLL_LOCK (1 << 30) 10311#define PLL_POWER_ENABLE (1 << 27) 10312#define PLL_POWER_STATE (1 << 26) 10313#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) 10314 10315#define TBT_PLL_ENABLE _MMIO(0x46020) 10316 10317#define _MG_PLL1_ENABLE 0x46030 10318#define _MG_PLL2_ENABLE 0x46034 10319#define _MG_PLL3_ENABLE 0x46038 10320#define _MG_PLL4_ENABLE 0x4603C 10321/* Bits are the same as DPLL0_ENABLE */ 10322#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 10323 _MG_PLL2_ENABLE) 10324 10325#define _MG_REFCLKIN_CTL_PORT1 0x16892C 10326#define _MG_REFCLKIN_CTL_PORT2 0x16992C 10327#define _MG_REFCLKIN_CTL_PORT3 0x16A92C 10328#define _MG_REFCLKIN_CTL_PORT4 0x16B92C 10329#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) 10330#define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) 10331#define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ 10332 _MG_REFCLKIN_CTL_PORT1, \ 10333 _MG_REFCLKIN_CTL_PORT2) 10334 10335#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 10336#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 10337#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16A8D8 10338#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16B8D8 10339#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) 10340#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) 10341#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) 10342#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) 10343#define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ 10344 _MG_CLKTOP2_CORECLKCTL1_PORT1, \ 10345 _MG_CLKTOP2_CORECLKCTL1_PORT2) 10346 10347#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 10348#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 10349#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4 10350#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4 10351#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) 10352#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) 10353#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) 10354#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) 10355#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) 10356#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) 10357#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) 10358#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) 10359#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) 10360#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) 10361#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 10362#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) 10363#define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ 10364 _MG_CLKTOP2_HSCLKCTL_PORT1, \ 10365 _MG_CLKTOP2_HSCLKCTL_PORT2) 10366 10367#define _MG_PLL_DIV0_PORT1 0x168A00 10368#define _MG_PLL_DIV0_PORT2 0x169A00 10369#define _MG_PLL_DIV0_PORT3 0x16AA00 10370#define _MG_PLL_DIV0_PORT4 0x16BA00 10371#define MG_PLL_DIV0_FRACNEN_H (1 << 30) 10372#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) 10373#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 10374#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) 10375#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) 10376#define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 10377#define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ 10378 _MG_PLL_DIV0_PORT2) 10379 10380#define _MG_PLL_DIV1_PORT1 0x168A04 10381#define _MG_PLL_DIV1_PORT2 0x169A04 10382#define _MG_PLL_DIV1_PORT3 0x16AA04 10383#define _MG_PLL_DIV1_PORT4 0x16BA04 10384#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) 10385#define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) 10386#define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) 10387#define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) 10388#define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) 10389#define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) 10390#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) 10391#define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) 10392#define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ 10393 _MG_PLL_DIV1_PORT2) 10394 10395#define _MG_PLL_LF_PORT1 0x168A08 10396#define _MG_PLL_LF_PORT2 0x169A08 10397#define _MG_PLL_LF_PORT3 0x16AA08 10398#define _MG_PLL_LF_PORT4 0x16BA08 10399#define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) 10400#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) 10401#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) 10402#define MG_PLL_LF_GAINCTRL(x) ((x) << 16) 10403#define MG_PLL_LF_INT_COEFF(x) ((x) << 8) 10404#define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) 10405#define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ 10406 _MG_PLL_LF_PORT2) 10407 10408#define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C 10409#define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C 10410#define _MG_PLL_FRAC_LOCK_PORT3 0x16AA0C 10411#define _MG_PLL_FRAC_LOCK_PORT4 0x16BA0C 10412#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) 10413#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) 10414#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) 10415#define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) 10416#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) 10417#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) 10418#define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ 10419 _MG_PLL_FRAC_LOCK_PORT1, \ 10420 _MG_PLL_FRAC_LOCK_PORT2) 10421 10422#define _MG_PLL_SSC_PORT1 0x168A10 10423#define _MG_PLL_SSC_PORT2 0x169A10 10424#define _MG_PLL_SSC_PORT3 0x16AA10 10425#define _MG_PLL_SSC_PORT4 0x16BA10 10426#define MG_PLL_SSC_EN (1 << 28) 10427#define MG_PLL_SSC_TYPE(x) ((x) << 26) 10428#define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) 10429#define MG_PLL_SSC_STEPNUM(x) ((x) << 10) 10430#define MG_PLL_SSC_FLLEN (1 << 9) 10431#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) 10432#define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ 10433 _MG_PLL_SSC_PORT2) 10434 10435#define _MG_PLL_BIAS_PORT1 0x168A14 10436#define _MG_PLL_BIAS_PORT2 0x169A14 10437#define _MG_PLL_BIAS_PORT3 0x16AA14 10438#define _MG_PLL_BIAS_PORT4 0x16BA14 10439#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) 10440#define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) 10441#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) 10442#define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) 10443#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) 10444#define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) 10445#define MG_PLL_BIAS_BIASCAL_EN (1 << 15) 10446#define MG_PLL_BIAS_CTRIM(x) ((x) << 8) 10447#define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) 10448#define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) 10449#define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) 10450#define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) 10451#define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) 10452#define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ 10453 _MG_PLL_BIAS_PORT2) 10454 10455#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 10456#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 10457#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16AA18 10458#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16BA18 10459#define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) 10460#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) 10461#define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) 10462#define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) 10463#define MG_PLL_TDC_TDCSEL(x) ((x) << 0) 10464#define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ 10465 _MG_PLL_TDC_COLDST_BIAS_PORT1, \ 10466 _MG_PLL_TDC_COLDST_BIAS_PORT2) 10467 10468#define _CNL_DPLL0_CFGCR0 0x6C000 10469#define _CNL_DPLL1_CFGCR0 0x6C080 10470#define DPLL_CFGCR0_HDMI_MODE (1 << 30) 10471#define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 10472#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 10473#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 10474#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 10475#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 10476#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 10477#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 10478#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 10479#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 10480#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 10481#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 10482#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 10483#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 10484#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 10485#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 10486#define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) 10487 10488#define _CNL_DPLL0_CFGCR1 0x6C004 10489#define _CNL_DPLL1_CFGCR1 0x6C084 10490#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 10491#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 10492#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 10493#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 10494#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 10495#define DPLL_CFGCR1_KDIV_MASK (7 << 6) 10496#define DPLL_CFGCR1_KDIV_SHIFT (6) 10497#define DPLL_CFGCR1_KDIV(x) ((x) << 6) 10498#define DPLL_CFGCR1_KDIV_1 (1 << 6) 10499#define DPLL_CFGCR1_KDIV_2 (2 << 6) 10500#define DPLL_CFGCR1_KDIV_3 (4 << 6) 10501#define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 10502#define DPLL_CFGCR1_PDIV_SHIFT (2) 10503#define DPLL_CFGCR1_PDIV(x) ((x) << 2) 10504#define DPLL_CFGCR1_PDIV_2 (1 << 2) 10505#define DPLL_CFGCR1_PDIV_3 (2 << 2) 10506#define DPLL_CFGCR1_PDIV_5 (4 << 2) 10507#define DPLL_CFGCR1_PDIV_7 (8 << 2) 10508#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 10509#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 10510#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 10511#define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1) 10512 10513#define _ICL_DPLL0_CFGCR0 0x164000 10514#define _ICL_DPLL1_CFGCR0 0x164080 10515#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 10516 _ICL_DPLL1_CFGCR0) 10517 10518#define _ICL_DPLL0_CFGCR1 0x164004 10519#define _ICL_DPLL1_CFGCR1 0x164084 10520#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 10521 _ICL_DPLL1_CFGCR1) 10522 10523#define _TGL_DPLL0_CFGCR0 0x164284 10524#define _TGL_DPLL1_CFGCR0 0x16428C 10525#define _TGL_TBTPLL_CFGCR0 0x16429C 10526#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 10527 _TGL_DPLL1_CFGCR0, \ 10528 _TGL_TBTPLL_CFGCR0) 10529#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 10530 _TGL_DPLL1_CFGCR0) 10531 10532#define _TGL_DPLL0_CFGCR1 0x164288 10533#define _TGL_DPLL1_CFGCR1 0x164290 10534#define _TGL_TBTPLL_CFGCR1 0x1642A0 10535#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 10536 _TGL_DPLL1_CFGCR1, \ 10537 _TGL_TBTPLL_CFGCR1) 10538#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 10539 _TGL_DPLL1_CFGCR1) 10540 10541#define _DKL_PHY1_BASE 0x168000 10542#define _DKL_PHY2_BASE 0x169000 10543#define _DKL_PHY3_BASE 0x16A000 10544#define _DKL_PHY4_BASE 0x16B000 10545#define _DKL_PHY5_BASE 0x16C000 10546#define _DKL_PHY6_BASE 0x16D000 10547 10548/* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 10549#define _DKL_PLL_DIV0 0x200 10550#define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 10551#define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 10552#define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 10553#define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 10554#define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 10555#define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 10556#define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 10557#define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 10558#define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 10559#define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10560 _DKL_PHY2_BASE) + \ 10561 _DKL_PLL_DIV0) 10562 10563#define _DKL_PLL_DIV1 0x204 10564#define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 10565#define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 10566#define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 10567#define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 10568#define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10569 _DKL_PHY2_BASE) + \ 10570 _DKL_PLL_DIV1) 10571 10572#define _DKL_PLL_SSC 0x210 10573#define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 10574#define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 10575#define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 10576#define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 10577#define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 10578#define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 10579#define DKL_PLL_SSC_EN (1 << 9) 10580#define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10581 _DKL_PHY2_BASE) + \ 10582 _DKL_PLL_SSC) 10583 10584#define _DKL_PLL_BIAS 0x214 10585#define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 10586#define DKL_PLL_BIAS_FBDIV_SHIFT (8) 10587#define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 10588#define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 10589#define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 10590 _DKL_PHY2_BASE) + \ 10591 _DKL_PLL_BIAS) 10592 10593#define _DKL_PLL_TDC_COLDST_BIAS 0x218 10594#define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 10595#define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 10596#define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 10597#define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 10598#define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 10599 _DKL_PHY1_BASE, \ 10600 _DKL_PHY2_BASE) + \ 10601 _DKL_PLL_TDC_COLDST_BIAS) 10602 10603#define _DKL_REFCLKIN_CTL 0x12C 10604/* Bits are the same as MG_REFCLKIN_CTL */ 10605#define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 10606 _DKL_PHY1_BASE, \ 10607 _DKL_PHY2_BASE) + \ 10608 _DKL_REFCLKIN_CTL) 10609 10610#define _DKL_CLKTOP2_HSCLKCTL 0xD4 10611/* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 10612#define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 10613 _DKL_PHY1_BASE, \ 10614 _DKL_PHY2_BASE) + \ 10615 _DKL_CLKTOP2_HSCLKCTL) 10616 10617#define _DKL_CLKTOP2_CORECLKCTL1 0xD8 10618/* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 10619#define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 10620 _DKL_PHY1_BASE, \ 10621 _DKL_PHY2_BASE) + \ 10622 _DKL_CLKTOP2_CORECLKCTL1) 10623 10624#define _DKL_TX_DPCNTL0 0x2C0 10625#define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 10626#define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 10627#define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 10628#define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 10629#define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 10630#define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 10631#define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 10632 _DKL_PHY1_BASE, \ 10633 _DKL_PHY2_BASE) + \ 10634 _DKL_TX_DPCNTL0) 10635 10636#define _DKL_TX_DPCNTL1 0x2C4 10637/* Bits are the same as DKL_TX_DPCNTRL0 */ 10638#define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 10639 _DKL_PHY1_BASE, \ 10640 _DKL_PHY2_BASE) + \ 10641 _DKL_TX_DPCNTL1) 10642 10643#define _DKL_TX_DPCNTL2 0x2C8 10644#define DKL_TX_DP20BITMODE (1 << 2) 10645#define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 10646 _DKL_PHY1_BASE, \ 10647 _DKL_PHY2_BASE) + \ 10648 _DKL_TX_DPCNTL2) 10649 10650#define _DKL_TX_FW_CALIB 0x2F8 10651#define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 10652#define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 10653 _DKL_PHY1_BASE, \ 10654 _DKL_PHY2_BASE) + \ 10655 _DKL_TX_FW_CALIB) 10656 10657#define _DKL_TX_PMD_LANE_SUS 0xD00 10658#define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 10659 _DKL_PHY1_BASE, \ 10660 _DKL_PHY2_BASE) + \ 10661 _DKL_TX_PMD_LANE_SUS) 10662 10663#define _DKL_TX_DW17 0xDC4 10664#define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 10665 _DKL_PHY1_BASE, \ 10666 _DKL_PHY2_BASE) + \ 10667 _DKL_TX_DW17) 10668 10669#define _DKL_TX_DW18 0xDC8 10670#define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 10671 _DKL_PHY1_BASE, \ 10672 _DKL_PHY2_BASE) + \ 10673 _DKL_TX_DW18) 10674 10675#define _DKL_DP_MODE 0xA0 10676#define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 10677 _DKL_PHY1_BASE, \ 10678 _DKL_PHY2_BASE) + \ 10679 _DKL_DP_MODE) 10680 10681#define _DKL_CMN_UC_DW27 0x36C 10682#define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 10683#define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 10684 _DKL_PHY1_BASE, \ 10685 _DKL_PHY2_BASE) + \ 10686 _DKL_CMN_UC_DW27) 10687 10688/* 10689 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 10690 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 10691 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 10692 * bits that point the 4KB window into the full PHY register space. 10693 */ 10694#define _HIP_INDEX_REG0 0x1010A0 10695#define _HIP_INDEX_REG1 0x1010A4 10696#define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 10697 : _HIP_INDEX_REG1) 10698#define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 10699#define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 10700 10701/* BXT display engine PLL */ 10702#define BXT_DE_PLL_CTL _MMIO(0x6d000) 10703#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 10704#define BXT_DE_PLL_RATIO_MASK 0xff 10705 10706#define BXT_DE_PLL_ENABLE _MMIO(0x46070) 10707#define BXT_DE_PLL_PLL_ENABLE (1 << 31) 10708#define BXT_DE_PLL_LOCK (1 << 30) 10709#define CNL_CDCLK_PLL_RATIO(x) (x) 10710#define CNL_CDCLK_PLL_RATIO_MASK 0xff 10711 10712/* GEN9 DC */ 10713#define DC_STATE_EN _MMIO(0x45504) 10714#define DC_STATE_DISABLE 0 10715#define DC_STATE_EN_DC3CO REG_BIT(30) 10716#define DC_STATE_DC3CO_STATUS REG_BIT(29) 10717#define DC_STATE_EN_UPTO_DC5 (1 << 0) 10718#define DC_STATE_EN_DC9 (1 << 3) 10719#define DC_STATE_EN_UPTO_DC6 (2 << 0) 10720#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 10721 10722#define DC_STATE_DEBUG _MMIO(0x45520) 10723#define DC_STATE_DEBUG_MASK_CORES (1 << 0) 10724#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 10725 10726#define BXT_P_CR_MC_BIOS_REQ_0_0_0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114) 10727#define BXT_REQ_DATA_MASK 0x3F 10728#define BXT_DRAM_CHANNEL_ACTIVE_SHIFT 12 10729#define BXT_DRAM_CHANNEL_ACTIVE_MASK (0xF << 12) 10730#define BXT_MEMORY_FREQ_MULTIPLIER_HZ 133333333 10731 10732#define BXT_D_CR_DRP0_DUNIT8 0x1000 10733#define BXT_D_CR_DRP0_DUNIT9 0x1200 10734#define BXT_D_CR_DRP0_DUNIT_START 8 10735#define BXT_D_CR_DRP0_DUNIT_END 11 10736#define BXT_D_CR_DRP0_DUNIT(x) _MMIO(MCHBAR_MIRROR_BASE_SNB + \ 10737 _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\ 10738 BXT_D_CR_DRP0_DUNIT9)) 10739#define BXT_DRAM_RANK_MASK 0x3 10740#define BXT_DRAM_RANK_SINGLE 0x1 10741#define BXT_DRAM_RANK_DUAL 0x3 10742#define BXT_DRAM_WIDTH_MASK (0x3 << 4) 10743#define BXT_DRAM_WIDTH_SHIFT 4 10744#define BXT_DRAM_WIDTH_X8 (0x0 << 4) 10745#define BXT_DRAM_WIDTH_X16 (0x1 << 4) 10746#define BXT_DRAM_WIDTH_X32 (0x2 << 4) 10747#define BXT_DRAM_WIDTH_X64 (0x3 << 4) 10748#define BXT_DRAM_SIZE_MASK (0x7 << 6) 10749#define BXT_DRAM_SIZE_SHIFT 6 10750#define BXT_DRAM_SIZE_4GBIT (0x0 << 6) 10751#define BXT_DRAM_SIZE_6GBIT (0x1 << 6) 10752#define BXT_DRAM_SIZE_8GBIT (0x2 << 6) 10753#define BXT_DRAM_SIZE_12GBIT (0x3 << 6) 10754#define BXT_DRAM_SIZE_16GBIT (0x4 << 6) 10755#define BXT_DRAM_TYPE_MASK (0x7 << 22) 10756#define BXT_DRAM_TYPE_SHIFT 22 10757#define BXT_DRAM_TYPE_DDR3 (0x0 << 22) 10758#define BXT_DRAM_TYPE_LPDDR3 (0x1 << 22) 10759#define BXT_DRAM_TYPE_LPDDR4 (0x2 << 22) 10760#define BXT_DRAM_TYPE_DDR4 (0x4 << 22) 10761 10762#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666 10763#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04) 10764#define SKL_REQ_DATA_MASK (0xF << 0) 10765 10766#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 10767#define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 10768#define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 10769#define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 10770#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 10771#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 10772 10773#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 10774#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 10775#define SKL_DRAM_S_SHIFT 16 10776#define SKL_DRAM_SIZE_MASK 0x3F 10777#define SKL_DRAM_WIDTH_MASK (0x3 << 8) 10778#define SKL_DRAM_WIDTH_SHIFT 8 10779#define SKL_DRAM_WIDTH_X8 (0x0 << 8) 10780#define SKL_DRAM_WIDTH_X16 (0x1 << 8) 10781#define SKL_DRAM_WIDTH_X32 (0x2 << 8) 10782#define SKL_DRAM_RANK_MASK (0x1 << 10) 10783#define SKL_DRAM_RANK_SHIFT 10 10784#define SKL_DRAM_RANK_1 (0x0 << 10) 10785#define SKL_DRAM_RANK_2 (0x1 << 10) 10786#define SKL_DRAM_RANK_MASK (0x1 << 10) 10787#define CNL_DRAM_SIZE_MASK 0x7F 10788#define CNL_DRAM_WIDTH_MASK (0x3 << 7) 10789#define CNL_DRAM_WIDTH_SHIFT 7 10790#define CNL_DRAM_WIDTH_X8 (0x0 << 7) 10791#define CNL_DRAM_WIDTH_X16 (0x1 << 7) 10792#define CNL_DRAM_WIDTH_X32 (0x2 << 7) 10793#define CNL_DRAM_RANK_MASK (0x3 << 9) 10794#define CNL_DRAM_RANK_SHIFT 9 10795#define CNL_DRAM_RANK_1 (0x0 << 9) 10796#define CNL_DRAM_RANK_2 (0x1 << 9) 10797#define CNL_DRAM_RANK_3 (0x2 << 9) 10798#define CNL_DRAM_RANK_4 (0x3 << 9) 10799 10800/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 10801 * since on HSW we can't write to it using I915_WRITE. */ 10802#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 10803#define D_COMP_BDW _MMIO(0x138144) 10804#define D_COMP_RCOMP_IN_PROGRESS (1 << 9) 10805#define D_COMP_COMP_FORCE (1 << 8) 10806#define D_COMP_COMP_DISABLE (1 << 0) 10807 10808/* Pipe WM_LINETIME - watermark line time */ 10809#define _WM_LINETIME_A 0x45270 10810#define _WM_LINETIME_B 0x45274 10811#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 10812#define HSW_LINETIME_MASK REG_GENMASK(8, 0) 10813#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 10814#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 10815#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 10816 10817/* SFUSE_STRAP */ 10818#define SFUSE_STRAP _MMIO(0xc2014) 10819#define SFUSE_STRAP_FUSE_LOCK (1 << 13) 10820#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 10821#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 10822#define SFUSE_STRAP_CRT_DISABLED (1 << 6) 10823#define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 10824#define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 10825#define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 10826#define SFUSE_STRAP_DDID_DETECTED (1 << 0) 10827 10828#define WM_MISC _MMIO(0x45260) 10829#define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 10830 10831#define WM_DBG _MMIO(0x45280) 10832#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 10833#define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 10834#define WM_DBG_DISALLOW_SPRITE (1 << 2) 10835 10836/* pipe CSC */ 10837#define _PIPE_A_CSC_COEFF_RY_GY 0x49010 10838#define _PIPE_A_CSC_COEFF_BY 0x49014 10839#define _PIPE_A_CSC_COEFF_RU_GU 0x49018 10840#define _PIPE_A_CSC_COEFF_BU 0x4901c 10841#define _PIPE_A_CSC_COEFF_RV_GV 0x49020 10842#define _PIPE_A_CSC_COEFF_BV 0x49024 10843 10844#define _PIPE_A_CSC_MODE 0x49028 10845#define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 10846#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 10847#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 10848#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 10849#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 10850 10851#define _PIPE_A_CSC_PREOFF_HI 0x49030 10852#define _PIPE_A_CSC_PREOFF_ME 0x49034 10853#define _PIPE_A_CSC_PREOFF_LO 0x49038 10854#define _PIPE_A_CSC_POSTOFF_HI 0x49040 10855#define _PIPE_A_CSC_POSTOFF_ME 0x49044 10856#define _PIPE_A_CSC_POSTOFF_LO 0x49048 10857 10858#define _PIPE_B_CSC_COEFF_RY_GY 0x49110 10859#define _PIPE_B_CSC_COEFF_BY 0x49114 10860#define _PIPE_B_CSC_COEFF_RU_GU 0x49118 10861#define _PIPE_B_CSC_COEFF_BU 0x4911c 10862#define _PIPE_B_CSC_COEFF_RV_GV 0x49120 10863#define _PIPE_B_CSC_COEFF_BV 0x49124 10864#define _PIPE_B_CSC_MODE 0x49128 10865#define _PIPE_B_CSC_PREOFF_HI 0x49130 10866#define _PIPE_B_CSC_PREOFF_ME 0x49134 10867#define _PIPE_B_CSC_PREOFF_LO 0x49138 10868#define _PIPE_B_CSC_POSTOFF_HI 0x49140 10869#define _PIPE_B_CSC_POSTOFF_ME 0x49144 10870#define _PIPE_B_CSC_POSTOFF_LO 0x49148 10871 10872#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 10873#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 10874#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 10875#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 10876#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 10877#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 10878#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 10879#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 10880#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 10881#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 10882#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 10883#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 10884#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 10885 10886/* Pipe Output CSC */ 10887#define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 10888#define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 10889#define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 10890#define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 10891#define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 10892#define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 10893#define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 10894#define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 10895#define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 10896#define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 10897#define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 10898#define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 10899 10900#define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 10901#define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 10902#define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 10903#define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 10904#define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 10905#define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 10906#define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 10907#define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 10908#define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 10909#define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 10910#define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 10911#define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 10912 10913#define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 10914 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 10915 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 10916#define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 10917 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 10918 _PIPE_B_OUTPUT_CSC_COEFF_BY) 10919#define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 10920 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 10921 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 10922#define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 10923 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 10924 _PIPE_B_OUTPUT_CSC_COEFF_BU) 10925#define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 10926 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 10927 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 10928#define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 10929 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 10930 _PIPE_B_OUTPUT_CSC_COEFF_BV) 10931#define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10932 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 10933 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 10934#define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10935 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 10936 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 10937#define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10938 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 10939 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 10940#define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 10941 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 10942 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 10943#define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 10944 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 10945 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 10946#define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 10947 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 10948 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 10949 10950/* pipe degamma/gamma LUTs on IVB+ */ 10951#define _PAL_PREC_INDEX_A 0x4A400 10952#define _PAL_PREC_INDEX_B 0x4AC00 10953#define _PAL_PREC_INDEX_C 0x4B400 10954#define PAL_PREC_10_12_BIT (0 << 31) 10955#define PAL_PREC_SPLIT_MODE (1 << 31) 10956#define PAL_PREC_AUTO_INCREMENT (1 << 15) 10957#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 10958#define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 10959#define _PAL_PREC_DATA_A 0x4A404 10960#define _PAL_PREC_DATA_B 0x4AC04 10961#define _PAL_PREC_DATA_C 0x4B404 10962#define _PAL_PREC_GC_MAX_A 0x4A410 10963#define _PAL_PREC_GC_MAX_B 0x4AC10 10964#define _PAL_PREC_GC_MAX_C 0x4B410 10965#define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 10966#define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 10967#define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 10968#define _PAL_PREC_EXT_GC_MAX_A 0x4A420 10969#define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 10970#define _PAL_PREC_EXT_GC_MAX_C 0x4B420 10971#define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 10972#define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 10973#define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 10974 10975#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 10976#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 10977#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 10978#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 10979#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 10980 10981#define _PRE_CSC_GAMC_INDEX_A 0x4A484 10982#define _PRE_CSC_GAMC_INDEX_B 0x4AC84 10983#define _PRE_CSC_GAMC_INDEX_C 0x4B484 10984#define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 10985#define _PRE_CSC_GAMC_DATA_A 0x4A488 10986#define _PRE_CSC_GAMC_DATA_B 0x4AC88 10987#define _PRE_CSC_GAMC_DATA_C 0x4B488 10988 10989#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 10990#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 10991 10992/* ICL Multi segmented gamma */ 10993#define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 10994#define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 10995#define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 10996#define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 10997 10998#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 10999#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 11000#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 11001#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 11002#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 11003#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 11004#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 11005#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 11006 11007#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 11008 _PAL_PREC_MULTI_SEG_INDEX_A, \ 11009 _PAL_PREC_MULTI_SEG_INDEX_B) 11010#define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 11011 _PAL_PREC_MULTI_SEG_DATA_A, \ 11012 _PAL_PREC_MULTI_SEG_DATA_B) 11013 11014/* pipe CSC & degamma/gamma LUTs on CHV */ 11015#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 11016#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 11017#define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 11018#define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 11019#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 11020#define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 11021#define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 11022#define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 11023#define CGM_PIPE_MODE_GAMMA (1 << 2) 11024#define CGM_PIPE_MODE_CSC (1 << 1) 11025#define CGM_PIPE_MODE_DEGAMMA (1 << 0) 11026#define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 11027#define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 11028#define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 11029 11030#define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 11031#define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 11032#define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 11033#define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 11034#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 11035#define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 11036#define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 11037#define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 11038 11039#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 11040#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 11041#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 11042#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 11043#define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 11044#define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 11045#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 11046#define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 11047 11048/* MIPI DSI registers */ 11049 11050#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */ 11051#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c)) 11052 11053/* Gen11 DSI */ 11054#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ 11055 dsi0, dsi1) 11056 11057#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004) 11058#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF 11059#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008) 11060#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF 11061 11062#define _ICL_DSI_ESC_CLK_DIV0 0x6b090 11063#define _ICL_DSI_ESC_CLK_DIV1 0x6b890 11064#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 11065 _ICL_DSI_ESC_CLK_DIV0, \ 11066 _ICL_DSI_ESC_CLK_DIV1) 11067#define _ICL_DPHY_ESC_CLK_DIV0 0x162190 11068#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 11069#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ 11070 _ICL_DPHY_ESC_CLK_DIV0, \ 11071 _ICL_DPHY_ESC_CLK_DIV1) 11072#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) 11073#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 11074#define ICL_ESC_CLK_DIV_MASK 0x1ff 11075#define ICL_ESC_CLK_DIV_SHIFT 0 11076#define DSI_MAX_ESC_CLK 20000 /* in KHz */ 11077 11078#define _DSI_CMD_FRMCTL_0 0x6b034 11079#define _DSI_CMD_FRMCTL_1 0x6b834 11080#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \ 11081 _DSI_CMD_FRMCTL_0,\ 11082 _DSI_CMD_FRMCTL_1) 11083#define DSI_FRAME_UPDATE_REQUEST (1 << 31) 11084#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29) 11085#define DSI_NULL_PACKET_ENABLE (1 << 28) 11086#define DSI_FRAME_IN_PROGRESS (1 << 0) 11087 11088#define _DSI_INTR_MASK_REG_0 0x6b070 11089#define _DSI_INTR_MASK_REG_1 0x6b870 11090#define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \ 11091 _DSI_INTR_MASK_REG_0,\ 11092 _DSI_INTR_MASK_REG_1) 11093 11094#define _DSI_INTR_IDENT_REG_0 0x6b074 11095#define _DSI_INTR_IDENT_REG_1 0x6b874 11096#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \ 11097 _DSI_INTR_IDENT_REG_0,\ 11098 _DSI_INTR_IDENT_REG_1) 11099#define DSI_TE_EVENT (1 << 31) 11100#define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30) 11101#define DSI_TX_DATA (1 << 29) 11102#define DSI_ULPS_ENTRY_DONE (1 << 28) 11103#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27) 11104#define DSI_HOST_CHKSUM_ERROR (1 << 26) 11105#define DSI_HOST_MULTI_ECC_ERROR (1 << 25) 11106#define DSI_HOST_SINGL_ECC_ERROR (1 << 24) 11107#define DSI_HOST_CONTENTION_DETECTED (1 << 23) 11108#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22) 11109#define DSI_HOST_TIMEOUT_ERROR (1 << 21) 11110#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20) 11111#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19) 11112#define DSI_FRAME_UPDATE_DONE (1 << 16) 11113#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15) 11114#define DSI_INVALID_TX_LENGTH (1 << 13) 11115#define DSI_INVALID_VC (1 << 12) 11116#define DSI_INVALID_DATA_TYPE (1 << 11) 11117#define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10) 11118#define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9) 11119#define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8) 11120#define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7) 11121#define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6) 11122#define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5) 11123#define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4) 11124#define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3) 11125#define DSI_EOT_SYNC_ERROR (1 << 2) 11126#define DSI_SOT_SYNC_ERROR (1 << 1) 11127#define DSI_SOT_ERROR (1 << 0) 11128 11129/* Gen4+ Timestamp and Pipe Frame time stamp registers */ 11130#define GEN4_TIMESTAMP _MMIO(0x2358) 11131#define ILK_TIMESTAMP_HI _MMIO(0x70070) 11132#define IVB_TIMESTAMP_CTR _MMIO(0x44070) 11133 11134#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 11135#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 11136#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 11137#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 11138#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 11139 11140#define _PIPE_FRMTMSTMP_A 0x70048 11141#define PIPE_FRMTMSTMP(pipe) \ 11142 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 11143 11144/* BXT MIPI clock controls */ 11145#define BXT_MAX_VAR_OUTPUT_KHZ 39500 11146 11147#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090) 11148#define BXT_MIPI1_DIV_SHIFT 26 11149#define BXT_MIPI2_DIV_SHIFT 10 11150#define BXT_MIPI_DIV_SHIFT(port) \ 11151 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \ 11152 BXT_MIPI2_DIV_SHIFT) 11153 11154/* TX control divider to select actual TX clock output from (8x/var) */ 11155#define BXT_MIPI1_TX_ESCLK_SHIFT 26 11156#define BXT_MIPI2_TX_ESCLK_SHIFT 10 11157#define BXT_MIPI_TX_ESCLK_SHIFT(port) \ 11158 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \ 11159 BXT_MIPI2_TX_ESCLK_SHIFT) 11160#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (0x3F << 26) 11161#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (0x3F << 10) 11162#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \ 11163 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \ 11164 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK) 11165#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \ 11166 (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port)) 11167/* RX upper control divider to select actual RX clock output from 8x */ 11168#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT 21 11169#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT 5 11170#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \ 11171 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \ 11172 BXT_MIPI2_RX_ESCLK_UPPER_SHIFT) 11173#define BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 21) 11174#define BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK (3 << 5) 11175#define BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port) \ 11176 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK, \ 11177 BXT_MIPI2_RX_ESCLK_UPPER_FIXDIV_MASK) 11178#define BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, val) \ 11179 (((val) & 3) << BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)) 11180/* 8/3X divider to select the actual 8/3X clock output from 8x */ 11181#define BXT_MIPI1_8X_BY3_SHIFT 19 11182#define BXT_MIPI2_8X_BY3_SHIFT 3 11183#define BXT_MIPI_8X_BY3_SHIFT(port) \ 11184 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_SHIFT, \ 11185 BXT_MIPI2_8X_BY3_SHIFT) 11186#define BXT_MIPI1_8X_BY3_DIVIDER_MASK (3 << 19) 11187#define BXT_MIPI2_8X_BY3_DIVIDER_MASK (3 << 3) 11188#define BXT_MIPI_8X_BY3_DIVIDER_MASK(port) \ 11189 _MIPI_PORT(port, BXT_MIPI1_8X_BY3_DIVIDER_MASK, \ 11190 BXT_MIPI2_8X_BY3_DIVIDER_MASK) 11191#define BXT_MIPI_8X_BY3_DIVIDER(port, val) \ 11192 (((val) & 3) << BXT_MIPI_8X_BY3_SHIFT(port)) 11193/* RX lower control divider to select actual RX clock output from 8x */ 11194#define BXT_MIPI1_RX_ESCLK_LOWER_SHIFT 16 11195#define BXT_MIPI2_RX_ESCLK_LOWER_SHIFT 0 11196#define BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port) \ 11197 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_SHIFT, \ 11198 BXT_MIPI2_RX_ESCLK_LOWER_SHIFT) 11199#define BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 16) 11200#define BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK (3 << 0) 11201#define BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port) \ 11202 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_LOWER_FIXDIV_MASK, \ 11203 BXT_MIPI2_RX_ESCLK_LOWER_FIXDIV_MASK) 11204#define BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, val) \ 11205 (((val) & 3) << BXT_MIPI_RX_ESCLK_LOWER_SHIFT(port)) 11206 11207#define RX_DIVIDER_BIT_1_2 0x3 11208#define RX_DIVIDER_BIT_3_4 0xC 11209 11210/* BXT MIPI mode configure */ 11211#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8 11212#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8 11213#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \ 11214 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE) 11215 11216#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC 11217#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC 11218#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \ 11219 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE) 11220 11221#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100 11222#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900 11223#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \ 11224 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL) 11225 11226#define BXT_DSI_PLL_CTL _MMIO(0x161000) 11227#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16 11228#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 11229#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT) 11230#define BXT_DSIC_16X_BY1 (0 << 10) 11231#define BXT_DSIC_16X_BY2 (1 << 10) 11232#define BXT_DSIC_16X_BY3 (2 << 10) 11233#define BXT_DSIC_16X_BY4 (3 << 10) 11234#define BXT_DSIC_16X_MASK (3 << 10) 11235#define BXT_DSIA_16X_BY1 (0 << 8) 11236#define BXT_DSIA_16X_BY2 (1 << 8) 11237#define BXT_DSIA_16X_BY3 (2 << 8) 11238#define BXT_DSIA_16X_BY4 (3 << 8) 11239#define BXT_DSIA_16X_MASK (3 << 8) 11240#define BXT_DSI_FREQ_SEL_SHIFT 8 11241#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT) 11242 11243#define BXT_DSI_PLL_RATIO_MAX 0x7D 11244#define BXT_DSI_PLL_RATIO_MIN 0x22 11245#define GLK_DSI_PLL_RATIO_MAX 0x6F 11246#define GLK_DSI_PLL_RATIO_MIN 0x22 11247#define BXT_DSI_PLL_RATIO_MASK 0xFF 11248#define BXT_REF_CLOCK_KHZ 19200 11249 11250#define BXT_DSI_PLL_ENABLE _MMIO(0x46080) 11251#define BXT_DSI_PLL_DO_ENABLE (1 << 31) 11252#define BXT_DSI_PLL_LOCKED (1 << 30) 11253 11254#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 11255#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 11256#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL) 11257 11258 /* BXT port control */ 11259#define _BXT_MIPIA_PORT_CTRL 0x6B0C0 11260#define _BXT_MIPIC_PORT_CTRL 0x6B8C0 11261#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL) 11262 11263/* ICL DSI MODE control */ 11264#define _ICL_DSI_IO_MODECTL_0 0x6B094 11265#define _ICL_DSI_IO_MODECTL_1 0x6B894 11266#define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ 11267 _ICL_DSI_IO_MODECTL_0, \ 11268 _ICL_DSI_IO_MODECTL_1) 11269#define COMBO_PHY_MODE_DSI (1 << 0) 11270 11271/* Display Stream Splitter Control */ 11272#define DSS_CTL1 _MMIO(0x67400) 11273#define SPLITTER_ENABLE (1 << 31) 11274#define JOINER_ENABLE (1 << 30) 11275#define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 11276#define DUAL_LINK_MODE_FRONTBACK (0 << 24) 11277#define OVERLAP_PIXELS_MASK (0xf << 16) 11278#define OVERLAP_PIXELS(pixels) ((pixels) << 16) 11279#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 11280#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 11281#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 11282 11283#define DSS_CTL2 _MMIO(0x67404) 11284#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 11285#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 11286#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 11287#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 11288 11289#define _ICL_PIPE_DSS_CTL1_PB 0x78200 11290#define _ICL_PIPE_DSS_CTL1_PC 0x78400 11291#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11292 _ICL_PIPE_DSS_CTL1_PB, \ 11293 _ICL_PIPE_DSS_CTL1_PC) 11294#define BIG_JOINER_ENABLE (1 << 29) 11295#define MASTER_BIG_JOINER_ENABLE (1 << 28) 11296#define VGA_CENTERING_ENABLE (1 << 27) 11297 11298#define _ICL_PIPE_DSS_CTL2_PB 0x78204 11299#define _ICL_PIPE_DSS_CTL2_PC 0x78404 11300#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 11301 _ICL_PIPE_DSS_CTL2_PB, \ 11302 _ICL_PIPE_DSS_CTL2_PC) 11303 11304#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020) 11305#define STAP_SELECT (1 << 0) 11306 11307#define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054) 11308#define HS_IO_CTRL_SELECT (1 << 0) 11309 11310#define DPI_ENABLE (1 << 31) /* A + C */ 11311#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 11312#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 11313#define DUAL_LINK_MODE_SHIFT 26 11314#define DUAL_LINK_MODE_MASK (1 << 26) 11315#define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 11316#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 11317#define DITHERING_ENABLE (1 << 25) /* A + C */ 11318#define FLOPPED_HSTX (1 << 23) 11319#define DE_INVERT (1 << 19) /* XXX */ 11320#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 11321#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 11322#define AFE_LATCHOUT (1 << 17) 11323#define LP_OUTPUT_HOLD (1 << 16) 11324#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 11325#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 11326#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11 11327#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 11328#define CSB_SHIFT 9 11329#define CSB_MASK (3 << 9) 11330#define CSB_20MHZ (0 << 9) 11331#define CSB_10MHZ (1 << 9) 11332#define CSB_40MHZ (2 << 9) 11333#define BANDGAP_MASK (1 << 8) 11334#define BANDGAP_PNW_CIRCUIT (0 << 8) 11335#define BANDGAP_LNC_CIRCUIT (1 << 8) 11336#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 11337#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 11338#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */ 11339#define TEARING_EFFECT_SHIFT 2 /* A + C */ 11340#define TEARING_EFFECT_MASK (3 << 2) 11341#define TEARING_EFFECT_OFF (0 << 2) 11342#define TEARING_EFFECT_DSI (1 << 2) 11343#define TEARING_EFFECT_GPIO (2 << 2) 11344#define LANE_CONFIGURATION_SHIFT 0 11345#define LANE_CONFIGURATION_MASK (3 << 0) 11346#define LANE_CONFIGURATION_4LANE (0 << 0) 11347#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 11348#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 11349 11350#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 11351#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 11352#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) 11353#define TEARING_EFFECT_DELAY_SHIFT 0 11354#define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 11355 11356/* XXX: all bits reserved */ 11357#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 11358 11359/* MIPI DSI Controller and D-PHY registers */ 11360 11361#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 11362#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 11363#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY) 11364#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 11365#define ULPS_STATE_MASK (3 << 1) 11366#define ULPS_STATE_ENTER (2 << 1) 11367#define ULPS_STATE_EXIT (1 << 1) 11368#define ULPS_STATE_NORMAL_OPERATION (0 << 1) 11369#define DEVICE_READY (1 << 0) 11370 11371#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 11372#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 11373#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT) 11374#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 11375#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 11376#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN) 11377#define TEARING_EFFECT (1 << 31) 11378#define SPL_PKT_SENT_INTERRUPT (1 << 30) 11379#define GEN_READ_DATA_AVAIL (1 << 29) 11380#define LP_GENERIC_WR_FIFO_FULL (1 << 28) 11381#define HS_GENERIC_WR_FIFO_FULL (1 << 27) 11382#define RX_PROT_VIOLATION (1 << 26) 11383#define RX_INVALID_TX_LENGTH (1 << 25) 11384#define ACK_WITH_NO_ERROR (1 << 24) 11385#define TURN_AROUND_ACK_TIMEOUT (1 << 23) 11386#define LP_RX_TIMEOUT (1 << 22) 11387#define HS_TX_TIMEOUT (1 << 21) 11388#define DPI_FIFO_UNDERRUN (1 << 20) 11389#define LOW_CONTENTION (1 << 19) 11390#define HIGH_CONTENTION (1 << 18) 11391#define TXDSI_VC_ID_INVALID (1 << 17) 11392#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 11393#define TXCHECKSUM_ERROR (1 << 15) 11394#define TXECC_MULTIBIT_ERROR (1 << 14) 11395#define TXECC_SINGLE_BIT_ERROR (1 << 13) 11396#define TXFALSE_CONTROL_ERROR (1 << 12) 11397#define RXDSI_VC_ID_INVALID (1 << 11) 11398#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 11399#define RXCHECKSUM_ERROR (1 << 9) 11400#define RXECC_MULTIBIT_ERROR (1 << 8) 11401#define RXECC_SINGLE_BIT_ERROR (1 << 7) 11402#define RXFALSE_CONTROL_ERROR (1 << 6) 11403#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 11404#define RX_LP_TX_SYNC_ERROR (1 << 4) 11405#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 11406#define RXEOT_SYNC_ERROR (1 << 2) 11407#define RXSOT_SYNC_ERROR (1 << 1) 11408#define RXSOT_ERROR (1 << 0) 11409 11410#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 11411#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 11412#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG) 11413#define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 11414#define CMD_MODE_NOT_SUPPORTED (0 << 13) 11415#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 11416#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 11417#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 11418#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 11419#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 11420#define VID_MODE_FORMAT_MASK (0xf << 7) 11421#define VID_MODE_NOT_SUPPORTED (0 << 7) 11422#define VID_MODE_FORMAT_RGB565 (1 << 7) 11423#define VID_MODE_FORMAT_RGB666_PACKED (2 << 7) 11424#define VID_MODE_FORMAT_RGB666 (3 << 7) 11425#define VID_MODE_FORMAT_RGB888 (4 << 7) 11426#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 11427#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 11428#define VID_MODE_CHANNEL_NUMBER_SHIFT 3 11429#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 11430#define DATA_LANES_PRG_REG_SHIFT 0 11431#define DATA_LANES_PRG_REG_MASK (7 << 0) 11432 11433#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 11434#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 11435#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT) 11436#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 11437 11438#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 11439#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 11440#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT) 11441#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 11442 11443#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 11444#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 11445#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) 11446#define TURN_AROUND_TIMEOUT_MASK 0x3f 11447 11448#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 11449#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 11450#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) 11451#define DEVICE_RESET_TIMER_MASK 0xffff 11452 11453#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 11454#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 11455#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) 11456#define VERTICAL_ADDRESS_SHIFT 16 11457#define VERTICAL_ADDRESS_MASK (0xffff << 16) 11458#define HORIZONTAL_ADDRESS_SHIFT 0 11459#define HORIZONTAL_ADDRESS_MASK 0xffff 11460 11461#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 11462#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 11463#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) 11464#define DBI_FIFO_EMPTY_HALF (0 << 0) 11465#define DBI_FIFO_EMPTY_QUARTER (1 << 0) 11466#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 11467 11468/* regs below are bits 15:0 */ 11469#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 11470#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 11471#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) 11472 11473#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 11474#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 11475#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT) 11476 11477#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 11478#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 11479#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT) 11480 11481#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 11482#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 11483#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) 11484 11485#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 11486#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 11487#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) 11488 11489#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 11490#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 11491#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT) 11492 11493#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 11494#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 11495#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT) 11496 11497#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 11498#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 11499#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) 11500 11501/* regs above are bits 15:0 */ 11502 11503#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 11504#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 11505#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL) 11506#define DPI_LP_MODE (1 << 6) 11507#define BACKLIGHT_OFF (1 << 5) 11508#define BACKLIGHT_ON (1 << 4) 11509#define COLOR_MODE_OFF (1 << 3) 11510#define COLOR_MODE_ON (1 << 2) 11511#define TURN_ON (1 << 1) 11512#define SHUTDOWN (1 << 0) 11513 11514#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 11515#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 11516#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA) 11517#define COMMAND_BYTE_SHIFT 0 11518#define COMMAND_BYTE_MASK (0x3f << 0) 11519 11520#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 11521#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 11522#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT) 11523#define MASTER_INIT_TIMER_SHIFT 0 11524#define MASTER_INIT_TIMER_MASK (0xffff << 0) 11525 11526#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 11527#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 11528#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \ 11529 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE) 11530#define MAX_RETURN_PKT_SIZE_SHIFT 0 11531#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 11532 11533#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 11534#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 11535#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) 11536#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 11537#define DISABLE_VIDEO_BTA (1 << 3) 11538#define IP_TG_CONFIG (1 << 2) 11539#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 11540#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 11541#define VIDEO_MODE_BURST (3 << 0) 11542 11543#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 11544#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 11545#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE) 11546#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9) 11547#define BXT_DPHY_DEFEATURE_EN (1 << 8) 11548#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 11549#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 11550#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 11551#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 11552#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 11553#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 11554#define CLOCKSTOP (1 << 1) 11555#define EOT_DISABLE (1 << 0) 11556 11557#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 11558#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 11559#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK) 11560#define LP_BYTECLK_SHIFT 0 11561#define LP_BYTECLK_MASK (0xffff << 0) 11562 11563#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4) 11564#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4) 11565#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) 11566 11567#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098) 11568#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898) 11569#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) 11570 11571/* bits 31:0 */ 11572#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 11573#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 11574#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA) 11575 11576/* bits 31:0 */ 11577#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 11578#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 11579#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA) 11580 11581#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 11582#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 11583#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL) 11584#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 11585#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 11586#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL) 11587#define LONG_PACKET_WORD_COUNT_SHIFT 8 11588#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 11589#define SHORT_PACKET_PARAM_SHIFT 8 11590#define SHORT_PACKET_PARAM_MASK (0xffff << 8) 11591#define VIRTUAL_CHANNEL_SHIFT 6 11592#define VIRTUAL_CHANNEL_MASK (3 << 6) 11593#define DATA_TYPE_SHIFT 0 11594#define DATA_TYPE_MASK (0x3f << 0) 11595/* data type values, see include/video/mipi_display.h */ 11596 11597#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 11598#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 11599#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT) 11600#define DPI_FIFO_EMPTY (1 << 28) 11601#define DBI_FIFO_EMPTY (1 << 27) 11602#define LP_CTRL_FIFO_EMPTY (1 << 26) 11603#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 11604#define LP_CTRL_FIFO_FULL (1 << 24) 11605#define HS_CTRL_FIFO_EMPTY (1 << 18) 11606#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 11607#define HS_CTRL_FIFO_FULL (1 << 16) 11608#define LP_DATA_FIFO_EMPTY (1 << 10) 11609#define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 11610#define LP_DATA_FIFO_FULL (1 << 8) 11611#define HS_DATA_FIFO_EMPTY (1 << 2) 11612#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 11613#define HS_DATA_FIFO_FULL (1 << 0) 11614 11615#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 11616#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 11617#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) 11618#define DBI_HS_LP_MODE_MASK (1 << 0) 11619#define DBI_LP_MODE (1 << 0) 11620#define DBI_HS_MODE (0 << 0) 11621 11622#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 11623#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 11624#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM) 11625#define EXIT_ZERO_COUNT_SHIFT 24 11626#define EXIT_ZERO_COUNT_MASK (0x3f << 24) 11627#define TRAIL_COUNT_SHIFT 16 11628#define TRAIL_COUNT_MASK (0x1f << 16) 11629#define CLK_ZERO_COUNT_SHIFT 8 11630#define CLK_ZERO_COUNT_MASK (0xff << 8) 11631#define PREPARE_COUNT_SHIFT 0 11632#define PREPARE_COUNT_MASK (0x3f << 0) 11633 11634#define _ICL_DSI_T_INIT_MASTER_0 0x6b088 11635#define _ICL_DSI_T_INIT_MASTER_1 0x6b888 11636#define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ 11637 _ICL_DSI_T_INIT_MASTER_0,\ 11638 _ICL_DSI_T_INIT_MASTER_1) 11639 11640#define _DPHY_CLK_TIMING_PARAM_0 0x162180 11641#define _DPHY_CLK_TIMING_PARAM_1 0x6c180 11642#define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 11643 _DPHY_CLK_TIMING_PARAM_0,\ 11644 _DPHY_CLK_TIMING_PARAM_1) 11645#define _DSI_CLK_TIMING_PARAM_0 0x6b080 11646#define _DSI_CLK_TIMING_PARAM_1 0x6b880 11647#define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ 11648 _DSI_CLK_TIMING_PARAM_0,\ 11649 _DSI_CLK_TIMING_PARAM_1) 11650#define CLK_PREPARE_OVERRIDE (1 << 31) 11651#define CLK_PREPARE(x) ((x) << 28) 11652#define CLK_PREPARE_MASK (0x7 << 28) 11653#define CLK_PREPARE_SHIFT 28 11654#define CLK_ZERO_OVERRIDE (1 << 27) 11655#define CLK_ZERO(x) ((x) << 20) 11656#define CLK_ZERO_MASK (0xf << 20) 11657#define CLK_ZERO_SHIFT 20 11658#define CLK_PRE_OVERRIDE (1 << 19) 11659#define CLK_PRE(x) ((x) << 16) 11660#define CLK_PRE_MASK (0x3 << 16) 11661#define CLK_PRE_SHIFT 16 11662#define CLK_POST_OVERRIDE (1 << 15) 11663#define CLK_POST(x) ((x) << 8) 11664#define CLK_POST_MASK (0x7 << 8) 11665#define CLK_POST_SHIFT 8 11666#define CLK_TRAIL_OVERRIDE (1 << 7) 11667#define CLK_TRAIL(x) ((x) << 0) 11668#define CLK_TRAIL_MASK (0xf << 0) 11669#define CLK_TRAIL_SHIFT 0 11670 11671#define _DPHY_DATA_TIMING_PARAM_0 0x162184 11672#define _DPHY_DATA_TIMING_PARAM_1 0x6c184 11673#define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11674 _DPHY_DATA_TIMING_PARAM_0,\ 11675 _DPHY_DATA_TIMING_PARAM_1) 11676#define _DSI_DATA_TIMING_PARAM_0 0x6B084 11677#define _DSI_DATA_TIMING_PARAM_1 0x6B884 11678#define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11679 _DSI_DATA_TIMING_PARAM_0,\ 11680 _DSI_DATA_TIMING_PARAM_1) 11681#define HS_PREPARE_OVERRIDE (1 << 31) 11682#define HS_PREPARE(x) ((x) << 24) 11683#define HS_PREPARE_MASK (0x7 << 24) 11684#define HS_PREPARE_SHIFT 24 11685#define HS_ZERO_OVERRIDE (1 << 23) 11686#define HS_ZERO(x) ((x) << 16) 11687#define HS_ZERO_MASK (0xf << 16) 11688#define HS_ZERO_SHIFT 16 11689#define HS_TRAIL_OVERRIDE (1 << 15) 11690#define HS_TRAIL(x) ((x) << 8) 11691#define HS_TRAIL_MASK (0x7 << 8) 11692#define HS_TRAIL_SHIFT 8 11693#define HS_EXIT_OVERRIDE (1 << 7) 11694#define HS_EXIT(x) ((x) << 0) 11695#define HS_EXIT_MASK (0x7 << 0) 11696#define HS_EXIT_SHIFT 0 11697 11698#define _DPHY_TA_TIMING_PARAM_0 0x162188 11699#define _DPHY_TA_TIMING_PARAM_1 0x6c188 11700#define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11701 _DPHY_TA_TIMING_PARAM_0,\ 11702 _DPHY_TA_TIMING_PARAM_1) 11703#define _DSI_TA_TIMING_PARAM_0 0x6b098 11704#define _DSI_TA_TIMING_PARAM_1 0x6b898 11705#define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ 11706 _DSI_TA_TIMING_PARAM_0,\ 11707 _DSI_TA_TIMING_PARAM_1) 11708#define TA_SURE_OVERRIDE (1 << 31) 11709#define TA_SURE(x) ((x) << 16) 11710#define TA_SURE_MASK (0x1f << 16) 11711#define TA_SURE_SHIFT 16 11712#define TA_GO_OVERRIDE (1 << 15) 11713#define TA_GO(x) ((x) << 8) 11714#define TA_GO_MASK (0xf << 8) 11715#define TA_GO_SHIFT 8 11716#define TA_GET_OVERRIDE (1 << 7) 11717#define TA_GET(x) ((x) << 0) 11718#define TA_GET_MASK (0xf << 0) 11719#define TA_GET_SHIFT 0 11720 11721/* DSI transcoder configuration */ 11722#define _DSI_TRANS_FUNC_CONF_0 0x6b030 11723#define _DSI_TRANS_FUNC_CONF_1 0x6b830 11724#define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ 11725 _DSI_TRANS_FUNC_CONF_0,\ 11726 _DSI_TRANS_FUNC_CONF_1) 11727#define OP_MODE_MASK (0x3 << 28) 11728#define OP_MODE_SHIFT 28 11729#define CMD_MODE_NO_GATE (0x0 << 28) 11730#define CMD_MODE_TE_GATE (0x1 << 28) 11731#define VIDEO_MODE_SYNC_EVENT (0x2 << 28) 11732#define VIDEO_MODE_SYNC_PULSE (0x3 << 28) 11733#define TE_SOURCE_GPIO (1 << 27) 11734#define LINK_READY (1 << 20) 11735#define PIX_FMT_MASK (0x3 << 16) 11736#define PIX_FMT_SHIFT 16 11737#define PIX_FMT_RGB565 (0x0 << 16) 11738#define PIX_FMT_RGB666_PACKED (0x1 << 16) 11739#define PIX_FMT_RGB666_LOOSE (0x2 << 16) 11740#define PIX_FMT_RGB888 (0x3 << 16) 11741#define PIX_FMT_RGB101010 (0x4 << 16) 11742#define PIX_FMT_RGB121212 (0x5 << 16) 11743#define PIX_FMT_COMPRESSED (0x6 << 16) 11744#define BGR_TRANSMISSION (1 << 15) 11745#define PIX_VIRT_CHAN(x) ((x) << 12) 11746#define PIX_VIRT_CHAN_MASK (0x3 << 12) 11747#define PIX_VIRT_CHAN_SHIFT 12 11748#define PIX_BUF_THRESHOLD_MASK (0x3 << 10) 11749#define PIX_BUF_THRESHOLD_SHIFT 10 11750#define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) 11751#define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) 11752#define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) 11753#define PIX_BUF_THRESHOLD_FULL (0x3 << 10) 11754#define CONTINUOUS_CLK_MASK (0x3 << 8) 11755#define CONTINUOUS_CLK_SHIFT 8 11756#define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) 11757#define CLK_HS_OR_LP (0x2 << 8) 11758#define CLK_HS_CONTINUOUS (0x3 << 8) 11759#define LINK_CALIBRATION_MASK (0x3 << 4) 11760#define LINK_CALIBRATION_SHIFT 4 11761#define CALIBRATION_DISABLED (0x0 << 4) 11762#define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) 11763#define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) 11764#define BLANKING_PACKET_ENABLE (1 << 2) 11765#define S3D_ORIENTATION_LANDSCAPE (1 << 1) 11766#define EOTP_DISABLED (1 << 0) 11767 11768#define _DSI_CMD_RXCTL_0 0x6b0d4 11769#define _DSI_CMD_RXCTL_1 0x6b8d4 11770#define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ 11771 _DSI_CMD_RXCTL_0,\ 11772 _DSI_CMD_RXCTL_1) 11773#define READ_UNLOADS_DW (1 << 16) 11774#define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) 11775#define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) 11776#define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) 11777#define RECEIVED_RESET_TRIGGER (1 << 12) 11778#define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) 11779#define RECEIVED_CRC_WAS_LOST (1 << 10) 11780#define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) 11781#define NUMBER_RX_PLOAD_DW_SHIFT 0 11782 11783#define _DSI_CMD_TXCTL_0 0x6b0d0 11784#define _DSI_CMD_TXCTL_1 0x6b8d0 11785#define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ 11786 _DSI_CMD_TXCTL_0,\ 11787 _DSI_CMD_TXCTL_1) 11788#define KEEP_LINK_IN_HS (1 << 24) 11789#define FREE_HEADER_CREDIT_MASK (0x1f << 8) 11790#define FREE_HEADER_CREDIT_SHIFT 0x8 11791#define FREE_PLOAD_CREDIT_MASK (0xff << 0) 11792#define FREE_PLOAD_CREDIT_SHIFT 0 11793#define MAX_HEADER_CREDIT 0x10 11794#define MAX_PLOAD_CREDIT 0x40 11795 11796#define _DSI_CMD_TXHDR_0 0x6b100 11797#define _DSI_CMD_TXHDR_1 0x6b900 11798#define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ 11799 _DSI_CMD_TXHDR_0,\ 11800 _DSI_CMD_TXHDR_1) 11801#define PAYLOAD_PRESENT (1 << 31) 11802#define LP_DATA_TRANSFER (1 << 30) 11803#define VBLANK_FENCE (1 << 29) 11804#define PARAM_WC_MASK (0xffff << 8) 11805#define PARAM_WC_LOWER_SHIFT 8 11806#define PARAM_WC_UPPER_SHIFT 16 11807#define VC_MASK (0x3 << 6) 11808#define VC_SHIFT 6 11809#define DT_MASK (0x3f << 0) 11810#define DT_SHIFT 0 11811 11812#define _DSI_CMD_TXPYLD_0 0x6b104 11813#define _DSI_CMD_TXPYLD_1 0x6b904 11814#define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ 11815 _DSI_CMD_TXPYLD_0,\ 11816 _DSI_CMD_TXPYLD_1) 11817 11818#define _DSI_LP_MSG_0 0x6b0d8 11819#define _DSI_LP_MSG_1 0x6b8d8 11820#define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ 11821 _DSI_LP_MSG_0,\ 11822 _DSI_LP_MSG_1) 11823#define LPTX_IN_PROGRESS (1 << 17) 11824#define LINK_IN_ULPS (1 << 16) 11825#define LINK_ULPS_TYPE_LP11 (1 << 8) 11826#define LINK_ENTER_ULPS (1 << 0) 11827 11828/* DSI timeout registers */ 11829#define _DSI_HSTX_TO_0 0x6b044 11830#define _DSI_HSTX_TO_1 0x6b844 11831#define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ 11832 _DSI_HSTX_TO_0,\ 11833 _DSI_HSTX_TO_1) 11834#define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) 11835#define HSTX_TIMEOUT_VALUE_SHIFT 16 11836#define HSTX_TIMEOUT_VALUE(x) ((x) << 16) 11837#define HSTX_TIMED_OUT (1 << 0) 11838 11839#define _DSI_LPRX_HOST_TO_0 0x6b048 11840#define _DSI_LPRX_HOST_TO_1 0x6b848 11841#define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ 11842 _DSI_LPRX_HOST_TO_0,\ 11843 _DSI_LPRX_HOST_TO_1) 11844#define LPRX_TIMED_OUT (1 << 16) 11845#define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) 11846#define LPRX_TIMEOUT_VALUE_SHIFT 0 11847#define LPRX_TIMEOUT_VALUE(x) ((x) << 0) 11848 11849#define _DSI_PWAIT_TO_0 0x6b040 11850#define _DSI_PWAIT_TO_1 0x6b840 11851#define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ 11852 _DSI_PWAIT_TO_0,\ 11853 _DSI_PWAIT_TO_1) 11854#define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) 11855#define PRESET_TIMEOUT_VALUE_SHIFT 16 11856#define PRESET_TIMEOUT_VALUE(x) ((x) << 16) 11857#define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) 11858#define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 11859#define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) 11860 11861#define _DSI_TA_TO_0 0x6b04c 11862#define _DSI_TA_TO_1 0x6b84c 11863#define DSI_TA_TO(tc) _MMIO_DSI(tc, \ 11864 _DSI_TA_TO_0,\ 11865 _DSI_TA_TO_1) 11866#define TA_TIMED_OUT (1 << 16) 11867#define TA_TIMEOUT_VALUE_MASK (0xffff << 0) 11868#define TA_TIMEOUT_VALUE_SHIFT 0 11869#define TA_TIMEOUT_VALUE(x) ((x) << 0) 11870 11871/* bits 31:0 */ 11872#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 11873#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 11874#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL) 11875 11876#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088) 11877#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888) 11878#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) 11879#define LP_HS_SSW_CNT_SHIFT 16 11880#define LP_HS_SSW_CNT_MASK (0xffff << 16) 11881#define HS_LP_PWR_SW_CNT_SHIFT 0 11882#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 11883 11884#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 11885#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 11886#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) 11887#define STOP_STATE_STALL_COUNTER_SHIFT 0 11888#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 11889 11890#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 11891#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 11892#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) 11893#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 11894#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 11895#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1) 11896#define RX_CONTENTION_DETECTED (1 << 0) 11897 11898/* XXX: only pipe A ?!? */ 11899#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 11900#define DBI_TYPEC_ENABLE (1 << 31) 11901#define DBI_TYPEC_WIP (1 << 30) 11902#define DBI_TYPEC_OPTION_SHIFT 28 11903#define DBI_TYPEC_OPTION_MASK (3 << 28) 11904#define DBI_TYPEC_FREQ_SHIFT 24 11905#define DBI_TYPEC_FREQ_MASK (0xf << 24) 11906#define DBI_TYPEC_OVERRIDE (1 << 8) 11907#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 11908#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 11909 11910 11911/* MIPI adapter registers */ 11912 11913#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 11914#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904) 11915#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL) 11916#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 11917#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 11918#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 11919#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 11920#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 11921#define READ_REQUEST_PRIORITY_SHIFT 3 11922#define READ_REQUEST_PRIORITY_MASK (3 << 3) 11923#define READ_REQUEST_PRIORITY_LOW (0 << 3) 11924#define READ_REQUEST_PRIORITY_HIGH (3 << 3) 11925#define RGB_FLIP_TO_BGR (1 << 2) 11926 11927#define BXT_PIPE_SELECT_SHIFT 7 11928#define BXT_PIPE_SELECT_MASK (7 << 7) 11929#define BXT_PIPE_SELECT(pipe) ((pipe) << 7) 11930#define GLK_PHY_STATUS_PORT_READY (1 << 31) /* RO */ 11931#define GLK_ULPS_NOT_ACTIVE (1 << 30) /* RO */ 11932#define GLK_MIPIIO_RESET_RELEASED (1 << 28) 11933#define GLK_CLOCK_LANE_STOP_STATE (1 << 27) /* RO */ 11934#define GLK_DATA_LANE_STOP_STATE (1 << 26) /* RO */ 11935#define GLK_LP_WAKE (1 << 22) 11936#define GLK_LP11_LOW_PWR_MODE (1 << 21) 11937#define GLK_LP00_LOW_PWR_MODE (1 << 20) 11938#define GLK_FIREWALL_ENABLE (1 << 16) 11939#define BXT_PIXEL_OVERLAP_CNT_MASK (0xf << 10) 11940#define BXT_PIXEL_OVERLAP_CNT_SHIFT 10 11941#define BXT_DSC_ENABLE (1 << 3) 11942#define BXT_RGB_FLIP (1 << 2) 11943#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */ 11944#define GLK_MIPIIO_ENABLE (1 << 0) 11945 11946#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 11947#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 11948#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS) 11949#define DATA_MEM_ADDRESS_SHIFT 5 11950#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 11951#define DATA_VALID (1 << 0) 11952 11953#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 11954#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 11955#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH) 11956#define DATA_LENGTH_SHIFT 0 11957#define DATA_LENGTH_MASK (0xfffff << 0) 11958 11959#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 11960#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 11961#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) 11962#define COMMAND_MEM_ADDRESS_SHIFT 5 11963#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 11964#define AUTO_PWG_ENABLE (1 << 2) 11965#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 11966#define COMMAND_VALID (1 << 0) 11967 11968#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 11969#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 11970#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) 11971#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 11972#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 11973 11974#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 11975#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 11976#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */ 11977 11978#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 11979#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 11980#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID) 11981#define READ_DATA_VALID(n) (1 << (n)) 11982 11983/* MOCS (Memory Object Control State) registers */ 11984#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 11985 11986#define __GEN9_RCS0_MOCS0 0xc800 11987#define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) 11988#define __GEN9_VCS0_MOCS0 0xc900 11989#define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4) 11990#define __GEN9_VCS1_MOCS0 0xca00 11991#define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4) 11992#define __GEN9_VECS0_MOCS0 0xcb00 11993#define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4) 11994#define __GEN9_BCS0_MOCS0 0xcc00 11995#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4) 11996#define __GEN11_VCS2_MOCS0 0x10000 11997#define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) 11998 11999#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0) 12000#define PMFLUSHDONE_LNICRSDROP (1 << 20) 12001#define PMFLUSH_GAPL3UNBLOCK (1 << 21) 12002#define PMFLUSHDONE_LNEBLK (1 << 22) 12003 12004#define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ 12005 12006/* gamt regs */ 12007#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 12008#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 12009#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 12010#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 12011#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 12012 12013#define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 12014#define MMCD_PCLA (1 << 31) 12015#define MMCD_HOTSPOT_EN (1 << 27) 12016 12017#define _ICL_PHY_MISC_A 0x64C00 12018#define _ICL_PHY_MISC_B 0x64C04 12019#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \ 12020 _ICL_PHY_MISC_B) 12021#define ICL_PHY_MISC_MUX_DDID (1 << 28) 12022#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 12023 12024/* Icelake Display Stream Compression Registers */ 12025#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 12026#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 12027#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 12028#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 12029#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 12030#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 12031#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12032 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 12033 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 12034#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12035 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 12036 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 12037#define DSC_VBR_ENABLE (1 << 19) 12038#define DSC_422_ENABLE (1 << 18) 12039#define DSC_COLOR_SPACE_CONVERSION (1 << 17) 12040#define DSC_BLOCK_PREDICTION (1 << 16) 12041#define DSC_LINE_BUF_DEPTH_SHIFT 12 12042#define DSC_BPC_SHIFT 8 12043#define DSC_VER_MIN_SHIFT 4 12044#define DSC_VER_MAJ (0x1 << 0) 12045 12046#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 12047#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 12048#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 12049#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 12050#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 12051#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 12052#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12053 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 12054 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 12055#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12056 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 12057 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 12058#define DSC_BPP(bpp) ((bpp) << 0) 12059 12060#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 12061#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 12062#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 12063#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 12064#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 12065#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 12066#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12067 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 12068 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 12069#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12070 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 12071 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 12072#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 12073#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 12074 12075#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 12076#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 12077#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 12078#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 12079#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 12080#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 12081#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12082 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 12083 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 12084#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12085 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 12086 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 12087#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 12088#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 12089 12090#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 12091#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 12092#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 12093#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 12094#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 12095#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 12096#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12097 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 12098 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 12099#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12100 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 12101 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 12102#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 12103#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 12104 12105#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 12106#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 12107#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 12108#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 12109#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 12110#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 12111#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12112 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 12113 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 12114#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12115 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 12116 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 12117#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 12118#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 12119 12120#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 12121#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 12122#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 12123#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 12124#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 12125#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 12126#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12127 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 12128 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 12129#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12130 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 12131 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 12132#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 12133#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 12134#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 12135#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 12136 12137#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 12138#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 12139#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 12140#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 12141#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 12142#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 12143#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12144 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 12145 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 12146#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12147 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 12148 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 12149#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 12150#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 12151 12152#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 12153#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 12154#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 12155#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 12156#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 12157#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 12158#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12159 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 12160 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 12161#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12162 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 12163 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 12164#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 12165#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 12166 12167#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 12168#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 12169#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 12170#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 12171#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 12172#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 12173#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12174 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 12175 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 12176#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12177 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 12178 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 12179#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 12180#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 12181 12182#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 12183#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 12184#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 12185#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 12186#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 12187#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 12188#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12189 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 12190 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 12191#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12192 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 12193 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 12194#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 12195#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 12196#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 12197#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 12198 12199#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 12200#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 12201#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 12202#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 12203#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 12204#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 12205#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12206 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 12207 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 12208#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12209 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 12210 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 12211 12212#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 12213#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 12214#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 12215#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 12216#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 12217#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 12218#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12219 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 12220 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 12221#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12222 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 12223 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 12224 12225#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 12226#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 12227#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 12228#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 12229#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 12230#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 12231#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12232 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 12233 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 12234#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12235 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 12236 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 12237 12238#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 12239#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 12240#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 12241#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 12242#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 12243#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 12244#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12245 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 12246 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 12247#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12248 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 12249 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 12250 12251#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 12252#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 12253#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 12254#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 12255#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 12256#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 12257#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12258 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 12259 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 12260#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12261 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 12262 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 12263 12264#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 12265#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 12266#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 12267#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 12268#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 12269#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 12270#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12271 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 12272 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 12273#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12274 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 12275 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 12276#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 12277#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 12278#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 12279 12280/* Icelake Rate Control Buffer Threshold Registers */ 12281#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 12282#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 12283#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 12284#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 12285#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 12286#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 12287#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 12288#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 12289#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 12290#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 12291#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 12292#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 12293#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12294 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 12295 _ICL_DSC0_RC_BUF_THRESH_0_PC) 12296#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12297 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 12298 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 12299#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12300 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 12301 _ICL_DSC1_RC_BUF_THRESH_0_PC) 12302#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12303 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 12304 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 12305 12306#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 12307#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 12308#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 12309#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 12310#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 12311#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 12312#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 12313#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 12314#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 12315#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 12316#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 12317#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 12318#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12319 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 12320 _ICL_DSC0_RC_BUF_THRESH_1_PC) 12321#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12322 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 12323 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 12324#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12325 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 12326 _ICL_DSC1_RC_BUF_THRESH_1_PC) 12327#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 12328 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 12329 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 12330 12331#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 12332#define MODULAR_FIA_MASK (1 << 4) 12333#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 12334#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 12335#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 12336#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 12337#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 12338 12339#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 12340#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 12341 12342#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 12343#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 12344 12345#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 12346#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 12347#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 12348#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 12349 12350/* This register controls the Display State Buffer (DSB) engines. */ 12351#define _DSBSL_INSTANCE_BASE 0x70B00 12352#define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 12353 (pipe) * 0x1000 + (id) * 0x100) 12354#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 12355#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 12356#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 12357#define DSB_ENABLE (1 << 31) 12358#define DSB_STATUS (1 << 0) 12359 12360#define TGL_ROOT_DEVICE_ID 0x9A00 12361#define TGL_ROOT_DEVICE_MASK 0xFF00 12362#define TGL_ROOT_DEVICE_SKU_MASK 0xF 12363#define TGL_ROOT_DEVICE_SKU_ULX 0x2 12364#define TGL_ROOT_DEVICE_SKU_ULT 0x4 12365 12366#endif /* _I915_REG_H_ */ 12367