1/* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36#include <linux/kthread.h> 37 38#include "gem/i915_gem_pm.h" 39#include "gt/intel_context.h" 40#include "gt/intel_ring.h" 41 42#include "i915_drv.h" 43#include "i915_gem_gtt.h" 44#include "gvt.h" 45 46#define RING_CTX_OFF(x) \ 47 offsetof(struct execlist_ring_context, x) 48 49static void set_context_pdp_root_pointer( 50 struct execlist_ring_context *ring_context, 51 u32 pdp[8]) 52{ 53 int i; 54 55 for (i = 0; i < 8; i++) 56 ring_context->pdps[i].val = pdp[7 - i]; 57} 58 59static void update_shadow_pdps(struct intel_vgpu_workload *workload) 60{ 61 struct execlist_ring_context *shadow_ring_context; 62 struct intel_context *ctx = workload->req->context; 63 64 if (WARN_ON(!workload->shadow_mm)) 65 return; 66 67 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount))) 68 return; 69 70 shadow_ring_context = (struct execlist_ring_context *)ctx->lrc_reg_state; 71 set_context_pdp_root_pointer(shadow_ring_context, 72 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); 73} 74 75/* 76 * when populating shadow ctx from guest, we should not overrride oa related 77 * registers, so that they will not be overlapped by guest oa configs. Thus 78 * made it possible to capture oa data from host for both host and guests. 79 */ 80static void sr_oa_regs(struct intel_vgpu_workload *workload, 81 u32 *reg_state, bool save) 82{ 83 struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915; 84 u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset; 85 u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset; 86 int i = 0; 87 u32 flex_mmio[] = { 88 i915_mmio_reg_offset(EU_PERF_CNTL0), 89 i915_mmio_reg_offset(EU_PERF_CNTL1), 90 i915_mmio_reg_offset(EU_PERF_CNTL2), 91 i915_mmio_reg_offset(EU_PERF_CNTL3), 92 i915_mmio_reg_offset(EU_PERF_CNTL4), 93 i915_mmio_reg_offset(EU_PERF_CNTL5), 94 i915_mmio_reg_offset(EU_PERF_CNTL6), 95 }; 96 97 if (workload->engine->id != RCS0) 98 return; 99 100 if (save) { 101 workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; 102 103 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 104 u32 state_offset = ctx_flexeu0 + i * 2; 105 106 workload->flex_mmio[i] = reg_state[state_offset + 1]; 107 } 108 } else { 109 reg_state[ctx_oactxctrl] = 110 i915_mmio_reg_offset(GEN8_OACTXCONTROL); 111 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; 112 113 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 114 u32 state_offset = ctx_flexeu0 + i * 2; 115 u32 mmio = flex_mmio[i]; 116 117 reg_state[state_offset] = mmio; 118 reg_state[state_offset + 1] = workload->flex_mmio[i]; 119 } 120 } 121} 122 123static int populate_shadow_context(struct intel_vgpu_workload *workload) 124{ 125 struct intel_vgpu *vgpu = workload->vgpu; 126 struct intel_gvt *gvt = vgpu->gvt; 127 struct intel_context *ctx = workload->req->context; 128 struct execlist_ring_context *shadow_ring_context; 129 void *dst; 130 void *context_base; 131 unsigned long context_gpa, context_page_num; 132 unsigned long gpa_base; /* first gpa of consecutive GPAs */ 133 unsigned long gpa_size; /* size of consecutive GPAs */ 134 struct intel_vgpu_submission *s = &vgpu->submission; 135 int i; 136 bool skip = false; 137 int ring_id = workload->engine->id; 138 139 GEM_BUG_ON(!intel_context_is_pinned(ctx)); 140 141 context_base = (void *) ctx->lrc_reg_state - 142 (LRC_STATE_PN << I915_GTT_PAGE_SHIFT); 143 144 shadow_ring_context = (void *) ctx->lrc_reg_state; 145 146 sr_oa_regs(workload, (u32 *)shadow_ring_context, true); 147#define COPY_REG(name) \ 148 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 149 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 150#define COPY_REG_MASKED(name) {\ 151 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 152 + RING_CTX_OFF(name.val),\ 153 &shadow_ring_context->name.val, 4);\ 154 shadow_ring_context->name.val |= 0xffff << 16;\ 155 } 156 157 COPY_REG_MASKED(ctx_ctrl); 158 COPY_REG(ctx_timestamp); 159 160 if (workload->engine->id == RCS0) { 161 COPY_REG(bb_per_ctx_ptr); 162 COPY_REG(rcs_indirect_ctx); 163 COPY_REG(rcs_indirect_ctx_offset); 164 } 165#undef COPY_REG 166#undef COPY_REG_MASKED 167 168 intel_gvt_hypervisor_read_gpa(vgpu, 169 workload->ring_context_gpa + 170 sizeof(*shadow_ring_context), 171 (void *)shadow_ring_context + 172 sizeof(*shadow_ring_context), 173 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 174 175 sr_oa_regs(workload, (u32 *)shadow_ring_context, false); 176 177 gvt_dbg_sched("ring %s workload lrca %x, ctx_id %x, ctx gpa %llx", 178 workload->engine->name, workload->ctx_desc.lrca, 179 workload->ctx_desc.context_id, 180 workload->ring_context_gpa); 181 182 /* only need to ensure this context is not pinned/unpinned during the 183 * period from last submission to this this submission. 184 * Upon reaching this function, the currently submitted context is not 185 * supposed to get unpinned. If a misbehaving guest driver ever does 186 * this, it would corrupt itself. 187 */ 188 if (s->last_ctx[ring_id].valid && 189 (s->last_ctx[ring_id].lrca == 190 workload->ctx_desc.lrca) && 191 (s->last_ctx[ring_id].ring_context_gpa == 192 workload->ring_context_gpa)) 193 skip = true; 194 195 s->last_ctx[ring_id].lrca = workload->ctx_desc.lrca; 196 s->last_ctx[ring_id].ring_context_gpa = workload->ring_context_gpa; 197 198 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) || skip) 199 return 0; 200 201 s->last_ctx[ring_id].valid = false; 202 context_page_num = workload->engine->context_size; 203 context_page_num = context_page_num >> PAGE_SHIFT; 204 205 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) 206 context_page_num = 19; 207 208 /* find consecutive GPAs from gma until the first inconsecutive GPA. 209 * read from the continuous GPAs into dst virtual address 210 */ 211 gpa_size = 0; 212 for (i = 2; i < context_page_num; i++) { 213 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 214 (u32)((workload->ctx_desc.lrca + i) << 215 I915_GTT_PAGE_SHIFT)); 216 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 217 gvt_vgpu_err("Invalid guest context descriptor\n"); 218 return -EFAULT; 219 } 220 221 if (gpa_size == 0) { 222 gpa_base = context_gpa; 223 dst = context_base + (i << I915_GTT_PAGE_SHIFT); 224 } else if (context_gpa != gpa_base + gpa_size) 225 goto read; 226 227 gpa_size += I915_GTT_PAGE_SIZE; 228 229 if (i == context_page_num - 1) 230 goto read; 231 232 continue; 233 234read: 235 intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size); 236 gpa_base = context_gpa; 237 gpa_size = I915_GTT_PAGE_SIZE; 238 dst = context_base + (i << I915_GTT_PAGE_SHIFT); 239 } 240 s->last_ctx[ring_id].valid = true; 241 return 0; 242} 243 244static inline bool is_gvt_request(struct i915_request *rq) 245{ 246 return intel_context_force_single_submission(rq->context); 247} 248 249static void save_ring_hw_state(struct intel_vgpu *vgpu, 250 const struct intel_engine_cs *engine) 251{ 252 struct intel_uncore *uncore = engine->uncore; 253 i915_reg_t reg; 254 255 reg = RING_INSTDONE(engine->mmio_base); 256 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = 257 intel_uncore_read(uncore, reg); 258 259 reg = RING_ACTHD(engine->mmio_base); 260 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = 261 intel_uncore_read(uncore, reg); 262 263 reg = RING_ACTHD_UDW(engine->mmio_base); 264 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = 265 intel_uncore_read(uncore, reg); 266} 267 268static int shadow_context_status_change(struct notifier_block *nb, 269 unsigned long action, void *data) 270{ 271 struct i915_request *rq = data; 272 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, 273 shadow_ctx_notifier_block[rq->engine->id]); 274 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 275 enum intel_engine_id ring_id = rq->engine->id; 276 struct intel_vgpu_workload *workload; 277 unsigned long flags; 278 279 if (!is_gvt_request(rq)) { 280 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 281 if (action == INTEL_CONTEXT_SCHEDULE_IN && 282 scheduler->engine_owner[ring_id]) { 283 /* Switch ring from vGPU to host. */ 284 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 285 NULL, rq->engine); 286 scheduler->engine_owner[ring_id] = NULL; 287 } 288 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 289 290 return NOTIFY_OK; 291 } 292 293 workload = scheduler->current_workload[ring_id]; 294 if (unlikely(!workload)) 295 return NOTIFY_OK; 296 297 switch (action) { 298 case INTEL_CONTEXT_SCHEDULE_IN: 299 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 300 if (workload->vgpu != scheduler->engine_owner[ring_id]) { 301 /* Switch ring from host to vGPU or vGPU to vGPU. */ 302 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 303 workload->vgpu, rq->engine); 304 scheduler->engine_owner[ring_id] = workload->vgpu; 305 } else 306 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n", 307 ring_id, workload->vgpu->id); 308 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 309 atomic_set(&workload->shadow_ctx_active, 1); 310 break; 311 case INTEL_CONTEXT_SCHEDULE_OUT: 312 save_ring_hw_state(workload->vgpu, rq->engine); 313 atomic_set(&workload->shadow_ctx_active, 0); 314 break; 315 case INTEL_CONTEXT_SCHEDULE_PREEMPTED: 316 save_ring_hw_state(workload->vgpu, rq->engine); 317 break; 318 default: 319 WARN_ON(1); 320 return NOTIFY_OK; 321 } 322 wake_up(&workload->shadow_ctx_status_wq); 323 return NOTIFY_OK; 324} 325 326static void 327shadow_context_descriptor_update(struct intel_context *ce, 328 struct intel_vgpu_workload *workload) 329{ 330 u64 desc = ce->lrc.desc; 331 332 /* 333 * Update bits 0-11 of the context descriptor which includes flags 334 * like GEN8_CTX_* cached in desc_template 335 */ 336 desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT); 337 desc |= (u64)workload->ctx_desc.addressing_mode << 338 GEN8_CTX_ADDRESSING_MODE_SHIFT; 339 340 ce->lrc.desc = desc; 341} 342 343static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) 344{ 345 struct intel_vgpu *vgpu = workload->vgpu; 346 struct i915_request *req = workload->req; 347 void *shadow_ring_buffer_va; 348 u32 *cs; 349 int err; 350 351 if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context)) 352 intel_vgpu_restore_inhibit_context(vgpu, req); 353 354 /* 355 * To track whether a request has started on HW, we can emit a 356 * breadcrumb at the beginning of the request and check its 357 * timeline's HWSP to see if the breadcrumb has advanced past the 358 * start of this request. Actually, the request must have the 359 * init_breadcrumb if its timeline set has_init_bread_crumb, or the 360 * scheduler might get a wrong state of it during reset. Since the 361 * requests from gvt always set the has_init_breadcrumb flag, here 362 * need to do the emit_init_breadcrumb for all the requests. 363 */ 364 if (req->engine->emit_init_breadcrumb) { 365 err = req->engine->emit_init_breadcrumb(req); 366 if (err) { 367 gvt_vgpu_err("fail to emit init breadcrumb\n"); 368 return err; 369 } 370 } 371 372 /* allocate shadow ring buffer */ 373 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32)); 374 if (IS_ERR(cs)) { 375 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", 376 workload->rb_len); 377 return PTR_ERR(cs); 378 } 379 380 shadow_ring_buffer_va = workload->shadow_ring_buffer_va; 381 382 /* get shadow ring buffer va */ 383 workload->shadow_ring_buffer_va = cs; 384 385 memcpy(cs, shadow_ring_buffer_va, 386 workload->rb_len); 387 388 cs += workload->rb_len / sizeof(u32); 389 intel_ring_advance(workload->req, cs); 390 391 return 0; 392} 393 394static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 395{ 396 if (!wa_ctx->indirect_ctx.obj) 397 return; 398 399 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj); 400 i915_gem_object_put(wa_ctx->indirect_ctx.obj); 401 402 wa_ctx->indirect_ctx.obj = NULL; 403 wa_ctx->indirect_ctx.shadow_va = NULL; 404} 405 406static void set_dma_address(struct i915_page_directory *pd, dma_addr_t addr) 407{ 408 struct scatterlist *sg = pd->pt.base->mm.pages->sgl; 409 410 /* This is not a good idea */ 411 sg->dma_address = addr; 412} 413 414static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, 415 struct intel_context *ce) 416{ 417 struct intel_vgpu_mm *mm = workload->shadow_mm; 418 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm); 419 int i = 0; 420 421 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { 422 set_dma_address(ppgtt->pd, mm->ppgtt_mm.shadow_pdps[0]); 423 } else { 424 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) { 425 struct i915_page_directory * const pd = 426 i915_pd_entry(ppgtt->pd, i); 427 /* skip now as current i915 ppgtt alloc won't allocate 428 top level pdp for non 4-level table, won't impact 429 shadow ppgtt. */ 430 if (!pd) 431 break; 432 433 set_dma_address(pd, mm->ppgtt_mm.shadow_pdps[i]); 434 } 435 } 436} 437 438static int 439intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload) 440{ 441 struct intel_vgpu *vgpu = workload->vgpu; 442 struct intel_vgpu_submission *s = &vgpu->submission; 443 struct i915_request *rq; 444 445 if (workload->req) 446 return 0; 447 448 rq = i915_request_create(s->shadow[workload->engine->id]); 449 if (IS_ERR(rq)) { 450 gvt_vgpu_err("fail to allocate gem request\n"); 451 return PTR_ERR(rq); 452 } 453 454 workload->req = i915_request_get(rq); 455 return 0; 456} 457 458/** 459 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and 460 * shadow it as well, include ringbuffer,wa_ctx and ctx. 461 * @workload: an abstract entity for each execlist submission. 462 * 463 * This function is called before the workload submitting to i915, to make 464 * sure the content of the workload is valid. 465 */ 466int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) 467{ 468 struct intel_vgpu *vgpu = workload->vgpu; 469 struct intel_vgpu_submission *s = &vgpu->submission; 470 int ret; 471 472 lockdep_assert_held(&vgpu->vgpu_lock); 473 474 if (workload->shadow) 475 return 0; 476 477 if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated)) 478 shadow_context_descriptor_update(s->shadow[workload->engine->id], 479 workload); 480 481 ret = intel_gvt_scan_and_shadow_ringbuffer(workload); 482 if (ret) 483 return ret; 484 485 if (workload->engine->id == RCS0 && 486 workload->wa_ctx.indirect_ctx.size) { 487 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 488 if (ret) 489 goto err_shadow; 490 } 491 492 workload->shadow = true; 493 return 0; 494 495err_shadow: 496 release_shadow_wa_ctx(&workload->wa_ctx); 497 return ret; 498} 499 500static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload); 501 502static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 503{ 504 struct intel_gvt *gvt = workload->vgpu->gvt; 505 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 506 struct intel_vgpu_shadow_bb *bb; 507 int ret; 508 509 list_for_each_entry(bb, &workload->shadow_bb, list) { 510 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va 511 * is only updated into ring_scan_buffer, not real ring address 512 * allocated in later copy_workload_to_ring_buffer. pls be noted 513 * shadow_ring_buffer_va is now pointed to real ring buffer va 514 * in copy_workload_to_ring_buffer. 515 */ 516 517 if (bb->bb_offset) 518 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va 519 + bb->bb_offset; 520 521 /* 522 * For non-priv bb, scan&shadow is only for 523 * debugging purpose, so the content of shadow bb 524 * is the same as original bb. Therefore, 525 * here, rather than switch to shadow bb's gma 526 * address, we directly use original batch buffer's 527 * gma address, and send original bb to hardware 528 * directly 529 */ 530 if (!bb->ppgtt) { 531 bb->vma = i915_gem_object_ggtt_pin(bb->obj, 532 NULL, 0, 0, 0); 533 if (IS_ERR(bb->vma)) { 534 ret = PTR_ERR(bb->vma); 535 goto err; 536 } 537 538 /* relocate shadow batch buffer */ 539 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); 540 if (gmadr_bytes == 8) 541 bb->bb_start_cmd_va[2] = 0; 542 543 ret = i915_vma_move_to_active(bb->vma, 544 workload->req, 545 0); 546 if (ret) 547 goto err; 548 } 549 550 /* No one is going to touch shadow bb from now on. */ 551 i915_gem_object_flush_map(bb->obj); 552 } 553 return 0; 554err: 555 release_shadow_batch_buffer(workload); 556 return ret; 557} 558 559static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx) 560{ 561 struct intel_vgpu_workload *workload = 562 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx); 563 struct i915_request *rq = workload->req; 564 struct execlist_ring_context *shadow_ring_context = 565 (struct execlist_ring_context *)rq->context->lrc_reg_state; 566 567 shadow_ring_context->bb_per_ctx_ptr.val = 568 (shadow_ring_context->bb_per_ctx_ptr.val & 569 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma; 570 shadow_ring_context->rcs_indirect_ctx.val = 571 (shadow_ring_context->rcs_indirect_ctx.val & 572 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma; 573} 574 575static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 576{ 577 struct i915_vma *vma; 578 unsigned char *per_ctx_va = 579 (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 580 wa_ctx->indirect_ctx.size; 581 582 if (wa_ctx->indirect_ctx.size == 0) 583 return 0; 584 585 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL, 586 0, CACHELINE_BYTES, 0); 587 if (IS_ERR(vma)) 588 return PTR_ERR(vma); 589 590 /* FIXME: we are not tracking our pinned VMA leaving it 591 * up to the core to fix up the stray pin_count upon 592 * free. 593 */ 594 595 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); 596 597 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1); 598 memset(per_ctx_va, 0, CACHELINE_BYTES); 599 600 update_wa_ctx_2_shadow_ctx(wa_ctx); 601 return 0; 602} 603 604static void update_vreg_in_ctx(struct intel_vgpu_workload *workload) 605{ 606 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = 607 workload->rb_start; 608} 609 610static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 611{ 612 struct intel_vgpu_shadow_bb *bb, *pos; 613 614 if (list_empty(&workload->shadow_bb)) 615 return; 616 617 bb = list_first_entry(&workload->shadow_bb, 618 struct intel_vgpu_shadow_bb, list); 619 620 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { 621 if (bb->obj) { 622 if (bb->va && !IS_ERR(bb->va)) 623 i915_gem_object_unpin_map(bb->obj); 624 625 if (bb->vma && !IS_ERR(bb->vma)) 626 i915_vma_unpin(bb->vma); 627 628 i915_gem_object_put(bb->obj); 629 } 630 list_del(&bb->list); 631 kfree(bb); 632 } 633} 634 635static int 636intel_vgpu_shadow_mm_pin(struct intel_vgpu_workload *workload) 637{ 638 struct intel_vgpu *vgpu = workload->vgpu; 639 struct intel_vgpu_mm *m; 640 int ret = 0; 641 642 ret = intel_vgpu_pin_mm(workload->shadow_mm); 643 if (ret) { 644 gvt_vgpu_err("fail to vgpu pin mm\n"); 645 return ret; 646 } 647 648 if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT || 649 !workload->shadow_mm->ppgtt_mm.shadowed) { 650 intel_vgpu_unpin_mm(workload->shadow_mm); 651 gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); 652 return -EINVAL; 653 } 654 655 if (!list_empty(&workload->lri_shadow_mm)) { 656 list_for_each_entry(m, &workload->lri_shadow_mm, 657 ppgtt_mm.link) { 658 ret = intel_vgpu_pin_mm(m); 659 if (ret) { 660 list_for_each_entry_from_reverse(m, 661 &workload->lri_shadow_mm, 662 ppgtt_mm.link) 663 intel_vgpu_unpin_mm(m); 664 gvt_vgpu_err("LRI shadow ppgtt fail to pin\n"); 665 break; 666 } 667 } 668 } 669 670 if (ret) 671 intel_vgpu_unpin_mm(workload->shadow_mm); 672 673 return ret; 674} 675 676static void 677intel_vgpu_shadow_mm_unpin(struct intel_vgpu_workload *workload) 678{ 679 struct intel_vgpu_mm *m; 680 681 if (!list_empty(&workload->lri_shadow_mm)) { 682 list_for_each_entry(m, &workload->lri_shadow_mm, 683 ppgtt_mm.link) 684 intel_vgpu_unpin_mm(m); 685 } 686 intel_vgpu_unpin_mm(workload->shadow_mm); 687} 688 689static int prepare_workload(struct intel_vgpu_workload *workload) 690{ 691 struct intel_vgpu *vgpu = workload->vgpu; 692 struct intel_vgpu_submission *s = &vgpu->submission; 693 int ret = 0; 694 695 ret = intel_vgpu_shadow_mm_pin(workload); 696 if (ret) { 697 gvt_vgpu_err("fail to pin shadow mm\n"); 698 return ret; 699 } 700 701 update_shadow_pdps(workload); 702 703 set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]); 704 705 ret = intel_vgpu_sync_oos_pages(workload->vgpu); 706 if (ret) { 707 gvt_vgpu_err("fail to vgpu sync oos pages\n"); 708 goto err_unpin_mm; 709 } 710 711 ret = intel_vgpu_flush_post_shadow(workload->vgpu); 712 if (ret) { 713 gvt_vgpu_err("fail to flush post shadow\n"); 714 goto err_unpin_mm; 715 } 716 717 ret = copy_workload_to_ring_buffer(workload); 718 if (ret) { 719 gvt_vgpu_err("fail to generate request\n"); 720 goto err_unpin_mm; 721 } 722 723 ret = prepare_shadow_batch_buffer(workload); 724 if (ret) { 725 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n"); 726 goto err_unpin_mm; 727 } 728 729 ret = prepare_shadow_wa_ctx(&workload->wa_ctx); 730 if (ret) { 731 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n"); 732 goto err_shadow_batch; 733 } 734 735 if (workload->prepare) { 736 ret = workload->prepare(workload); 737 if (ret) 738 goto err_shadow_wa_ctx; 739 } 740 741 return 0; 742err_shadow_wa_ctx: 743 release_shadow_wa_ctx(&workload->wa_ctx); 744err_shadow_batch: 745 release_shadow_batch_buffer(workload); 746err_unpin_mm: 747 intel_vgpu_shadow_mm_unpin(workload); 748 return ret; 749} 750 751static int dispatch_workload(struct intel_vgpu_workload *workload) 752{ 753 struct intel_vgpu *vgpu = workload->vgpu; 754 struct i915_request *rq; 755 int ret; 756 757 gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n", 758 workload->engine->name, workload); 759 760 mutex_lock(&vgpu->vgpu_lock); 761 762 ret = intel_gvt_workload_req_alloc(workload); 763 if (ret) 764 goto err_req; 765 766 ret = intel_gvt_scan_and_shadow_workload(workload); 767 if (ret) 768 goto out; 769 770 ret = populate_shadow_context(workload); 771 if (ret) { 772 release_shadow_wa_ctx(&workload->wa_ctx); 773 goto out; 774 } 775 776 ret = prepare_workload(workload); 777out: 778 if (ret) { 779 /* We might still need to add request with 780 * clean ctx to retire it properly.. 781 */ 782 rq = fetch_and_zero(&workload->req); 783 i915_request_put(rq); 784 } 785 786 if (!IS_ERR_OR_NULL(workload->req)) { 787 gvt_dbg_sched("ring id %s submit workload to i915 %p\n", 788 workload->engine->name, workload->req); 789 i915_request_add(workload->req); 790 workload->dispatched = true; 791 } 792err_req: 793 if (ret) 794 workload->status = ret; 795 mutex_unlock(&vgpu->vgpu_lock); 796 return ret; 797} 798 799static struct intel_vgpu_workload * 800pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine) 801{ 802 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 803 struct intel_vgpu_workload *workload = NULL; 804 805 mutex_lock(&gvt->sched_lock); 806 807 /* 808 * no current vgpu / will be scheduled out / no workload 809 * bail out 810 */ 811 if (!scheduler->current_vgpu) { 812 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name); 813 goto out; 814 } 815 816 if (scheduler->need_reschedule) { 817 gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name); 818 goto out; 819 } 820 821 if (!scheduler->current_vgpu->active || 822 list_empty(workload_q_head(scheduler->current_vgpu, engine))) 823 goto out; 824 825 /* 826 * still have current workload, maybe the workload disptacher 827 * fail to submit it for some reason, resubmit it. 828 */ 829 if (scheduler->current_workload[engine->id]) { 830 workload = scheduler->current_workload[engine->id]; 831 gvt_dbg_sched("ring %s still have current workload %p\n", 832 engine->name, workload); 833 goto out; 834 } 835 836 /* 837 * pick a workload as current workload 838 * once current workload is set, schedule policy routines 839 * will wait the current workload is finished when trying to 840 * schedule out a vgpu. 841 */ 842 scheduler->current_workload[engine->id] = 843 list_first_entry(workload_q_head(scheduler->current_vgpu, 844 engine), 845 struct intel_vgpu_workload, list); 846 847 workload = scheduler->current_workload[engine->id]; 848 849 gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload); 850 851 atomic_inc(&workload->vgpu->submission.running_workload_num); 852out: 853 mutex_unlock(&gvt->sched_lock); 854 return workload; 855} 856 857static void update_guest_pdps(struct intel_vgpu *vgpu, 858 u64 ring_context_gpa, u32 pdp[8]) 859{ 860 u64 gpa; 861 int i; 862 863 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); 864 865 for (i = 0; i < 8; i++) 866 intel_gvt_hypervisor_write_gpa(vgpu, 867 gpa + i * 8, &pdp[7 - i], 4); 868} 869 870static __maybe_unused bool 871check_shadow_context_ppgtt(struct execlist_ring_context *c, struct intel_vgpu_mm *m) 872{ 873 if (m->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { 874 u64 shadow_pdp = c->pdps[7].val | (u64) c->pdps[6].val << 32; 875 876 if (shadow_pdp != m->ppgtt_mm.shadow_pdps[0]) { 877 gvt_dbg_mm("4-level context ppgtt not match LRI command\n"); 878 return false; 879 } 880 return true; 881 } else { 882 /* see comment in LRI handler in cmd_parser.c */ 883 gvt_dbg_mm("invalid shadow mm type\n"); 884 return false; 885 } 886} 887 888static void update_guest_context(struct intel_vgpu_workload *workload) 889{ 890 struct i915_request *rq = workload->req; 891 struct intel_vgpu *vgpu = workload->vgpu; 892 struct execlist_ring_context *shadow_ring_context; 893 struct intel_context *ctx = workload->req->context; 894 void *context_base; 895 void *src; 896 unsigned long context_gpa, context_page_num; 897 unsigned long gpa_base; /* first gpa of consecutive GPAs */ 898 unsigned long gpa_size; /* size of consecutive GPAs*/ 899 int i; 900 u32 ring_base; 901 u32 head, tail; 902 u16 wrap_count; 903 904 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id, 905 workload->ctx_desc.lrca); 906 907 GEM_BUG_ON(!intel_context_is_pinned(ctx)); 908 909 head = workload->rb_head; 910 tail = workload->rb_tail; 911 wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF; 912 913 if (tail < head) { 914 if (wrap_count == RB_HEAD_WRAP_CNT_MAX) 915 wrap_count = 0; 916 else 917 wrap_count += 1; 918 } 919 920 head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail; 921 922 ring_base = rq->engine->mmio_base; 923 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; 924 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; 925 926 context_page_num = rq->engine->context_size; 927 context_page_num = context_page_num >> PAGE_SHIFT; 928 929 if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0) 930 context_page_num = 19; 931 932 context_base = (void *) ctx->lrc_reg_state - 933 (LRC_STATE_PN << I915_GTT_PAGE_SHIFT); 934 935 /* find consecutive GPAs from gma until the first inconsecutive GPA. 936 * write to the consecutive GPAs from src virtual address 937 */ 938 gpa_size = 0; 939 for (i = 2; i < context_page_num; i++) { 940 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 941 (u32)((workload->ctx_desc.lrca + i) << 942 I915_GTT_PAGE_SHIFT)); 943 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 944 gvt_vgpu_err("invalid guest context descriptor\n"); 945 return; 946 } 947 948 if (gpa_size == 0) { 949 gpa_base = context_gpa; 950 src = context_base + (i << I915_GTT_PAGE_SHIFT); 951 } else if (context_gpa != gpa_base + gpa_size) 952 goto write; 953 954 gpa_size += I915_GTT_PAGE_SIZE; 955 956 if (i == context_page_num - 1) 957 goto write; 958 959 continue; 960 961write: 962 intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size); 963 gpa_base = context_gpa; 964 gpa_size = I915_GTT_PAGE_SIZE; 965 src = context_base + (i << I915_GTT_PAGE_SHIFT); 966 } 967 968 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 969 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 970 971 shadow_ring_context = (void *) ctx->lrc_reg_state; 972 973 if (!list_empty(&workload->lri_shadow_mm)) { 974 struct intel_vgpu_mm *m = list_last_entry(&workload->lri_shadow_mm, 975 struct intel_vgpu_mm, 976 ppgtt_mm.link); 977 GEM_BUG_ON(!check_shadow_context_ppgtt(shadow_ring_context, m)); 978 update_guest_pdps(vgpu, workload->ring_context_gpa, 979 (void *)m->ppgtt_mm.guest_pdps); 980 } 981 982#define COPY_REG(name) \ 983 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 984 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 985 986 COPY_REG(ctx_ctrl); 987 COPY_REG(ctx_timestamp); 988 989#undef COPY_REG 990 991 intel_gvt_hypervisor_write_gpa(vgpu, 992 workload->ring_context_gpa + 993 sizeof(*shadow_ring_context), 994 (void *)shadow_ring_context + 995 sizeof(*shadow_ring_context), 996 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 997} 998 999void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu, 1000 intel_engine_mask_t engine_mask) 1001{ 1002 struct intel_vgpu_submission *s = &vgpu->submission; 1003 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1004 struct intel_engine_cs *engine; 1005 struct intel_vgpu_workload *pos, *n; 1006 intel_engine_mask_t tmp; 1007 1008 /* free the unsubmited workloads in the queues. */ 1009 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) { 1010 list_for_each_entry_safe(pos, n, 1011 &s->workload_q_head[engine->id], list) { 1012 list_del_init(&pos->list); 1013 intel_vgpu_destroy_workload(pos); 1014 } 1015 clear_bit(engine->id, s->shadow_ctx_desc_updated); 1016 } 1017} 1018 1019static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 1020{ 1021 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1022 struct intel_vgpu_workload *workload = 1023 scheduler->current_workload[ring_id]; 1024 struct intel_vgpu *vgpu = workload->vgpu; 1025 struct intel_vgpu_submission *s = &vgpu->submission; 1026 struct i915_request *rq = workload->req; 1027 int event; 1028 1029 mutex_lock(&vgpu->vgpu_lock); 1030 mutex_lock(&gvt->sched_lock); 1031 1032 /* For the workload w/ request, needs to wait for the context 1033 * switch to make sure request is completed. 1034 * For the workload w/o request, directly complete the workload. 1035 */ 1036 if (rq) { 1037 wait_event(workload->shadow_ctx_status_wq, 1038 !atomic_read(&workload->shadow_ctx_active)); 1039 1040 /* If this request caused GPU hang, req->fence.error will 1041 * be set to -EIO. Use -EIO to set workload status so 1042 * that when this request caused GPU hang, didn't trigger 1043 * context switch interrupt to guest. 1044 */ 1045 if (likely(workload->status == -EINPROGRESS)) { 1046 if (workload->req->fence.error == -EIO) 1047 workload->status = -EIO; 1048 else 1049 workload->status = 0; 1050 } 1051 1052 if (!workload->status && 1053 !(vgpu->resetting_eng & BIT(ring_id))) { 1054 update_guest_context(workload); 1055 1056 for_each_set_bit(event, workload->pending_events, 1057 INTEL_GVT_EVENT_MAX) 1058 intel_vgpu_trigger_virtual_event(vgpu, event); 1059 } 1060 1061 i915_request_put(fetch_and_zero(&workload->req)); 1062 } 1063 1064 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 1065 ring_id, workload, workload->status); 1066 1067 scheduler->current_workload[ring_id] = NULL; 1068 1069 list_del_init(&workload->list); 1070 1071 if (workload->status || vgpu->resetting_eng & BIT(ring_id)) { 1072 /* if workload->status is not successful means HW GPU 1073 * has occurred GPU hang or something wrong with i915/GVT, 1074 * and GVT won't inject context switch interrupt to guest. 1075 * So this error is a vGPU hang actually to the guest. 1076 * According to this we should emunlate a vGPU hang. If 1077 * there are pending workloads which are already submitted 1078 * from guest, we should clean them up like HW GPU does. 1079 * 1080 * if it is in middle of engine resetting, the pending 1081 * workloads won't be submitted to HW GPU and will be 1082 * cleaned up during the resetting process later, so doing 1083 * the workload clean up here doesn't have any impact. 1084 **/ 1085 intel_vgpu_clean_workloads(vgpu, BIT(ring_id)); 1086 } 1087 1088 workload->complete(workload); 1089 1090 intel_vgpu_shadow_mm_unpin(workload); 1091 intel_vgpu_destroy_workload(workload); 1092 1093 atomic_dec(&s->running_workload_num); 1094 wake_up(&scheduler->workload_complete_wq); 1095 1096 if (gvt->scheduler.need_reschedule) 1097 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED); 1098 1099 mutex_unlock(&gvt->sched_lock); 1100 mutex_unlock(&vgpu->vgpu_lock); 1101} 1102 1103static int workload_thread(void *arg) 1104{ 1105 struct intel_engine_cs *engine = arg; 1106 const bool need_force_wake = INTEL_GEN(engine->i915) >= 9; 1107 struct intel_gvt *gvt = engine->i915->gvt; 1108 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1109 struct intel_vgpu_workload *workload = NULL; 1110 struct intel_vgpu *vgpu = NULL; 1111 int ret; 1112 DEFINE_WAIT_FUNC(wait, woken_wake_function); 1113 1114 gvt_dbg_core("workload thread for ring %s started\n", engine->name); 1115 1116 while (!kthread_should_stop()) { 1117 intel_wakeref_t wakeref; 1118 1119 add_wait_queue(&scheduler->waitq[engine->id], &wait); 1120 do { 1121 workload = pick_next_workload(gvt, engine); 1122 if (workload) 1123 break; 1124 wait_woken(&wait, TASK_INTERRUPTIBLE, 1125 MAX_SCHEDULE_TIMEOUT); 1126 } while (!kthread_should_stop()); 1127 remove_wait_queue(&scheduler->waitq[engine->id], &wait); 1128 1129 if (!workload) 1130 break; 1131 1132 gvt_dbg_sched("ring %s next workload %p vgpu %d\n", 1133 engine->name, workload, 1134 workload->vgpu->id); 1135 1136 wakeref = intel_runtime_pm_get(engine->uncore->rpm); 1137 1138 gvt_dbg_sched("ring %s will dispatch workload %p\n", 1139 engine->name, workload); 1140 1141 if (need_force_wake) 1142 intel_uncore_forcewake_get(engine->uncore, 1143 FORCEWAKE_ALL); 1144 /* 1145 * Update the vReg of the vGPU which submitted this 1146 * workload. The vGPU may use these registers for checking 1147 * the context state. The value comes from GPU commands 1148 * in this workload. 1149 */ 1150 update_vreg_in_ctx(workload); 1151 1152 ret = dispatch_workload(workload); 1153 1154 if (ret) { 1155 vgpu = workload->vgpu; 1156 gvt_vgpu_err("fail to dispatch workload, skip\n"); 1157 goto complete; 1158 } 1159 1160 gvt_dbg_sched("ring %s wait workload %p\n", 1161 engine->name, workload); 1162 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT); 1163 1164complete: 1165 gvt_dbg_sched("will complete workload %p, status: %d\n", 1166 workload, workload->status); 1167 1168 complete_current_workload(gvt, engine->id); 1169 1170 if (need_force_wake) 1171 intel_uncore_forcewake_put(engine->uncore, 1172 FORCEWAKE_ALL); 1173 1174 intel_runtime_pm_put(engine->uncore->rpm, wakeref); 1175 if (ret && (vgpu_is_vm_unhealthy(ret))) 1176 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1177 } 1178 return 0; 1179} 1180 1181void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 1182{ 1183 struct intel_vgpu_submission *s = &vgpu->submission; 1184 struct intel_gvt *gvt = vgpu->gvt; 1185 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1186 1187 if (atomic_read(&s->running_workload_num)) { 1188 gvt_dbg_sched("wait vgpu idle\n"); 1189 1190 wait_event(scheduler->workload_complete_wq, 1191 !atomic_read(&s->running_workload_num)); 1192 } 1193} 1194 1195void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 1196{ 1197 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1198 struct intel_engine_cs *engine; 1199 enum intel_engine_id i; 1200 1201 gvt_dbg_core("clean workload scheduler\n"); 1202 1203 for_each_engine(engine, gvt->gt, i) { 1204 atomic_notifier_chain_unregister( 1205 &engine->context_status_notifier, 1206 &gvt->shadow_ctx_notifier_block[i]); 1207 kthread_stop(scheduler->thread[i]); 1208 } 1209} 1210 1211int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 1212{ 1213 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1214 struct intel_engine_cs *engine; 1215 enum intel_engine_id i; 1216 int ret; 1217 1218 gvt_dbg_core("init workload scheduler\n"); 1219 1220 init_waitqueue_head(&scheduler->workload_complete_wq); 1221 1222 for_each_engine(engine, gvt->gt, i) { 1223 init_waitqueue_head(&scheduler->waitq[i]); 1224 1225 scheduler->thread[i] = kthread_run(workload_thread, engine, 1226 "gvt:%s", engine->name); 1227 if (IS_ERR(scheduler->thread[i])) { 1228 gvt_err("fail to create workload thread\n"); 1229 ret = PTR_ERR(scheduler->thread[i]); 1230 goto err; 1231 } 1232 1233 gvt->shadow_ctx_notifier_block[i].notifier_call = 1234 shadow_context_status_change; 1235 atomic_notifier_chain_register(&engine->context_status_notifier, 1236 &gvt->shadow_ctx_notifier_block[i]); 1237 } 1238 1239 return 0; 1240 1241err: 1242 intel_gvt_clean_workload_scheduler(gvt); 1243 return ret; 1244} 1245 1246static void 1247i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s, 1248 struct i915_ppgtt *ppgtt) 1249{ 1250 int i; 1251 1252 if (i915_vm_is_4lvl(&ppgtt->vm)) { 1253 set_dma_address(ppgtt->pd, s->i915_context_pml4); 1254 } else { 1255 for (i = 0; i < GEN8_3LVL_PDPES; i++) { 1256 struct i915_page_directory * const pd = 1257 i915_pd_entry(ppgtt->pd, i); 1258 1259 set_dma_address(pd, s->i915_context_pdps[i]); 1260 } 1261 } 1262} 1263 1264/** 1265 * intel_vgpu_clean_submission - free submission-related resource for vGPU 1266 * @vgpu: a vGPU 1267 * 1268 * This function is called when a vGPU is being destroyed. 1269 * 1270 */ 1271void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) 1272{ 1273 struct intel_vgpu_submission *s = &vgpu->submission; 1274 struct intel_engine_cs *engine; 1275 enum intel_engine_id id; 1276 1277 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 1278 1279 i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm)); 1280 for_each_engine(engine, vgpu->gvt->gt, id) 1281 intel_context_put(s->shadow[id]); 1282 1283 kmem_cache_destroy(s->workloads); 1284} 1285 1286 1287/** 1288 * intel_vgpu_reset_submission - reset submission-related resource for vGPU 1289 * @vgpu: a vGPU 1290 * @engine_mask: engines expected to be reset 1291 * 1292 * This function is called when a vGPU is being destroyed. 1293 * 1294 */ 1295void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, 1296 intel_engine_mask_t engine_mask) 1297{ 1298 struct intel_vgpu_submission *s = &vgpu->submission; 1299 1300 if (!s->active) 1301 return; 1302 1303 intel_vgpu_clean_workloads(vgpu, engine_mask); 1304 s->ops->reset(vgpu, engine_mask); 1305} 1306 1307static void 1308i915_context_ppgtt_root_save(struct intel_vgpu_submission *s, 1309 struct i915_ppgtt *ppgtt) 1310{ 1311 int i; 1312 1313 if (i915_vm_is_4lvl(&ppgtt->vm)) { 1314 s->i915_context_pml4 = px_dma(ppgtt->pd); 1315 } else { 1316 for (i = 0; i < GEN8_3LVL_PDPES; i++) { 1317 struct i915_page_directory * const pd = 1318 i915_pd_entry(ppgtt->pd, i); 1319 1320 s->i915_context_pdps[i] = px_dma(pd); 1321 } 1322 } 1323} 1324 1325/** 1326 * intel_vgpu_setup_submission - setup submission-related resource for vGPU 1327 * @vgpu: a vGPU 1328 * 1329 * This function is called when a vGPU is being created. 1330 * 1331 * Returns: 1332 * Zero on success, negative error code if failed. 1333 * 1334 */ 1335int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 1336{ 1337 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1338 struct intel_vgpu_submission *s = &vgpu->submission; 1339 struct intel_engine_cs *engine; 1340 struct i915_ppgtt *ppgtt; 1341 enum intel_engine_id i; 1342 int ret; 1343 1344 ppgtt = i915_ppgtt_create(&i915->gt); 1345 if (IS_ERR(ppgtt)) 1346 return PTR_ERR(ppgtt); 1347 1348 i915_context_ppgtt_root_save(s, ppgtt); 1349 1350 for_each_engine(engine, vgpu->gvt->gt, i) { 1351 struct intel_context *ce; 1352 1353 INIT_LIST_HEAD(&s->workload_q_head[i]); 1354 s->shadow[i] = ERR_PTR(-EINVAL); 1355 1356 ce = intel_context_create(engine); 1357 if (IS_ERR(ce)) { 1358 ret = PTR_ERR(ce); 1359 goto out_shadow_ctx; 1360 } 1361 1362 i915_vm_put(ce->vm); 1363 ce->vm = i915_vm_get(&ppgtt->vm); 1364 intel_context_set_single_submission(ce); 1365 1366 /* Max ring buffer size */ 1367 if (!intel_uc_wants_guc_submission(&engine->gt->uc)) { 1368 const unsigned int ring_size = 512 * SZ_4K; 1369 1370 ce->ring = __intel_context_ring_size(ring_size); 1371 } 1372 1373 s->shadow[i] = ce; 1374 } 1375 1376 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); 1377 1378 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", 1379 sizeof(struct intel_vgpu_workload), 0, 1380 SLAB_HWCACHE_ALIGN, 1381 offsetof(struct intel_vgpu_workload, rb_tail), 1382 sizeof_field(struct intel_vgpu_workload, rb_tail), 1383 NULL); 1384 1385 if (!s->workloads) { 1386 ret = -ENOMEM; 1387 goto out_shadow_ctx; 1388 } 1389 1390 atomic_set(&s->running_workload_num, 0); 1391 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES); 1392 1393 memset(s->last_ctx, 0, sizeof(s->last_ctx)); 1394 1395 i915_vm_put(&ppgtt->vm); 1396 return 0; 1397 1398out_shadow_ctx: 1399 i915_context_ppgtt_root_restore(s, ppgtt); 1400 for_each_engine(engine, vgpu->gvt->gt, i) { 1401 if (IS_ERR(s->shadow[i])) 1402 break; 1403 1404 intel_context_put(s->shadow[i]); 1405 } 1406 i915_vm_put(&ppgtt->vm); 1407 return ret; 1408} 1409 1410/** 1411 * intel_vgpu_select_submission_ops - select virtual submission interface 1412 * @vgpu: a vGPU 1413 * @engine_mask: either ALL_ENGINES or target engine mask 1414 * @interface: expected vGPU virtual submission interface 1415 * 1416 * This function is called when guest configures submission interface. 1417 * 1418 * Returns: 1419 * Zero on success, negative error code if failed. 1420 * 1421 */ 1422int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, 1423 intel_engine_mask_t engine_mask, 1424 unsigned int interface) 1425{ 1426 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1427 struct intel_vgpu_submission *s = &vgpu->submission; 1428 const struct intel_vgpu_submission_ops *ops[] = { 1429 [INTEL_VGPU_EXECLIST_SUBMISSION] = 1430 &intel_vgpu_execlist_submission_ops, 1431 }; 1432 int ret; 1433 1434 if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops))) 1435 return -EINVAL; 1436 1437 if (drm_WARN_ON(&i915->drm, 1438 interface == 0 && engine_mask != ALL_ENGINES)) 1439 return -EINVAL; 1440 1441 if (s->active) 1442 s->ops->clean(vgpu, engine_mask); 1443 1444 if (interface == 0) { 1445 s->ops = NULL; 1446 s->virtual_submission_interface = 0; 1447 s->active = false; 1448 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); 1449 return 0; 1450 } 1451 1452 ret = ops[interface]->init(vgpu, engine_mask); 1453 if (ret) 1454 return ret; 1455 1456 s->ops = ops[interface]; 1457 s->virtual_submission_interface = interface; 1458 s->active = true; 1459 1460 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", 1461 vgpu->id, s->ops->name); 1462 1463 return 0; 1464} 1465 1466/** 1467 * intel_vgpu_destroy_workload - destroy a vGPU workload 1468 * @workload: workload to destroy 1469 * 1470 * This function is called when destroy a vGPU workload. 1471 * 1472 */ 1473void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload) 1474{ 1475 struct intel_vgpu_submission *s = &workload->vgpu->submission; 1476 1477 intel_context_unpin(s->shadow[workload->engine->id]); 1478 release_shadow_batch_buffer(workload); 1479 release_shadow_wa_ctx(&workload->wa_ctx); 1480 1481 if (!list_empty(&workload->lri_shadow_mm)) { 1482 struct intel_vgpu_mm *m, *mm; 1483 list_for_each_entry_safe(m, mm, &workload->lri_shadow_mm, 1484 ppgtt_mm.link) { 1485 list_del(&m->ppgtt_mm.link); 1486 intel_vgpu_mm_put(m); 1487 } 1488 } 1489 1490 GEM_BUG_ON(!list_empty(&workload->lri_shadow_mm)); 1491 if (workload->shadow_mm) 1492 intel_vgpu_mm_put(workload->shadow_mm); 1493 1494 kmem_cache_free(s->workloads, workload); 1495} 1496 1497static struct intel_vgpu_workload * 1498alloc_workload(struct intel_vgpu *vgpu) 1499{ 1500 struct intel_vgpu_submission *s = &vgpu->submission; 1501 struct intel_vgpu_workload *workload; 1502 1503 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL); 1504 if (!workload) 1505 return ERR_PTR(-ENOMEM); 1506 1507 INIT_LIST_HEAD(&workload->list); 1508 INIT_LIST_HEAD(&workload->shadow_bb); 1509 INIT_LIST_HEAD(&workload->lri_shadow_mm); 1510 1511 init_waitqueue_head(&workload->shadow_ctx_status_wq); 1512 atomic_set(&workload->shadow_ctx_active, 0); 1513 1514 workload->status = -EINPROGRESS; 1515 workload->vgpu = vgpu; 1516 1517 return workload; 1518} 1519 1520#define RING_CTX_OFF(x) \ 1521 offsetof(struct execlist_ring_context, x) 1522 1523static void read_guest_pdps(struct intel_vgpu *vgpu, 1524 u64 ring_context_gpa, u32 pdp[8]) 1525{ 1526 u64 gpa; 1527 int i; 1528 1529 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); 1530 1531 for (i = 0; i < 8; i++) 1532 intel_gvt_hypervisor_read_gpa(vgpu, 1533 gpa + i * 8, &pdp[7 - i], 4); 1534} 1535 1536static int prepare_mm(struct intel_vgpu_workload *workload) 1537{ 1538 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc; 1539 struct intel_vgpu_mm *mm; 1540 struct intel_vgpu *vgpu = workload->vgpu; 1541 enum intel_gvt_gtt_type root_entry_type; 1542 u64 pdps[GVT_RING_CTX_NR_PDPS]; 1543 1544 switch (desc->addressing_mode) { 1545 case 1: /* legacy 32-bit */ 1546 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1547 break; 1548 case 3: /* legacy 64-bit */ 1549 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1550 break; 1551 default: 1552 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n"); 1553 return -EINVAL; 1554 } 1555 1556 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps); 1557 1558 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps); 1559 if (IS_ERR(mm)) 1560 return PTR_ERR(mm); 1561 1562 workload->shadow_mm = mm; 1563 return 0; 1564} 1565 1566#define same_context(a, b) (((a)->context_id == (b)->context_id) && \ 1567 ((a)->lrca == (b)->lrca)) 1568 1569/** 1570 * intel_vgpu_create_workload - create a vGPU workload 1571 * @vgpu: a vGPU 1572 * @engine: the engine 1573 * @desc: a guest context descriptor 1574 * 1575 * This function is called when creating a vGPU workload. 1576 * 1577 * Returns: 1578 * struct intel_vgpu_workload * on success, negative error code in 1579 * pointer if failed. 1580 * 1581 */ 1582struct intel_vgpu_workload * 1583intel_vgpu_create_workload(struct intel_vgpu *vgpu, 1584 const struct intel_engine_cs *engine, 1585 struct execlist_ctx_descriptor_format *desc) 1586{ 1587 struct intel_vgpu_submission *s = &vgpu->submission; 1588 struct list_head *q = workload_q_head(vgpu, engine); 1589 struct intel_vgpu_workload *last_workload = NULL; 1590 struct intel_vgpu_workload *workload = NULL; 1591 u64 ring_context_gpa; 1592 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; 1593 u32 guest_head; 1594 int ret; 1595 1596 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 1597 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT)); 1598 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) { 1599 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca); 1600 return ERR_PTR(-EINVAL); 1601 } 1602 1603 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1604 RING_CTX_OFF(ring_header.val), &head, 4); 1605 1606 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1607 RING_CTX_OFF(ring_tail.val), &tail, 4); 1608 1609 guest_head = head; 1610 1611 head &= RB_HEAD_OFF_MASK; 1612 tail &= RB_TAIL_OFF_MASK; 1613 1614 list_for_each_entry_reverse(last_workload, q, list) { 1615 1616 if (same_context(&last_workload->ctx_desc, desc)) { 1617 gvt_dbg_el("ring %s cur workload == last\n", 1618 engine->name); 1619 gvt_dbg_el("ctx head %x real head %lx\n", head, 1620 last_workload->rb_tail); 1621 /* 1622 * cannot use guest context head pointer here, 1623 * as it might not be updated at this time 1624 */ 1625 head = last_workload->rb_tail; 1626 break; 1627 } 1628 } 1629 1630 gvt_dbg_el("ring %s begin a new workload\n", engine->name); 1631 1632 /* record some ring buffer register values for scan and shadow */ 1633 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1634 RING_CTX_OFF(rb_start.val), &start, 4); 1635 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1636 RING_CTX_OFF(rb_ctrl.val), &ctl, 4); 1637 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1638 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); 1639 1640 if (!intel_gvt_ggtt_validate_range(vgpu, start, 1641 _RING_CTL_BUF_SIZE(ctl))) { 1642 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start); 1643 return ERR_PTR(-EINVAL); 1644 } 1645 1646 workload = alloc_workload(vgpu); 1647 if (IS_ERR(workload)) 1648 return workload; 1649 1650 workload->engine = engine; 1651 workload->ctx_desc = *desc; 1652 workload->ring_context_gpa = ring_context_gpa; 1653 workload->rb_head = head; 1654 workload->guest_rb_head = guest_head; 1655 workload->rb_tail = tail; 1656 workload->rb_start = start; 1657 workload->rb_ctl = ctl; 1658 1659 if (engine->id == RCS0) { 1660 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1661 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); 1662 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1663 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4); 1664 1665 workload->wa_ctx.indirect_ctx.guest_gma = 1666 indirect_ctx & INDIRECT_CTX_ADDR_MASK; 1667 workload->wa_ctx.indirect_ctx.size = 1668 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * 1669 CACHELINE_BYTES; 1670 1671 if (workload->wa_ctx.indirect_ctx.size != 0) { 1672 if (!intel_gvt_ggtt_validate_range(vgpu, 1673 workload->wa_ctx.indirect_ctx.guest_gma, 1674 workload->wa_ctx.indirect_ctx.size)) { 1675 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n", 1676 workload->wa_ctx.indirect_ctx.guest_gma); 1677 kmem_cache_free(s->workloads, workload); 1678 return ERR_PTR(-EINVAL); 1679 } 1680 } 1681 1682 workload->wa_ctx.per_ctx.guest_gma = 1683 per_ctx & PER_CTX_ADDR_MASK; 1684 workload->wa_ctx.per_ctx.valid = per_ctx & 1; 1685 if (workload->wa_ctx.per_ctx.valid) { 1686 if (!intel_gvt_ggtt_validate_range(vgpu, 1687 workload->wa_ctx.per_ctx.guest_gma, 1688 CACHELINE_BYTES)) { 1689 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n", 1690 workload->wa_ctx.per_ctx.guest_gma); 1691 kmem_cache_free(s->workloads, workload); 1692 return ERR_PTR(-EINVAL); 1693 } 1694 } 1695 } 1696 1697 gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n", 1698 workload, engine->name, head, tail, start, ctl); 1699 1700 ret = prepare_mm(workload); 1701 if (ret) { 1702 kmem_cache_free(s->workloads, workload); 1703 return ERR_PTR(ret); 1704 } 1705 1706 /* Only scan and shadow the first workload in the queue 1707 * as there is only one pre-allocated buf-obj for shadow. 1708 */ 1709 if (list_empty(q)) { 1710 intel_wakeref_t wakeref; 1711 1712 with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref) 1713 ret = intel_gvt_scan_and_shadow_workload(workload); 1714 } 1715 1716 if (ret) { 1717 if (vgpu_is_vm_unhealthy(ret)) 1718 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1719 intel_vgpu_destroy_workload(workload); 1720 return ERR_PTR(ret); 1721 } 1722 1723 ret = intel_context_pin(s->shadow[engine->id]); 1724 if (ret) { 1725 intel_vgpu_destroy_workload(workload); 1726 return ERR_PTR(ret); 1727 } 1728 1729 return workload; 1730} 1731 1732/** 1733 * intel_vgpu_queue_workload - Qeue a vGPU workload 1734 * @workload: the workload to queue in 1735 */ 1736void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) 1737{ 1738 list_add_tail(&workload->list, 1739 workload_q_head(workload->vgpu, workload->engine)); 1740 intel_gvt_kick_schedule(workload->vgpu->gvt); 1741 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]); 1742} 1743