1/* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 29#include <drm/drm_fourcc.h> 30 31#include "gem/i915_gem_pm.h" 32#include "gt/intel_ring.h" 33 34#include "i915_drv.h" 35#include "i915_reg.h" 36#include "intel_display_types.h" 37#include "intel_frontbuffer.h" 38#include "intel_overlay.h" 39 40/* Limits for overlay size. According to intel doc, the real limits are: 41 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 43 * the mininum of both. */ 44#define IMAGE_MAX_WIDTH 2048 45#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 46/* on 830 and 845 these large limits result in the card hanging */ 47#define IMAGE_MAX_WIDTH_LEGACY 1024 48#define IMAGE_MAX_HEIGHT_LEGACY 1088 49 50/* overlay register definitions */ 51/* OCMD register */ 52#define OCMD_TILED_SURFACE (0x1<<19) 53#define OCMD_MIRROR_MASK (0x3<<17) 54#define OCMD_MIRROR_MODE (0x3<<17) 55#define OCMD_MIRROR_HORIZONTAL (0x1<<17) 56#define OCMD_MIRROR_VERTICAL (0x2<<17) 57#define OCMD_MIRROR_BOTH (0x3<<17) 58#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 59#define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 60#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 61#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 62#define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 63#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 64#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 65#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 66#define OCMD_YUV_422_PACKED (0x8<<10) 67#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 68#define OCMD_YUV_420_PLANAR (0xc<<10) 69#define OCMD_YUV_422_PLANAR (0xd<<10) 70#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 71#define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 72#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 73#define OCMD_BUF_TYPE_MASK (0x1<<5) 74#define OCMD_BUF_TYPE_FRAME (0x0<<5) 75#define OCMD_BUF_TYPE_FIELD (0x1<<5) 76#define OCMD_TEST_MODE (0x1<<4) 77#define OCMD_BUFFER_SELECT (0x3<<2) 78#define OCMD_BUFFER0 (0x0<<2) 79#define OCMD_BUFFER1 (0x1<<2) 80#define OCMD_FIELD_SELECT (0x1<<2) 81#define OCMD_FIELD0 (0x0<<1) 82#define OCMD_FIELD1 (0x1<<1) 83#define OCMD_ENABLE (0x1<<0) 84 85/* OCONFIG register */ 86#define OCONF_PIPE_MASK (0x1<<18) 87#define OCONF_PIPE_A (0x0<<18) 88#define OCONF_PIPE_B (0x1<<18) 89#define OCONF_GAMMA2_ENABLE (0x1<<16) 90#define OCONF_CSC_MODE_BT601 (0x0<<5) 91#define OCONF_CSC_MODE_BT709 (0x1<<5) 92#define OCONF_CSC_BYPASS (0x1<<4) 93#define OCONF_CC_OUT_8BIT (0x1<<3) 94#define OCONF_TEST_MODE (0x1<<2) 95#define OCONF_THREE_LINE_BUFFER (0x1<<0) 96#define OCONF_TWO_LINE_BUFFER (0x0<<0) 97 98/* DCLRKM (dst-key) register */ 99#define DST_KEY_ENABLE (0x1<<31) 100#define CLK_RGB24_MASK 0x0 101#define CLK_RGB16_MASK 0x070307 102#define CLK_RGB15_MASK 0x070707 103 104#define RGB30_TO_COLORKEY(c) \ 105 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2)) 106#define RGB16_TO_COLORKEY(c) \ 107 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3)) 108#define RGB15_TO_COLORKEY(c) \ 109 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3)) 110#define RGB8I_TO_COLORKEY(c) \ 111 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0)) 112 113/* overlay flip addr flag */ 114#define OFC_UPDATE 0x1 115 116/* polyphase filter coefficients */ 117#define N_HORIZ_Y_TAPS 5 118#define N_VERT_Y_TAPS 3 119#define N_HORIZ_UV_TAPS 3 120#define N_VERT_UV_TAPS 3 121#define N_PHASES 17 122#define MAX_TAPS 5 123 124/* memory bufferd overlay registers */ 125struct overlay_registers { 126 u32 OBUF_0Y; 127 u32 OBUF_1Y; 128 u32 OBUF_0U; 129 u32 OBUF_0V; 130 u32 OBUF_1U; 131 u32 OBUF_1V; 132 u32 OSTRIDE; 133 u32 YRGB_VPH; 134 u32 UV_VPH; 135 u32 HORZ_PH; 136 u32 INIT_PHS; 137 u32 DWINPOS; 138 u32 DWINSZ; 139 u32 SWIDTH; 140 u32 SWIDTHSW; 141 u32 SHEIGHT; 142 u32 YRGBSCALE; 143 u32 UVSCALE; 144 u32 OCLRC0; 145 u32 OCLRC1; 146 u32 DCLRKV; 147 u32 DCLRKM; 148 u32 SCLRKVH; 149 u32 SCLRKVL; 150 u32 SCLRKEN; 151 u32 OCONFIG; 152 u32 OCMD; 153 u32 RESERVED1; /* 0x6C */ 154 u32 OSTART_0Y; 155 u32 OSTART_1Y; 156 u32 OSTART_0U; 157 u32 OSTART_0V; 158 u32 OSTART_1U; 159 u32 OSTART_1V; 160 u32 OTILEOFF_0Y; 161 u32 OTILEOFF_1Y; 162 u32 OTILEOFF_0U; 163 u32 OTILEOFF_0V; 164 u32 OTILEOFF_1U; 165 u32 OTILEOFF_1V; 166 u32 FASTHSCALE; /* 0xA0 */ 167 u32 UVSCALEV; /* 0xA4 */ 168 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 169 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 170 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 171 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 172 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 173 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 174 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 175 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 176 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 177}; 178 179struct intel_overlay { 180 struct drm_i915_private *i915; 181 struct intel_context *context; 182 struct intel_crtc *crtc; 183 struct i915_vma *vma; 184 struct i915_vma *old_vma; 185 struct intel_frontbuffer *frontbuffer; 186 bool active; 187 bool pfit_active; 188 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 189 u32 color_key:24; 190 u32 color_key_enabled:1; 191 u32 brightness, contrast, saturation; 192 u32 old_xscale, old_yscale; 193 /* register access */ 194 struct drm_i915_gem_object *reg_bo; 195 struct overlay_registers __iomem *regs; 196 u32 flip_addr; 197 /* flip handling */ 198 struct i915_active last_flip; 199 void (*flip_complete)(struct intel_overlay *ovl); 200}; 201 202static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 203 bool enable) 204{ 205 struct pci_dev *pdev = dev_priv->drm.pdev; 206 u8 val; 207 208 /* WA_OVERLAY_CLKGATE:alm */ 209 if (enable) 210 intel_de_write(dev_priv, DSPCLK_GATE_D, 0); 211 else 212 intel_de_write(dev_priv, DSPCLK_GATE_D, 213 OVRUNIT_CLOCK_GATE_DISABLE); 214 215 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 216 pci_bus_read_config_byte(pdev->bus, 217 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 218 if (enable) 219 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 220 else 221 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 222 pci_bus_write_config_byte(pdev->bus, 223 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 224} 225 226static struct i915_request * 227alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 228{ 229 struct i915_request *rq; 230 int err; 231 232 overlay->flip_complete = fn; 233 234 rq = i915_request_create(overlay->context); 235 if (IS_ERR(rq)) 236 return rq; 237 238 err = i915_active_add_request(&overlay->last_flip, rq); 239 if (err) { 240 i915_request_add(rq); 241 return ERR_PTR(err); 242 } 243 244 return rq; 245} 246 247/* overlay needs to be disable in OCMD reg */ 248static int intel_overlay_on(struct intel_overlay *overlay) 249{ 250 struct drm_i915_private *dev_priv = overlay->i915; 251 struct i915_request *rq; 252 u32 *cs; 253 254 drm_WARN_ON(&dev_priv->drm, overlay->active); 255 256 rq = alloc_request(overlay, NULL); 257 if (IS_ERR(rq)) 258 return PTR_ERR(rq); 259 260 cs = intel_ring_begin(rq, 4); 261 if (IS_ERR(cs)) { 262 i915_request_add(rq); 263 return PTR_ERR(cs); 264 } 265 266 overlay->active = true; 267 268 if (IS_I830(dev_priv)) 269 i830_overlay_clock_gating(dev_priv, false); 270 271 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 272 *cs++ = overlay->flip_addr | OFC_UPDATE; 273 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 274 *cs++ = MI_NOOP; 275 intel_ring_advance(rq, cs); 276 277 i915_request_add(rq); 278 279 return i915_active_wait(&overlay->last_flip); 280} 281 282static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 283 struct i915_vma *vma) 284{ 285 enum pipe pipe = overlay->crtc->pipe; 286 struct intel_frontbuffer *frontbuffer = NULL; 287 288 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 289 290 if (vma) 291 frontbuffer = intel_frontbuffer_get(vma->obj); 292 293 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, 294 INTEL_FRONTBUFFER_OVERLAY(pipe)); 295 296 if (overlay->frontbuffer) 297 intel_frontbuffer_put(overlay->frontbuffer); 298 overlay->frontbuffer = frontbuffer; 299 300 intel_frontbuffer_flip_prepare(overlay->i915, 301 INTEL_FRONTBUFFER_OVERLAY(pipe)); 302 303 overlay->old_vma = overlay->vma; 304 if (vma) 305 overlay->vma = i915_vma_get(vma); 306 else 307 overlay->vma = NULL; 308} 309 310/* overlay needs to be enabled in OCMD reg */ 311static int intel_overlay_continue(struct intel_overlay *overlay, 312 struct i915_vma *vma, 313 bool load_polyphase_filter) 314{ 315 struct drm_i915_private *dev_priv = overlay->i915; 316 struct i915_request *rq; 317 u32 flip_addr = overlay->flip_addr; 318 u32 tmp, *cs; 319 320 drm_WARN_ON(&dev_priv->drm, !overlay->active); 321 322 if (load_polyphase_filter) 323 flip_addr |= OFC_UPDATE; 324 325 /* check for underruns */ 326 tmp = intel_de_read(dev_priv, DOVSTA); 327 if (tmp & (1 << 17)) 328 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 329 330 rq = alloc_request(overlay, NULL); 331 if (IS_ERR(rq)) 332 return PTR_ERR(rq); 333 334 cs = intel_ring_begin(rq, 2); 335 if (IS_ERR(cs)) { 336 i915_request_add(rq); 337 return PTR_ERR(cs); 338 } 339 340 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 341 *cs++ = flip_addr; 342 intel_ring_advance(rq, cs); 343 344 intel_overlay_flip_prepare(overlay, vma); 345 i915_request_add(rq); 346 347 return 0; 348} 349 350static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 351{ 352 struct i915_vma *vma; 353 354 vma = fetch_and_zero(&overlay->old_vma); 355 if (drm_WARN_ON(&overlay->i915->drm, !vma)) 356 return; 357 358 intel_frontbuffer_flip_complete(overlay->i915, 359 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 360 361 i915_vma_unpin(vma); 362 i915_vma_put(vma); 363} 364 365static void 366intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 367{ 368 intel_overlay_release_old_vma(overlay); 369} 370 371static void intel_overlay_off_tail(struct intel_overlay *overlay) 372{ 373 struct drm_i915_private *dev_priv = overlay->i915; 374 375 intel_overlay_release_old_vma(overlay); 376 377 overlay->crtc->overlay = NULL; 378 overlay->crtc = NULL; 379 overlay->active = false; 380 381 if (IS_I830(dev_priv)) 382 i830_overlay_clock_gating(dev_priv, true); 383} 384 385__i915_active_call static void 386intel_overlay_last_flip_retire(struct i915_active *active) 387{ 388 struct intel_overlay *overlay = 389 container_of(active, typeof(*overlay), last_flip); 390 391 if (overlay->flip_complete) 392 overlay->flip_complete(overlay); 393} 394 395/* overlay needs to be disabled in OCMD reg */ 396static int intel_overlay_off(struct intel_overlay *overlay) 397{ 398 struct i915_request *rq; 399 u32 *cs, flip_addr = overlay->flip_addr; 400 401 drm_WARN_ON(&overlay->i915->drm, !overlay->active); 402 403 /* According to intel docs the overlay hw may hang (when switching 404 * off) without loading the filter coeffs. It is however unclear whether 405 * this applies to the disabling of the overlay or to the switching off 406 * of the hw. Do it in both cases */ 407 flip_addr |= OFC_UPDATE; 408 409 rq = alloc_request(overlay, intel_overlay_off_tail); 410 if (IS_ERR(rq)) 411 return PTR_ERR(rq); 412 413 cs = intel_ring_begin(rq, 6); 414 if (IS_ERR(cs)) { 415 i915_request_add(rq); 416 return PTR_ERR(cs); 417 } 418 419 /* wait for overlay to go idle */ 420 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 421 *cs++ = flip_addr; 422 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 423 424 /* turn overlay off */ 425 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 426 *cs++ = flip_addr; 427 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 428 429 intel_ring_advance(rq, cs); 430 431 intel_overlay_flip_prepare(overlay, NULL); 432 i915_request_add(rq); 433 434 return i915_active_wait(&overlay->last_flip); 435} 436 437/* recover from an interruption due to a signal 438 * We have to be careful not to repeat work forever an make forward progess. */ 439static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 440{ 441 return i915_active_wait(&overlay->last_flip); 442} 443 444/* Wait for pending overlay flip and release old frame. 445 * Needs to be called before the overlay register are changed 446 * via intel_overlay_(un)map_regs 447 */ 448static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 449{ 450 struct drm_i915_private *dev_priv = overlay->i915; 451 struct i915_request *rq; 452 u32 *cs; 453 454 /* 455 * Only wait if there is actually an old frame to release to 456 * guarantee forward progress. 457 */ 458 if (!overlay->old_vma) 459 return 0; 460 461 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 462 intel_overlay_release_old_vid_tail(overlay); 463 return 0; 464 } 465 466 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 467 if (IS_ERR(rq)) 468 return PTR_ERR(rq); 469 470 cs = intel_ring_begin(rq, 2); 471 if (IS_ERR(cs)) { 472 i915_request_add(rq); 473 return PTR_ERR(cs); 474 } 475 476 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 477 *cs++ = MI_NOOP; 478 intel_ring_advance(rq, cs); 479 480 i915_request_add(rq); 481 482 return i915_active_wait(&overlay->last_flip); 483} 484 485void intel_overlay_reset(struct drm_i915_private *dev_priv) 486{ 487 struct intel_overlay *overlay = dev_priv->overlay; 488 489 if (!overlay) 490 return; 491 492 overlay->old_xscale = 0; 493 overlay->old_yscale = 0; 494 overlay->crtc = NULL; 495 overlay->active = false; 496} 497 498static int packed_depth_bytes(u32 format) 499{ 500 switch (format & I915_OVERLAY_DEPTH_MASK) { 501 case I915_OVERLAY_YUV422: 502 return 4; 503 case I915_OVERLAY_YUV411: 504 /* return 6; not implemented */ 505 default: 506 return -EINVAL; 507 } 508} 509 510static int packed_width_bytes(u32 format, short width) 511{ 512 switch (format & I915_OVERLAY_DEPTH_MASK) { 513 case I915_OVERLAY_YUV422: 514 return width << 1; 515 default: 516 return -EINVAL; 517 } 518} 519 520static int uv_hsubsampling(u32 format) 521{ 522 switch (format & I915_OVERLAY_DEPTH_MASK) { 523 case I915_OVERLAY_YUV422: 524 case I915_OVERLAY_YUV420: 525 return 2; 526 case I915_OVERLAY_YUV411: 527 case I915_OVERLAY_YUV410: 528 return 4; 529 default: 530 return -EINVAL; 531 } 532} 533 534static int uv_vsubsampling(u32 format) 535{ 536 switch (format & I915_OVERLAY_DEPTH_MASK) { 537 case I915_OVERLAY_YUV420: 538 case I915_OVERLAY_YUV410: 539 return 2; 540 case I915_OVERLAY_YUV422: 541 case I915_OVERLAY_YUV411: 542 return 1; 543 default: 544 return -EINVAL; 545 } 546} 547 548static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 549{ 550 u32 sw; 551 552 if (IS_GEN(dev_priv, 2)) 553 sw = ALIGN((offset & 31) + width, 32); 554 else 555 sw = ALIGN((offset & 63) + width, 64); 556 557 if (sw == 0) 558 return 0; 559 560 return (sw - 32) >> 3; 561} 562 563static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 564 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 565 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 566 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 567 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 568 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 569 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 570 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 571 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 572 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 573 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 574 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 575 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 576 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 577 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 578 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 579 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 580 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 581}; 582 583static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 584 [ 0] = { 0x3000, 0x1800, 0x1800, }, 585 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 586 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 587 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 588 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 589 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 590 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 591 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 592 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 593 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 594 [10] = { 0xb100, 0x1eb8, 0x3620, }, 595 [11] = { 0xb100, 0x1f18, 0x34a0, }, 596 [12] = { 0xb100, 0x1f68, 0x3360, }, 597 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 598 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 599 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 600 [16] = { 0x3000, 0x0800, 0x3000, }, 601}; 602 603static void update_polyphase_filter(struct overlay_registers __iomem *regs) 604{ 605 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 606 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 607 sizeof(uv_static_hcoeffs)); 608} 609 610static bool update_scaling_factors(struct intel_overlay *overlay, 611 struct overlay_registers __iomem *regs, 612 struct drm_intel_overlay_put_image *params) 613{ 614 /* fixed point with a 12 bit shift */ 615 u32 xscale, yscale, xscale_UV, yscale_UV; 616#define FP_SHIFT 12 617#define FRACT_MASK 0xfff 618 bool scale_changed = false; 619 int uv_hscale = uv_hsubsampling(params->flags); 620 int uv_vscale = uv_vsubsampling(params->flags); 621 622 if (params->dst_width > 1) 623 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 624 params->dst_width; 625 else 626 xscale = 1 << FP_SHIFT; 627 628 if (params->dst_height > 1) 629 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 630 params->dst_height; 631 else 632 yscale = 1 << FP_SHIFT; 633 634 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 635 xscale_UV = xscale/uv_hscale; 636 yscale_UV = yscale/uv_vscale; 637 /* make the Y scale to UV scale ratio an exact multiply */ 638 xscale = xscale_UV * uv_hscale; 639 yscale = yscale_UV * uv_vscale; 640 /*} else { 641 xscale_UV = 0; 642 yscale_UV = 0; 643 }*/ 644 645 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 646 scale_changed = true; 647 overlay->old_xscale = xscale; 648 overlay->old_yscale = yscale; 649 650 iowrite32(((yscale & FRACT_MASK) << 20) | 651 ((xscale >> FP_SHIFT) << 16) | 652 ((xscale & FRACT_MASK) << 3), 653 ®s->YRGBSCALE); 654 655 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 656 ((xscale_UV >> FP_SHIFT) << 16) | 657 ((xscale_UV & FRACT_MASK) << 3), 658 ®s->UVSCALE); 659 660 iowrite32((((yscale >> FP_SHIFT) << 16) | 661 ((yscale_UV >> FP_SHIFT) << 0)), 662 ®s->UVSCALEV); 663 664 if (scale_changed) 665 update_polyphase_filter(regs); 666 667 return scale_changed; 668} 669 670static void update_colorkey(struct intel_overlay *overlay, 671 struct overlay_registers __iomem *regs) 672{ 673 const struct intel_plane_state *state = 674 to_intel_plane_state(overlay->crtc->base.primary->state); 675 u32 key = overlay->color_key; 676 u32 format = 0; 677 u32 flags = 0; 678 679 if (overlay->color_key_enabled) 680 flags |= DST_KEY_ENABLE; 681 682 if (state->uapi.visible) 683 format = state->hw.fb->format->format; 684 685 switch (format) { 686 case DRM_FORMAT_C8: 687 key = RGB8I_TO_COLORKEY(key); 688 flags |= CLK_RGB24_MASK; 689 break; 690 case DRM_FORMAT_XRGB1555: 691 key = RGB15_TO_COLORKEY(key); 692 flags |= CLK_RGB15_MASK; 693 break; 694 case DRM_FORMAT_RGB565: 695 key = RGB16_TO_COLORKEY(key); 696 flags |= CLK_RGB16_MASK; 697 break; 698 case DRM_FORMAT_XRGB2101010: 699 case DRM_FORMAT_XBGR2101010: 700 key = RGB30_TO_COLORKEY(key); 701 flags |= CLK_RGB24_MASK; 702 break; 703 default: 704 flags |= CLK_RGB24_MASK; 705 break; 706 } 707 708 iowrite32(key, ®s->DCLRKV); 709 iowrite32(flags, ®s->DCLRKM); 710} 711 712static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 713{ 714 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 715 716 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 717 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 718 case I915_OVERLAY_YUV422: 719 cmd |= OCMD_YUV_422_PLANAR; 720 break; 721 case I915_OVERLAY_YUV420: 722 cmd |= OCMD_YUV_420_PLANAR; 723 break; 724 case I915_OVERLAY_YUV411: 725 case I915_OVERLAY_YUV410: 726 cmd |= OCMD_YUV_410_PLANAR; 727 break; 728 } 729 } else { /* YUV packed */ 730 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 731 case I915_OVERLAY_YUV422: 732 cmd |= OCMD_YUV_422_PACKED; 733 break; 734 case I915_OVERLAY_YUV411: 735 cmd |= OCMD_YUV_411_PACKED; 736 break; 737 } 738 739 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 740 case I915_OVERLAY_NO_SWAP: 741 break; 742 case I915_OVERLAY_UV_SWAP: 743 cmd |= OCMD_UV_SWAP; 744 break; 745 case I915_OVERLAY_Y_SWAP: 746 cmd |= OCMD_Y_SWAP; 747 break; 748 case I915_OVERLAY_Y_AND_UV_SWAP: 749 cmd |= OCMD_Y_AND_UV_SWAP; 750 break; 751 } 752 } 753 754 return cmd; 755} 756 757static int intel_overlay_do_put_image(struct intel_overlay *overlay, 758 struct drm_i915_gem_object *new_bo, 759 struct drm_intel_overlay_put_image *params) 760{ 761 struct overlay_registers __iomem *regs = overlay->regs; 762 struct drm_i915_private *dev_priv = overlay->i915; 763 u32 swidth, swidthsw, sheight, ostride; 764 enum pipe pipe = overlay->crtc->pipe; 765 bool scale_changed = false; 766 struct i915_vma *vma; 767 int ret, tmp_width; 768 769 drm_WARN_ON(&dev_priv->drm, 770 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 771 772 ret = intel_overlay_release_old_vid(overlay); 773 if (ret != 0) 774 return ret; 775 776 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 777 778 vma = i915_gem_object_pin_to_display_plane(new_bo, 779 0, NULL, PIN_MAPPABLE); 780 if (IS_ERR(vma)) { 781 ret = PTR_ERR(vma); 782 goto out_pin_section; 783 } 784 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 785 786 if (!overlay->active) { 787 const struct intel_crtc_state *crtc_state = 788 overlay->crtc->config; 789 u32 oconfig = 0; 790 791 if (crtc_state->gamma_enable && 792 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) 793 oconfig |= OCONF_CC_OUT_8BIT; 794 if (crtc_state->gamma_enable) 795 oconfig |= OCONF_GAMMA2_ENABLE; 796 if (IS_GEN(dev_priv, 4)) 797 oconfig |= OCONF_CSC_MODE_BT709; 798 oconfig |= pipe == 0 ? 799 OCONF_PIPE_A : OCONF_PIPE_B; 800 iowrite32(oconfig, ®s->OCONFIG); 801 802 ret = intel_overlay_on(overlay); 803 if (ret != 0) 804 goto out_unpin; 805 } 806 807 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 808 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 809 810 if (params->flags & I915_OVERLAY_YUV_PACKED) 811 tmp_width = packed_width_bytes(params->flags, 812 params->src_width); 813 else 814 tmp_width = params->src_width; 815 816 swidth = params->src_width; 817 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 818 sheight = params->src_height; 819 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 820 ostride = params->stride_Y; 821 822 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 823 int uv_hscale = uv_hsubsampling(params->flags); 824 int uv_vscale = uv_vsubsampling(params->flags); 825 u32 tmp_U, tmp_V; 826 827 swidth |= (params->src_width / uv_hscale) << 16; 828 sheight |= (params->src_height / uv_vscale) << 16; 829 830 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 831 params->src_width / uv_hscale); 832 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 833 params->src_width / uv_hscale); 834 swidthsw |= max(tmp_U, tmp_V) << 16; 835 836 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 837 ®s->OBUF_0U); 838 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 839 ®s->OBUF_0V); 840 841 ostride |= params->stride_UV << 16; 842 } 843 844 iowrite32(swidth, ®s->SWIDTH); 845 iowrite32(swidthsw, ®s->SWIDTHSW); 846 iowrite32(sheight, ®s->SHEIGHT); 847 iowrite32(ostride, ®s->OSTRIDE); 848 849 scale_changed = update_scaling_factors(overlay, regs, params); 850 851 update_colorkey(overlay, regs); 852 853 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 854 855 ret = intel_overlay_continue(overlay, vma, scale_changed); 856 if (ret) 857 goto out_unpin; 858 859 return 0; 860 861out_unpin: 862 i915_vma_unpin(vma); 863out_pin_section: 864 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 865 866 return ret; 867} 868 869int intel_overlay_switch_off(struct intel_overlay *overlay) 870{ 871 struct drm_i915_private *dev_priv = overlay->i915; 872 int ret; 873 874 drm_WARN_ON(&dev_priv->drm, 875 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 876 877 ret = intel_overlay_recover_from_interrupt(overlay); 878 if (ret != 0) 879 return ret; 880 881 if (!overlay->active) 882 return 0; 883 884 ret = intel_overlay_release_old_vid(overlay); 885 if (ret != 0) 886 return ret; 887 888 iowrite32(0, &overlay->regs->OCMD); 889 890 return intel_overlay_off(overlay); 891} 892 893static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 894 struct intel_crtc *crtc) 895{ 896 if (!crtc->active) 897 return -EINVAL; 898 899 /* can't use the overlay with double wide pipe */ 900 if (crtc->config->double_wide) 901 return -EINVAL; 902 903 return 0; 904} 905 906static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 907{ 908 struct drm_i915_private *dev_priv = overlay->i915; 909 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); 910 u32 ratio; 911 912 /* XXX: This is not the same logic as in the xorg driver, but more in 913 * line with the intel documentation for the i965 914 */ 915 if (INTEL_GEN(dev_priv) >= 4) { 916 /* on i965 use the PGM reg to read out the autoscaler values */ 917 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 918 } else { 919 if (pfit_control & VERT_AUTO_SCALE) 920 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); 921 else 922 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); 923 ratio >>= PFIT_VERT_SCALE_SHIFT; 924 } 925 926 overlay->pfit_vscale_ratio = ratio; 927} 928 929static int check_overlay_dst(struct intel_overlay *overlay, 930 struct drm_intel_overlay_put_image *rec) 931{ 932 const struct intel_crtc_state *pipe_config = 933 overlay->crtc->config; 934 935 if (rec->dst_height == 0 || rec->dst_width == 0) 936 return -EINVAL; 937 938 if (rec->dst_x < pipe_config->pipe_src_w && 939 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 940 rec->dst_y < pipe_config->pipe_src_h && 941 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 942 return 0; 943 else 944 return -EINVAL; 945} 946 947static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 948{ 949 u32 tmp; 950 951 /* downscaling limit is 8.0 */ 952 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 953 if (tmp > 7) 954 return -EINVAL; 955 956 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 957 if (tmp > 7) 958 return -EINVAL; 959 960 return 0; 961} 962 963static int check_overlay_src(struct drm_i915_private *dev_priv, 964 struct drm_intel_overlay_put_image *rec, 965 struct drm_i915_gem_object *new_bo) 966{ 967 int uv_hscale = uv_hsubsampling(rec->flags); 968 int uv_vscale = uv_vsubsampling(rec->flags); 969 u32 stride_mask; 970 int depth; 971 u32 tmp; 972 973 /* check src dimensions */ 974 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 975 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 976 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 977 return -EINVAL; 978 } else { 979 if (rec->src_height > IMAGE_MAX_HEIGHT || 980 rec->src_width > IMAGE_MAX_WIDTH) 981 return -EINVAL; 982 } 983 984 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 985 if (rec->src_height < N_VERT_Y_TAPS*4 || 986 rec->src_width < N_HORIZ_Y_TAPS*4) 987 return -EINVAL; 988 989 /* check alignment constraints */ 990 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 991 case I915_OVERLAY_RGB: 992 /* not implemented */ 993 return -EINVAL; 994 995 case I915_OVERLAY_YUV_PACKED: 996 if (uv_vscale != 1) 997 return -EINVAL; 998 999 depth = packed_depth_bytes(rec->flags); 1000 if (depth < 0) 1001 return depth; 1002 1003 /* ignore UV planes */ 1004 rec->stride_UV = 0; 1005 rec->offset_U = 0; 1006 rec->offset_V = 0; 1007 /* check pixel alignment */ 1008 if (rec->offset_Y % depth) 1009 return -EINVAL; 1010 break; 1011 1012 case I915_OVERLAY_YUV_PLANAR: 1013 if (uv_vscale < 0 || uv_hscale < 0) 1014 return -EINVAL; 1015 /* no offset restrictions for planar formats */ 1016 break; 1017 1018 default: 1019 return -EINVAL; 1020 } 1021 1022 if (rec->src_width % uv_hscale) 1023 return -EINVAL; 1024 1025 /* stride checking */ 1026 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1027 stride_mask = 255; 1028 else 1029 stride_mask = 63; 1030 1031 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1032 return -EINVAL; 1033 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1034 return -EINVAL; 1035 1036 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1037 4096 : 8192; 1038 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1039 return -EINVAL; 1040 1041 /* check buffer dimensions */ 1042 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1043 case I915_OVERLAY_RGB: 1044 case I915_OVERLAY_YUV_PACKED: 1045 /* always 4 Y values per depth pixels */ 1046 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1047 return -EINVAL; 1048 1049 tmp = rec->stride_Y*rec->src_height; 1050 if (rec->offset_Y + tmp > new_bo->base.size) 1051 return -EINVAL; 1052 break; 1053 1054 case I915_OVERLAY_YUV_PLANAR: 1055 if (rec->src_width > rec->stride_Y) 1056 return -EINVAL; 1057 if (rec->src_width/uv_hscale > rec->stride_UV) 1058 return -EINVAL; 1059 1060 tmp = rec->stride_Y * rec->src_height; 1061 if (rec->offset_Y + tmp > new_bo->base.size) 1062 return -EINVAL; 1063 1064 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1065 if (rec->offset_U + tmp > new_bo->base.size || 1066 rec->offset_V + tmp > new_bo->base.size) 1067 return -EINVAL; 1068 break; 1069 } 1070 1071 return 0; 1072} 1073 1074int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1075 struct drm_file *file_priv) 1076{ 1077 struct drm_intel_overlay_put_image *params = data; 1078 struct drm_i915_private *dev_priv = to_i915(dev); 1079 struct intel_overlay *overlay; 1080 struct drm_crtc *drmmode_crtc; 1081 struct intel_crtc *crtc; 1082 struct drm_i915_gem_object *new_bo; 1083 int ret; 1084 1085 overlay = dev_priv->overlay; 1086 if (!overlay) { 1087 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1088 return -ENODEV; 1089 } 1090 1091 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1092 drm_modeset_lock_all(dev); 1093 ret = intel_overlay_switch_off(overlay); 1094 drm_modeset_unlock_all(dev); 1095 1096 return ret; 1097 } 1098 1099 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1100 if (!drmmode_crtc) 1101 return -ENOENT; 1102 crtc = to_intel_crtc(drmmode_crtc); 1103 1104 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1105 if (!new_bo) 1106 return -ENOENT; 1107 1108 drm_modeset_lock_all(dev); 1109 1110 if (i915_gem_object_is_tiled(new_bo)) { 1111 drm_dbg_kms(&dev_priv->drm, 1112 "buffer used for overlay image can not be tiled\n"); 1113 ret = -EINVAL; 1114 goto out_unlock; 1115 } 1116 1117 ret = intel_overlay_recover_from_interrupt(overlay); 1118 if (ret != 0) 1119 goto out_unlock; 1120 1121 if (overlay->crtc != crtc) { 1122 ret = intel_overlay_switch_off(overlay); 1123 if (ret != 0) 1124 goto out_unlock; 1125 1126 ret = check_overlay_possible_on_crtc(overlay, crtc); 1127 if (ret != 0) 1128 goto out_unlock; 1129 1130 overlay->crtc = crtc; 1131 crtc->overlay = overlay; 1132 1133 /* line too wide, i.e. one-line-mode */ 1134 if (crtc->config->pipe_src_w > 1024 && 1135 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1136 overlay->pfit_active = true; 1137 update_pfit_vscale_ratio(overlay); 1138 } else 1139 overlay->pfit_active = false; 1140 } 1141 1142 ret = check_overlay_dst(overlay, params); 1143 if (ret != 0) 1144 goto out_unlock; 1145 1146 if (overlay->pfit_active) { 1147 params->dst_y = (((u32)params->dst_y << 12) / 1148 overlay->pfit_vscale_ratio); 1149 /* shifting right rounds downwards, so add 1 */ 1150 params->dst_height = (((u32)params->dst_height << 12) / 1151 overlay->pfit_vscale_ratio) + 1; 1152 } 1153 1154 if (params->src_scan_height > params->src_height || 1155 params->src_scan_width > params->src_width) { 1156 ret = -EINVAL; 1157 goto out_unlock; 1158 } 1159 1160 ret = check_overlay_src(dev_priv, params, new_bo); 1161 if (ret != 0) 1162 goto out_unlock; 1163 1164 /* Check scaling after src size to prevent a divide-by-zero. */ 1165 ret = check_overlay_scaling(params); 1166 if (ret != 0) 1167 goto out_unlock; 1168 1169 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1170 if (ret != 0) 1171 goto out_unlock; 1172 1173 drm_modeset_unlock_all(dev); 1174 i915_gem_object_put(new_bo); 1175 1176 return 0; 1177 1178out_unlock: 1179 drm_modeset_unlock_all(dev); 1180 i915_gem_object_put(new_bo); 1181 1182 return ret; 1183} 1184 1185static void update_reg_attrs(struct intel_overlay *overlay, 1186 struct overlay_registers __iomem *regs) 1187{ 1188 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1189 ®s->OCLRC0); 1190 iowrite32(overlay->saturation, ®s->OCLRC1); 1191} 1192 1193static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1194{ 1195 int i; 1196 1197 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1198 return false; 1199 1200 for (i = 0; i < 3; i++) { 1201 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1202 return false; 1203 } 1204 1205 return true; 1206} 1207 1208static bool check_gamma5_errata(u32 gamma5) 1209{ 1210 int i; 1211 1212 for (i = 0; i < 3; i++) { 1213 if (((gamma5 >> i*8) & 0xff) == 0x80) 1214 return false; 1215 } 1216 1217 return true; 1218} 1219 1220static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1221{ 1222 if (!check_gamma_bounds(0, attrs->gamma0) || 1223 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1224 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1225 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1226 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1227 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1228 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1229 return -EINVAL; 1230 1231 if (!check_gamma5_errata(attrs->gamma5)) 1232 return -EINVAL; 1233 1234 return 0; 1235} 1236 1237int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1238 struct drm_file *file_priv) 1239{ 1240 struct drm_intel_overlay_attrs *attrs = data; 1241 struct drm_i915_private *dev_priv = to_i915(dev); 1242 struct intel_overlay *overlay; 1243 int ret; 1244 1245 overlay = dev_priv->overlay; 1246 if (!overlay) { 1247 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1248 return -ENODEV; 1249 } 1250 1251 drm_modeset_lock_all(dev); 1252 1253 ret = -EINVAL; 1254 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1255 attrs->color_key = overlay->color_key; 1256 attrs->brightness = overlay->brightness; 1257 attrs->contrast = overlay->contrast; 1258 attrs->saturation = overlay->saturation; 1259 1260 if (!IS_GEN(dev_priv, 2)) { 1261 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1262 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1263 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1264 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1265 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1266 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1267 } 1268 } else { 1269 if (attrs->brightness < -128 || attrs->brightness > 127) 1270 goto out_unlock; 1271 if (attrs->contrast > 255) 1272 goto out_unlock; 1273 if (attrs->saturation > 1023) 1274 goto out_unlock; 1275 1276 overlay->color_key = attrs->color_key; 1277 overlay->brightness = attrs->brightness; 1278 overlay->contrast = attrs->contrast; 1279 overlay->saturation = attrs->saturation; 1280 1281 update_reg_attrs(overlay, overlay->regs); 1282 1283 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1284 if (IS_GEN(dev_priv, 2)) 1285 goto out_unlock; 1286 1287 if (overlay->active) { 1288 ret = -EBUSY; 1289 goto out_unlock; 1290 } 1291 1292 ret = check_gamma(attrs); 1293 if (ret) 1294 goto out_unlock; 1295 1296 intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1297 intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1298 intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1299 intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1300 intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1301 intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1302 } 1303 } 1304 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1305 1306 ret = 0; 1307out_unlock: 1308 drm_modeset_unlock_all(dev); 1309 1310 return ret; 1311} 1312 1313static int get_registers(struct intel_overlay *overlay, bool use_phys) 1314{ 1315 struct drm_i915_private *i915 = overlay->i915; 1316 struct drm_i915_gem_object *obj; 1317 struct i915_vma *vma; 1318 int err; 1319 1320 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1321 if (IS_ERR(obj)) 1322 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1323 if (IS_ERR(obj)) 1324 return PTR_ERR(obj); 1325 1326 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1327 if (IS_ERR(vma)) { 1328 err = PTR_ERR(vma); 1329 goto err_put_bo; 1330 } 1331 1332 if (use_phys) 1333 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1334 else 1335 overlay->flip_addr = i915_ggtt_offset(vma); 1336 overlay->regs = i915_vma_pin_iomap(vma); 1337 i915_vma_unpin(vma); 1338 1339 if (IS_ERR(overlay->regs)) { 1340 err = PTR_ERR(overlay->regs); 1341 goto err_put_bo; 1342 } 1343 1344 overlay->reg_bo = obj; 1345 return 0; 1346 1347err_put_bo: 1348 i915_gem_object_put(obj); 1349 return err; 1350} 1351 1352void intel_overlay_setup(struct drm_i915_private *dev_priv) 1353{ 1354 struct intel_overlay *overlay; 1355 struct intel_engine_cs *engine; 1356 int ret; 1357 1358 if (!HAS_OVERLAY(dev_priv)) 1359 return; 1360 1361 engine = dev_priv->gt.engine[RCS0]; 1362 if (!engine || !engine->kernel_context) 1363 return; 1364 1365 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1366 if (!overlay) 1367 return; 1368 1369 overlay->i915 = dev_priv; 1370 overlay->context = engine->kernel_context; 1371 GEM_BUG_ON(!overlay->context); 1372 1373 overlay->color_key = 0x0101fe; 1374 overlay->color_key_enabled = true; 1375 overlay->brightness = -19; 1376 overlay->contrast = 75; 1377 overlay->saturation = 146; 1378 1379 i915_active_init(&overlay->last_flip, 1380 NULL, intel_overlay_last_flip_retire); 1381 1382 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1383 if (ret) 1384 goto out_free; 1385 1386 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1387 update_polyphase_filter(overlay->regs); 1388 update_reg_attrs(overlay, overlay->regs); 1389 1390 dev_priv->overlay = overlay; 1391 drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1392 return; 1393 1394out_free: 1395 kfree(overlay); 1396} 1397 1398void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1399{ 1400 struct intel_overlay *overlay; 1401 1402 overlay = fetch_and_zero(&dev_priv->overlay); 1403 if (!overlay) 1404 return; 1405 1406 /* 1407 * The bo's should be free'd by the generic code already. 1408 * Furthermore modesetting teardown happens beforehand so the 1409 * hardware should be off already. 1410 */ 1411 drm_WARN_ON(&dev_priv->drm, overlay->active); 1412 1413 i915_gem_object_put(overlay->reg_bo); 1414 i915_active_fini(&overlay->last_flip); 1415 1416 kfree(overlay); 1417} 1418 1419#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1420 1421struct intel_overlay_error_state { 1422 struct overlay_registers regs; 1423 unsigned long base; 1424 u32 dovsta; 1425 u32 isr; 1426}; 1427 1428struct intel_overlay_error_state * 1429intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1430{ 1431 struct intel_overlay *overlay = dev_priv->overlay; 1432 struct intel_overlay_error_state *error; 1433 1434 if (!overlay || !overlay->active) 1435 return NULL; 1436 1437 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1438 if (error == NULL) 1439 return NULL; 1440 1441 error->dovsta = intel_de_read(dev_priv, DOVSTA); 1442 error->isr = intel_de_read(dev_priv, GEN2_ISR); 1443 error->base = overlay->flip_addr; 1444 1445 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1446 1447 return error; 1448} 1449 1450void 1451intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1452 struct intel_overlay_error_state *error) 1453{ 1454 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1455 error->dovsta, error->isr); 1456 i915_error_printf(m, " Register file at 0x%08lx:\n", 1457 error->base); 1458 1459#define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1460 P(OBUF_0Y); 1461 P(OBUF_1Y); 1462 P(OBUF_0U); 1463 P(OBUF_0V); 1464 P(OBUF_1U); 1465 P(OBUF_1V); 1466 P(OSTRIDE); 1467 P(YRGB_VPH); 1468 P(UV_VPH); 1469 P(HORZ_PH); 1470 P(INIT_PHS); 1471 P(DWINPOS); 1472 P(DWINSZ); 1473 P(SWIDTH); 1474 P(SWIDTHSW); 1475 P(SHEIGHT); 1476 P(YRGBSCALE); 1477 P(UVSCALE); 1478 P(OCLRC0); 1479 P(OCLRC1); 1480 P(DCLRKV); 1481 P(DCLRKM); 1482 P(SCLRKVH); 1483 P(SCLRKVL); 1484 P(SCLRKEN); 1485 P(OCONFIG); 1486 P(OCMD); 1487 P(OSTART_0Y); 1488 P(OSTART_1Y); 1489 P(OSTART_0U); 1490 P(OSTART_0V); 1491 P(OSTART_1U); 1492 P(OSTART_1V); 1493 P(OTILEOFF_0Y); 1494 P(OTILEOFF_1Y); 1495 P(OTILEOFF_0U); 1496 P(OTILEOFF_0V); 1497 P(OTILEOFF_1U); 1498 P(OTILEOFF_1V); 1499 P(FASTHSCALE); 1500 P(UVSCALEV); 1501#undef P 1502} 1503 1504#endif 1505