1/* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29#include <linux/delay.h> 30#include <linux/hdmi.h> 31#include <linux/i2c.h> 32#include <linux/slab.h> 33 34#include <drm/drm_atomic_helper.h> 35#include <drm/drm_crtc.h> 36#include <drm/drm_edid.h> 37#include <drm/drm_hdcp.h> 38#include <drm/drm_scdc_helper.h> 39#include <drm/intel_lpe_audio.h> 40 41#include "i915_debugfs.h" 42#include "i915_drv.h" 43#include "intel_atomic.h" 44#include "intel_audio.h" 45#include "intel_connector.h" 46#include "intel_ddi.h" 47#include "intel_display_types.h" 48#include "intel_dp.h" 49#include "intel_dpio_phy.h" 50#include "intel_fifo_underrun.h" 51#include "intel_gmbus.h" 52#include "intel_hdcp.h" 53#include "intel_hdmi.h" 54#include "intel_hotplug.h" 55#include "intel_lspcon.h" 56#include "intel_panel.h" 57#include "intel_sdvo.h" 58#include "intel_sideband.h" 59 60static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 61{ 62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 63} 64 65static void 66assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 67{ 68 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 69 struct drm_i915_private *dev_priv = to_i915(dev); 70 u32 enabled_bits; 71 72 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 73 74 drm_WARN(dev, 75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 76 "HDMI port enabled, expecting disabled\n"); 77} 78 79static void 80assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 81 enum transcoder cpu_transcoder) 82{ 83 drm_WARN(&dev_priv->drm, 84 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 85 TRANS_DDI_FUNC_ENABLE, 86 "HDMI transcoder function enabled, expecting disabled\n"); 87} 88 89struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) 90{ 91 struct intel_digital_port *dig_port = 92 container_of(&encoder->base, struct intel_digital_port, 93 base.base); 94 return &dig_port->hdmi; 95} 96 97static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) 98{ 99 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 100} 101 102static u32 g4x_infoframe_index(unsigned int type) 103{ 104 switch (type) { 105 case HDMI_PACKET_TYPE_GAMUT_METADATA: 106 return VIDEO_DIP_SELECT_GAMUT; 107 case HDMI_INFOFRAME_TYPE_AVI: 108 return VIDEO_DIP_SELECT_AVI; 109 case HDMI_INFOFRAME_TYPE_SPD: 110 return VIDEO_DIP_SELECT_SPD; 111 case HDMI_INFOFRAME_TYPE_VENDOR: 112 return VIDEO_DIP_SELECT_VENDOR; 113 default: 114 MISSING_CASE(type); 115 return 0; 116 } 117} 118 119static u32 g4x_infoframe_enable(unsigned int type) 120{ 121 switch (type) { 122 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 123 return VIDEO_DIP_ENABLE_GCP; 124 case HDMI_PACKET_TYPE_GAMUT_METADATA: 125 return VIDEO_DIP_ENABLE_GAMUT; 126 case DP_SDP_VSC: 127 return 0; 128 case HDMI_INFOFRAME_TYPE_AVI: 129 return VIDEO_DIP_ENABLE_AVI; 130 case HDMI_INFOFRAME_TYPE_SPD: 131 return VIDEO_DIP_ENABLE_SPD; 132 case HDMI_INFOFRAME_TYPE_VENDOR: 133 return VIDEO_DIP_ENABLE_VENDOR; 134 case HDMI_INFOFRAME_TYPE_DRM: 135 return 0; 136 default: 137 MISSING_CASE(type); 138 return 0; 139 } 140} 141 142static u32 hsw_infoframe_enable(unsigned int type) 143{ 144 switch (type) { 145 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 146 return VIDEO_DIP_ENABLE_GCP_HSW; 147 case HDMI_PACKET_TYPE_GAMUT_METADATA: 148 return VIDEO_DIP_ENABLE_GMP_HSW; 149 case DP_SDP_VSC: 150 return VIDEO_DIP_ENABLE_VSC_HSW; 151 case DP_SDP_PPS: 152 return VDIP_ENABLE_PPS; 153 case HDMI_INFOFRAME_TYPE_AVI: 154 return VIDEO_DIP_ENABLE_AVI_HSW; 155 case HDMI_INFOFRAME_TYPE_SPD: 156 return VIDEO_DIP_ENABLE_SPD_HSW; 157 case HDMI_INFOFRAME_TYPE_VENDOR: 158 return VIDEO_DIP_ENABLE_VS_HSW; 159 case HDMI_INFOFRAME_TYPE_DRM: 160 return VIDEO_DIP_ENABLE_DRM_GLK; 161 default: 162 MISSING_CASE(type); 163 return 0; 164 } 165} 166 167static i915_reg_t 168hsw_dip_data_reg(struct drm_i915_private *dev_priv, 169 enum transcoder cpu_transcoder, 170 unsigned int type, 171 int i) 172{ 173 switch (type) { 174 case HDMI_PACKET_TYPE_GAMUT_METADATA: 175 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 176 case DP_SDP_VSC: 177 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 178 case DP_SDP_PPS: 179 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_AVI: 181 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_SPD: 183 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 184 case HDMI_INFOFRAME_TYPE_VENDOR: 185 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 186 case HDMI_INFOFRAME_TYPE_DRM: 187 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 188 default: 189 MISSING_CASE(type); 190 return INVALID_MMIO_REG; 191 } 192} 193 194static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 195 unsigned int type) 196{ 197 switch (type) { 198 case DP_SDP_VSC: 199 return VIDEO_DIP_VSC_DATA_SIZE; 200 case DP_SDP_PPS: 201 return VIDEO_DIP_PPS_DATA_SIZE; 202 case HDMI_PACKET_TYPE_GAMUT_METADATA: 203 if (INTEL_GEN(dev_priv) >= 11) 204 return VIDEO_DIP_GMP_DATA_SIZE; 205 else 206 return VIDEO_DIP_DATA_SIZE; 207 default: 208 return VIDEO_DIP_DATA_SIZE; 209 } 210} 211 212static void g4x_write_infoframe(struct intel_encoder *encoder, 213 const struct intel_crtc_state *crtc_state, 214 unsigned int type, 215 const void *frame, ssize_t len) 216{ 217 const u32 *data = frame; 218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 219 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 220 int i; 221 222 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 223 "Writing DIP with CTL reg disabled\n"); 224 225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 226 val |= g4x_infoframe_index(type); 227 228 val &= ~g4x_infoframe_enable(type); 229 230 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 231 232 for (i = 0; i < len; i += 4) { 233 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 234 data++; 235 } 236 /* Write every possible data byte to force correct ECC calculation. */ 237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 238 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 239 240 val |= g4x_infoframe_enable(type); 241 val &= ~VIDEO_DIP_FREQ_MASK; 242 val |= VIDEO_DIP_FREQ_VSYNC; 243 244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 245 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 246} 247 248static void g4x_read_infoframe(struct intel_encoder *encoder, 249 const struct intel_crtc_state *crtc_state, 250 unsigned int type, 251 void *frame, ssize_t len) 252{ 253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 254 u32 val, *data = frame; 255 int i; 256 257 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 258 259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 260 val |= g4x_infoframe_index(type); 261 262 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 263 264 for (i = 0; i < len; i += 4) 265 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 266} 267 268static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 269 const struct intel_crtc_state *pipe_config) 270{ 271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 272 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 273 274 if ((val & VIDEO_DIP_ENABLE) == 0) 275 return 0; 276 277 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 278 return 0; 279 280 return val & (VIDEO_DIP_ENABLE_AVI | 281 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 282} 283 284static void ibx_write_infoframe(struct intel_encoder *encoder, 285 const struct intel_crtc_state *crtc_state, 286 unsigned int type, 287 const void *frame, ssize_t len) 288{ 289 const u32 *data = frame; 290 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 292 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 293 u32 val = intel_de_read(dev_priv, reg); 294 int i; 295 296 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 297 "Writing DIP with CTL reg disabled\n"); 298 299 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 300 val |= g4x_infoframe_index(type); 301 302 val &= ~g4x_infoframe_enable(type); 303 304 intel_de_write(dev_priv, reg, val); 305 306 for (i = 0; i < len; i += 4) { 307 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 308 *data); 309 data++; 310 } 311 /* Write every possible data byte to force correct ECC calculation. */ 312 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 313 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 314 315 val |= g4x_infoframe_enable(type); 316 val &= ~VIDEO_DIP_FREQ_MASK; 317 val |= VIDEO_DIP_FREQ_VSYNC; 318 319 intel_de_write(dev_priv, reg, val); 320 intel_de_posting_read(dev_priv, reg); 321} 322 323static void ibx_read_infoframe(struct intel_encoder *encoder, 324 const struct intel_crtc_state *crtc_state, 325 unsigned int type, 326 void *frame, ssize_t len) 327{ 328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 330 u32 val, *data = frame; 331 int i; 332 333 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 334 335 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 336 val |= g4x_infoframe_index(type); 337 338 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 339 340 for (i = 0; i < len; i += 4) 341 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 342} 343 344static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 345 const struct intel_crtc_state *pipe_config) 346{ 347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 348 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 349 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 350 u32 val = intel_de_read(dev_priv, reg); 351 352 if ((val & VIDEO_DIP_ENABLE) == 0) 353 return 0; 354 355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 356 return 0; 357 358 return val & (VIDEO_DIP_ENABLE_AVI | 359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 361} 362 363static void cpt_write_infoframe(struct intel_encoder *encoder, 364 const struct intel_crtc_state *crtc_state, 365 unsigned int type, 366 const void *frame, ssize_t len) 367{ 368 const u32 *data = frame; 369 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 371 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 372 u32 val = intel_de_read(dev_priv, reg); 373 int i; 374 375 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 376 "Writing DIP with CTL reg disabled\n"); 377 378 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 379 val |= g4x_infoframe_index(type); 380 381 /* The DIP control register spec says that we need to update the AVI 382 * infoframe without clearing its enable bit */ 383 if (type != HDMI_INFOFRAME_TYPE_AVI) 384 val &= ~g4x_infoframe_enable(type); 385 386 intel_de_write(dev_priv, reg, val); 387 388 for (i = 0; i < len; i += 4) { 389 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 390 *data); 391 data++; 392 } 393 /* Write every possible data byte to force correct ECC calculation. */ 394 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 395 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 396 397 val |= g4x_infoframe_enable(type); 398 val &= ~VIDEO_DIP_FREQ_MASK; 399 val |= VIDEO_DIP_FREQ_VSYNC; 400 401 intel_de_write(dev_priv, reg, val); 402 intel_de_posting_read(dev_priv, reg); 403} 404 405static void cpt_read_infoframe(struct intel_encoder *encoder, 406 const struct intel_crtc_state *crtc_state, 407 unsigned int type, 408 void *frame, ssize_t len) 409{ 410 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 412 u32 val, *data = frame; 413 int i; 414 415 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 416 417 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 418 val |= g4x_infoframe_index(type); 419 420 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 421 422 for (i = 0; i < len; i += 4) 423 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 424} 425 426static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 427 const struct intel_crtc_state *pipe_config) 428{ 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 431 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 432 433 if ((val & VIDEO_DIP_ENABLE) == 0) 434 return 0; 435 436 return val & (VIDEO_DIP_ENABLE_AVI | 437 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 438 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 439} 440 441static void vlv_write_infoframe(struct intel_encoder *encoder, 442 const struct intel_crtc_state *crtc_state, 443 unsigned int type, 444 const void *frame, ssize_t len) 445{ 446 const u32 *data = frame; 447 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 449 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 450 u32 val = intel_de_read(dev_priv, reg); 451 int i; 452 453 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 454 "Writing DIP with CTL reg disabled\n"); 455 456 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 457 val |= g4x_infoframe_index(type); 458 459 val &= ~g4x_infoframe_enable(type); 460 461 intel_de_write(dev_priv, reg, val); 462 463 for (i = 0; i < len; i += 4) { 464 intel_de_write(dev_priv, 465 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 466 data++; 467 } 468 /* Write every possible data byte to force correct ECC calculation. */ 469 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 470 intel_de_write(dev_priv, 471 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 472 473 val |= g4x_infoframe_enable(type); 474 val &= ~VIDEO_DIP_FREQ_MASK; 475 val |= VIDEO_DIP_FREQ_VSYNC; 476 477 intel_de_write(dev_priv, reg, val); 478 intel_de_posting_read(dev_priv, reg); 479} 480 481static void vlv_read_infoframe(struct intel_encoder *encoder, 482 const struct intel_crtc_state *crtc_state, 483 unsigned int type, 484 void *frame, ssize_t len) 485{ 486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 488 u32 val, *data = frame; 489 int i; 490 491 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 492 493 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 494 val |= g4x_infoframe_index(type); 495 496 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 497 498 for (i = 0; i < len; i += 4) 499 *data++ = intel_de_read(dev_priv, 500 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 501} 502 503static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 504 const struct intel_crtc_state *pipe_config) 505{ 506 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 507 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 508 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 509 510 if ((val & VIDEO_DIP_ENABLE) == 0) 511 return 0; 512 513 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 514 return 0; 515 516 return val & (VIDEO_DIP_ENABLE_AVI | 517 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 518 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 519} 520 521static void hsw_write_infoframe(struct intel_encoder *encoder, 522 const struct intel_crtc_state *crtc_state, 523 unsigned int type, 524 const void *frame, ssize_t len) 525{ 526 const u32 *data = frame; 527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 529 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 530 int data_size; 531 int i; 532 u32 val = intel_de_read(dev_priv, ctl_reg); 533 534 data_size = hsw_dip_data_size(dev_priv, type); 535 536 drm_WARN_ON(&dev_priv->drm, len > data_size); 537 538 val &= ~hsw_infoframe_enable(type); 539 intel_de_write(dev_priv, ctl_reg, val); 540 541 for (i = 0; i < len; i += 4) { 542 intel_de_write(dev_priv, 543 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 544 *data); 545 data++; 546 } 547 /* Write every possible data byte to force correct ECC calculation. */ 548 for (; i < data_size; i += 4) 549 intel_de_write(dev_priv, 550 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 551 0); 552 553 val |= hsw_infoframe_enable(type); 554 intel_de_write(dev_priv, ctl_reg, val); 555 intel_de_posting_read(dev_priv, ctl_reg); 556} 557 558static void hsw_read_infoframe(struct intel_encoder *encoder, 559 const struct intel_crtc_state *crtc_state, 560 unsigned int type, 561 void *frame, ssize_t len) 562{ 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 565 u32 val, *data = frame; 566 int i; 567 568 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 569 570 for (i = 0; i < len; i += 4) 571 *data++ = intel_de_read(dev_priv, 572 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 573} 574 575static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 576 const struct intel_crtc_state *pipe_config) 577{ 578 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 579 u32 val = intel_de_read(dev_priv, 580 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 581 u32 mask; 582 583 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 584 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 585 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 586 587 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 588 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 589 590 return val & mask; 591} 592 593static const u8 infoframe_type_to_idx[] = { 594 HDMI_PACKET_TYPE_GENERAL_CONTROL, 595 HDMI_PACKET_TYPE_GAMUT_METADATA, 596 DP_SDP_VSC, 597 HDMI_INFOFRAME_TYPE_AVI, 598 HDMI_INFOFRAME_TYPE_SPD, 599 HDMI_INFOFRAME_TYPE_VENDOR, 600 HDMI_INFOFRAME_TYPE_DRM, 601}; 602 603u32 intel_hdmi_infoframe_enable(unsigned int type) 604{ 605 int i; 606 607 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 608 if (infoframe_type_to_idx[i] == type) 609 return BIT(i); 610 } 611 612 return 0; 613} 614 615u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 616 const struct intel_crtc_state *crtc_state) 617{ 618 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 619 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 620 u32 val, ret = 0; 621 int i; 622 623 val = dig_port->infoframes_enabled(encoder, crtc_state); 624 625 /* map from hardware bits to dip idx */ 626 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 627 unsigned int type = infoframe_type_to_idx[i]; 628 629 if (HAS_DDI(dev_priv)) { 630 if (val & hsw_infoframe_enable(type)) 631 ret |= BIT(i); 632 } else { 633 if (val & g4x_infoframe_enable(type)) 634 ret |= BIT(i); 635 } 636 } 637 638 return ret; 639} 640 641/* 642 * The data we write to the DIP data buffer registers is 1 byte bigger than the 643 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 644 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 645 * used for both technologies. 646 * 647 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 648 * DW1: DB3 | DB2 | DB1 | DB0 649 * DW2: DB7 | DB6 | DB5 | DB4 650 * DW3: ... 651 * 652 * (HB is Header Byte, DB is Data Byte) 653 * 654 * The hdmi pack() functions don't know about that hardware specific hole so we 655 * trick them by giving an offset into the buffer and moving back the header 656 * bytes by one. 657 */ 658static void intel_write_infoframe(struct intel_encoder *encoder, 659 const struct intel_crtc_state *crtc_state, 660 enum hdmi_infoframe_type type, 661 const union hdmi_infoframe *frame) 662{ 663 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 664 u8 buffer[VIDEO_DIP_DATA_SIZE]; 665 ssize_t len; 666 667 if ((crtc_state->infoframes.enable & 668 intel_hdmi_infoframe_enable(type)) == 0) 669 return; 670 671 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 672 return; 673 674 /* see comment above for the reason for this offset */ 675 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 676 if (drm_WARN_ON(encoder->base.dev, len < 0)) 677 return; 678 679 /* Insert the 'hole' (see big comment above) at position 3 */ 680 memmove(&buffer[0], &buffer[1], 3); 681 buffer[3] = 0; 682 len++; 683 684 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 685} 686 687void intel_read_infoframe(struct intel_encoder *encoder, 688 const struct intel_crtc_state *crtc_state, 689 enum hdmi_infoframe_type type, 690 union hdmi_infoframe *frame) 691{ 692 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 693 u8 buffer[VIDEO_DIP_DATA_SIZE]; 694 int ret; 695 696 if ((crtc_state->infoframes.enable & 697 intel_hdmi_infoframe_enable(type)) == 0) 698 return; 699 700 dig_port->read_infoframe(encoder, crtc_state, 701 type, buffer, sizeof(buffer)); 702 703 /* Fill the 'hole' (see big comment above) at position 3 */ 704 memmove(&buffer[1], &buffer[0], 3); 705 706 /* see comment above for the reason for this offset */ 707 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 708 if (ret) { 709 drm_dbg_kms(encoder->base.dev, 710 "Failed to unpack infoframe type 0x%02x\n", type); 711 return; 712 } 713 714 if (frame->any.type != type) 715 drm_dbg_kms(encoder->base.dev, 716 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 717 frame->any.type, type); 718} 719 720static bool 721intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 722 struct intel_crtc_state *crtc_state, 723 struct drm_connector_state *conn_state) 724{ 725 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 726 const struct drm_display_mode *adjusted_mode = 727 &crtc_state->hw.adjusted_mode; 728 struct drm_connector *connector = conn_state->connector; 729 int ret; 730 731 if (!crtc_state->has_infoframe) 732 return true; 733 734 crtc_state->infoframes.enable |= 735 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 736 737 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 738 adjusted_mode); 739 if (ret) 740 return false; 741 742 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 743 frame->colorspace = HDMI_COLORSPACE_YUV420; 744 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 745 frame->colorspace = HDMI_COLORSPACE_YUV444; 746 else 747 frame->colorspace = HDMI_COLORSPACE_RGB; 748 749 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 750 751 /* nonsense combination */ 752 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 753 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 754 755 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 756 drm_hdmi_avi_infoframe_quant_range(frame, connector, 757 adjusted_mode, 758 crtc_state->limited_color_range ? 759 HDMI_QUANTIZATION_RANGE_LIMITED : 760 HDMI_QUANTIZATION_RANGE_FULL); 761 } else { 762 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 763 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 764 } 765 766 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 767 768 /* TODO: handle pixel repetition for YCBCR420 outputs */ 769 770 ret = hdmi_avi_infoframe_check(frame); 771 if (drm_WARN_ON(encoder->base.dev, ret)) 772 return false; 773 774 return true; 775} 776 777static bool 778intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 779 struct intel_crtc_state *crtc_state, 780 struct drm_connector_state *conn_state) 781{ 782 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 783 int ret; 784 785 if (!crtc_state->has_infoframe) 786 return true; 787 788 crtc_state->infoframes.enable |= 789 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 790 791 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 792 if (drm_WARN_ON(encoder->base.dev, ret)) 793 return false; 794 795 frame->sdi = HDMI_SPD_SDI_PC; 796 797 ret = hdmi_spd_infoframe_check(frame); 798 if (drm_WARN_ON(encoder->base.dev, ret)) 799 return false; 800 801 return true; 802} 803 804static bool 805intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 806 struct intel_crtc_state *crtc_state, 807 struct drm_connector_state *conn_state) 808{ 809 struct hdmi_vendor_infoframe *frame = 810 &crtc_state->infoframes.hdmi.vendor.hdmi; 811 const struct drm_display_info *info = 812 &conn_state->connector->display_info; 813 int ret; 814 815 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 816 return true; 817 818 crtc_state->infoframes.enable |= 819 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 820 821 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 822 conn_state->connector, 823 &crtc_state->hw.adjusted_mode); 824 if (drm_WARN_ON(encoder->base.dev, ret)) 825 return false; 826 827 ret = hdmi_vendor_infoframe_check(frame); 828 if (drm_WARN_ON(encoder->base.dev, ret)) 829 return false; 830 831 return true; 832} 833 834static bool 835intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 836 struct intel_crtc_state *crtc_state, 837 struct drm_connector_state *conn_state) 838{ 839 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 841 int ret; 842 843 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 844 return true; 845 846 if (!crtc_state->has_infoframe) 847 return true; 848 849 if (!conn_state->hdr_output_metadata) 850 return true; 851 852 crtc_state->infoframes.enable |= 853 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 854 855 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 856 if (ret < 0) { 857 drm_dbg_kms(&dev_priv->drm, 858 "couldn't set HDR metadata in infoframe\n"); 859 return false; 860 } 861 862 ret = hdmi_drm_infoframe_check(frame); 863 if (drm_WARN_ON(&dev_priv->drm, ret)) 864 return false; 865 866 return true; 867} 868 869static void g4x_set_infoframes(struct intel_encoder *encoder, 870 bool enable, 871 const struct intel_crtc_state *crtc_state, 872 const struct drm_connector_state *conn_state) 873{ 874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 875 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 876 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 877 i915_reg_t reg = VIDEO_DIP_CTL; 878 u32 val = intel_de_read(dev_priv, reg); 879 u32 port = VIDEO_DIP_PORT(encoder->port); 880 881 assert_hdmi_port_disabled(intel_hdmi); 882 883 /* If the registers were not initialized yet, they might be zeroes, 884 * which means we're selecting the AVI DIP and we're setting its 885 * frequency to once. This seems to really confuse the HW and make 886 * things stop working (the register spec says the AVI always needs to 887 * be sent every VSync). So here we avoid writing to the register more 888 * than we need and also explicitly select the AVI DIP and explicitly 889 * set its frequency to every VSync. Avoiding to write it twice seems to 890 * be enough to solve the problem, but being defensive shouldn't hurt us 891 * either. */ 892 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 893 894 if (!enable) { 895 if (!(val & VIDEO_DIP_ENABLE)) 896 return; 897 if (port != (val & VIDEO_DIP_PORT_MASK)) { 898 drm_dbg_kms(&dev_priv->drm, 899 "video DIP still enabled on port %c\n", 900 (val & VIDEO_DIP_PORT_MASK) >> 29); 901 return; 902 } 903 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 904 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 905 intel_de_write(dev_priv, reg, val); 906 intel_de_posting_read(dev_priv, reg); 907 return; 908 } 909 910 if (port != (val & VIDEO_DIP_PORT_MASK)) { 911 if (val & VIDEO_DIP_ENABLE) { 912 drm_dbg_kms(&dev_priv->drm, 913 "video DIP already enabled on port %c\n", 914 (val & VIDEO_DIP_PORT_MASK) >> 29); 915 return; 916 } 917 val &= ~VIDEO_DIP_PORT_MASK; 918 val |= port; 919 } 920 921 val |= VIDEO_DIP_ENABLE; 922 val &= ~(VIDEO_DIP_ENABLE_AVI | 923 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 924 925 intel_de_write(dev_priv, reg, val); 926 intel_de_posting_read(dev_priv, reg); 927 928 intel_write_infoframe(encoder, crtc_state, 929 HDMI_INFOFRAME_TYPE_AVI, 930 &crtc_state->infoframes.avi); 931 intel_write_infoframe(encoder, crtc_state, 932 HDMI_INFOFRAME_TYPE_SPD, 933 &crtc_state->infoframes.spd); 934 intel_write_infoframe(encoder, crtc_state, 935 HDMI_INFOFRAME_TYPE_VENDOR, 936 &crtc_state->infoframes.hdmi); 937} 938 939/* 940 * Determine if default_phase=1 can be indicated in the GCP infoframe. 941 * 942 * From HDMI specification 1.4a: 943 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 944 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 945 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 946 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 947 * phase of 0 948 */ 949static bool gcp_default_phase_possible(int pipe_bpp, 950 const struct drm_display_mode *mode) 951{ 952 unsigned int pixels_per_group; 953 954 switch (pipe_bpp) { 955 case 30: 956 /* 4 pixels in 5 clocks */ 957 pixels_per_group = 4; 958 break; 959 case 36: 960 /* 2 pixels in 3 clocks */ 961 pixels_per_group = 2; 962 break; 963 case 48: 964 /* 1 pixel in 2 clocks */ 965 pixels_per_group = 1; 966 break; 967 default: 968 /* phase information not relevant for 8bpc */ 969 return false; 970 } 971 972 return mode->crtc_hdisplay % pixels_per_group == 0 && 973 mode->crtc_htotal % pixels_per_group == 0 && 974 mode->crtc_hblank_start % pixels_per_group == 0 && 975 mode->crtc_hblank_end % pixels_per_group == 0 && 976 mode->crtc_hsync_start % pixels_per_group == 0 && 977 mode->crtc_hsync_end % pixels_per_group == 0 && 978 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 979 mode->crtc_htotal/2 % pixels_per_group == 0); 980} 981 982static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 983 const struct intel_crtc_state *crtc_state, 984 const struct drm_connector_state *conn_state) 985{ 986 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 987 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 988 i915_reg_t reg; 989 990 if ((crtc_state->infoframes.enable & 991 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 992 return false; 993 994 if (HAS_DDI(dev_priv)) 995 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 996 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 997 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 998 else if (HAS_PCH_SPLIT(dev_priv)) 999 reg = TVIDEO_DIP_GCP(crtc->pipe); 1000 else 1001 return false; 1002 1003 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 1004 1005 return true; 1006} 1007 1008void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1009 struct intel_crtc_state *crtc_state) 1010{ 1011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1012 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1013 i915_reg_t reg; 1014 1015 if ((crtc_state->infoframes.enable & 1016 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1017 return; 1018 1019 if (HAS_DDI(dev_priv)) 1020 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1021 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1022 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1023 else if (HAS_PCH_SPLIT(dev_priv)) 1024 reg = TVIDEO_DIP_GCP(crtc->pipe); 1025 else 1026 return; 1027 1028 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1029} 1030 1031static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1032 struct intel_crtc_state *crtc_state, 1033 struct drm_connector_state *conn_state) 1034{ 1035 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1036 1037 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1038 return; 1039 1040 crtc_state->infoframes.enable |= 1041 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1042 1043 /* Indicate color indication for deep color mode */ 1044 if (crtc_state->pipe_bpp > 24) 1045 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1046 1047 /* Enable default_phase whenever the display mode is suitably aligned */ 1048 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1049 &crtc_state->hw.adjusted_mode)) 1050 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1051} 1052 1053static void ibx_set_infoframes(struct intel_encoder *encoder, 1054 bool enable, 1055 const struct intel_crtc_state *crtc_state, 1056 const struct drm_connector_state *conn_state) 1057{ 1058 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1060 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1061 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1062 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1063 u32 val = intel_de_read(dev_priv, reg); 1064 u32 port = VIDEO_DIP_PORT(encoder->port); 1065 1066 assert_hdmi_port_disabled(intel_hdmi); 1067 1068 /* See the big comment in g4x_set_infoframes() */ 1069 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1070 1071 if (!enable) { 1072 if (!(val & VIDEO_DIP_ENABLE)) 1073 return; 1074 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1075 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1076 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1077 intel_de_write(dev_priv, reg, val); 1078 intel_de_posting_read(dev_priv, reg); 1079 return; 1080 } 1081 1082 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1083 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1084 "DIP already enabled on port %c\n", 1085 (val & VIDEO_DIP_PORT_MASK) >> 29); 1086 val &= ~VIDEO_DIP_PORT_MASK; 1087 val |= port; 1088 } 1089 1090 val |= VIDEO_DIP_ENABLE; 1091 val &= ~(VIDEO_DIP_ENABLE_AVI | 1092 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1093 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1094 1095 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1096 val |= VIDEO_DIP_ENABLE_GCP; 1097 1098 intel_de_write(dev_priv, reg, val); 1099 intel_de_posting_read(dev_priv, reg); 1100 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_AVI, 1103 &crtc_state->infoframes.avi); 1104 intel_write_infoframe(encoder, crtc_state, 1105 HDMI_INFOFRAME_TYPE_SPD, 1106 &crtc_state->infoframes.spd); 1107 intel_write_infoframe(encoder, crtc_state, 1108 HDMI_INFOFRAME_TYPE_VENDOR, 1109 &crtc_state->infoframes.hdmi); 1110} 1111 1112static void cpt_set_infoframes(struct intel_encoder *encoder, 1113 bool enable, 1114 const struct intel_crtc_state *crtc_state, 1115 const struct drm_connector_state *conn_state) 1116{ 1117 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1119 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1120 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1121 u32 val = intel_de_read(dev_priv, reg); 1122 1123 assert_hdmi_port_disabled(intel_hdmi); 1124 1125 /* See the big comment in g4x_set_infoframes() */ 1126 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1127 1128 if (!enable) { 1129 if (!(val & VIDEO_DIP_ENABLE)) 1130 return; 1131 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1132 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1133 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1134 intel_de_write(dev_priv, reg, val); 1135 intel_de_posting_read(dev_priv, reg); 1136 return; 1137 } 1138 1139 /* Set both together, unset both together: see the spec. */ 1140 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1141 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1142 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1143 1144 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1145 val |= VIDEO_DIP_ENABLE_GCP; 1146 1147 intel_de_write(dev_priv, reg, val); 1148 intel_de_posting_read(dev_priv, reg); 1149 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_AVI, 1152 &crtc_state->infoframes.avi); 1153 intel_write_infoframe(encoder, crtc_state, 1154 HDMI_INFOFRAME_TYPE_SPD, 1155 &crtc_state->infoframes.spd); 1156 intel_write_infoframe(encoder, crtc_state, 1157 HDMI_INFOFRAME_TYPE_VENDOR, 1158 &crtc_state->infoframes.hdmi); 1159} 1160 1161static void vlv_set_infoframes(struct intel_encoder *encoder, 1162 bool enable, 1163 const struct intel_crtc_state *crtc_state, 1164 const struct drm_connector_state *conn_state) 1165{ 1166 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1168 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1169 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1170 u32 val = intel_de_read(dev_priv, reg); 1171 u32 port = VIDEO_DIP_PORT(encoder->port); 1172 1173 assert_hdmi_port_disabled(intel_hdmi); 1174 1175 /* See the big comment in g4x_set_infoframes() */ 1176 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1177 1178 if (!enable) { 1179 if (!(val & VIDEO_DIP_ENABLE)) 1180 return; 1181 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1182 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1183 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1184 intel_de_write(dev_priv, reg, val); 1185 intel_de_posting_read(dev_priv, reg); 1186 return; 1187 } 1188 1189 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1190 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1191 "DIP already enabled on port %c\n", 1192 (val & VIDEO_DIP_PORT_MASK) >> 29); 1193 val &= ~VIDEO_DIP_PORT_MASK; 1194 val |= port; 1195 } 1196 1197 val |= VIDEO_DIP_ENABLE; 1198 val &= ~(VIDEO_DIP_ENABLE_AVI | 1199 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1200 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1201 1202 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1203 val |= VIDEO_DIP_ENABLE_GCP; 1204 1205 intel_de_write(dev_priv, reg, val); 1206 intel_de_posting_read(dev_priv, reg); 1207 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_AVI, 1210 &crtc_state->infoframes.avi); 1211 intel_write_infoframe(encoder, crtc_state, 1212 HDMI_INFOFRAME_TYPE_SPD, 1213 &crtc_state->infoframes.spd); 1214 intel_write_infoframe(encoder, crtc_state, 1215 HDMI_INFOFRAME_TYPE_VENDOR, 1216 &crtc_state->infoframes.hdmi); 1217} 1218 1219static void hsw_set_infoframes(struct intel_encoder *encoder, 1220 bool enable, 1221 const struct intel_crtc_state *crtc_state, 1222 const struct drm_connector_state *conn_state) 1223{ 1224 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1225 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1226 u32 val = intel_de_read(dev_priv, reg); 1227 1228 assert_hdmi_transcoder_func_disabled(dev_priv, 1229 crtc_state->cpu_transcoder); 1230 1231 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1232 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1233 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1234 VIDEO_DIP_ENABLE_DRM_GLK); 1235 1236 if (!enable) { 1237 intel_de_write(dev_priv, reg, val); 1238 intel_de_posting_read(dev_priv, reg); 1239 return; 1240 } 1241 1242 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1243 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1244 1245 intel_de_write(dev_priv, reg, val); 1246 intel_de_posting_read(dev_priv, reg); 1247 1248 intel_write_infoframe(encoder, crtc_state, 1249 HDMI_INFOFRAME_TYPE_AVI, 1250 &crtc_state->infoframes.avi); 1251 intel_write_infoframe(encoder, crtc_state, 1252 HDMI_INFOFRAME_TYPE_SPD, 1253 &crtc_state->infoframes.spd); 1254 intel_write_infoframe(encoder, crtc_state, 1255 HDMI_INFOFRAME_TYPE_VENDOR, 1256 &crtc_state->infoframes.hdmi); 1257 intel_write_infoframe(encoder, crtc_state, 1258 HDMI_INFOFRAME_TYPE_DRM, 1259 &crtc_state->infoframes.drm); 1260} 1261 1262void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1263{ 1264 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1265 struct i2c_adapter *adapter = 1266 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1267 1268 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1269 return; 1270 1271 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1272 enable ? "Enabling" : "Disabling"); 1273 1274 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1275 adapter, enable); 1276} 1277 1278static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1279 unsigned int offset, void *buffer, size_t size) 1280{ 1281 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1282 struct intel_hdmi *hdmi = &dig_port->hdmi; 1283 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1284 hdmi->ddc_bus); 1285 int ret; 1286 u8 start = offset & 0xff; 1287 struct i2c_msg msgs[] = { 1288 { 1289 .addr = DRM_HDCP_DDC_ADDR, 1290 .flags = 0, 1291 .len = 1, 1292 .buf = &start, 1293 }, 1294 { 1295 .addr = DRM_HDCP_DDC_ADDR, 1296 .flags = I2C_M_RD, 1297 .len = size, 1298 .buf = buffer 1299 } 1300 }; 1301 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1302 if (ret == ARRAY_SIZE(msgs)) 1303 return 0; 1304 return ret >= 0 ? -EIO : ret; 1305} 1306 1307static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1308 unsigned int offset, void *buffer, size_t size) 1309{ 1310 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1311 struct intel_hdmi *hdmi = &dig_port->hdmi; 1312 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1313 hdmi->ddc_bus); 1314 int ret; 1315 u8 *write_buf; 1316 struct i2c_msg msg; 1317 1318 write_buf = kzalloc(size + 1, GFP_KERNEL); 1319 if (!write_buf) 1320 return -ENOMEM; 1321 1322 write_buf[0] = offset & 0xff; 1323 memcpy(&write_buf[1], buffer, size); 1324 1325 msg.addr = DRM_HDCP_DDC_ADDR; 1326 msg.flags = 0, 1327 msg.len = size + 1, 1328 msg.buf = write_buf; 1329 1330 ret = i2c_transfer(adapter, &msg, 1); 1331 if (ret == 1) 1332 ret = 0; 1333 else if (ret >= 0) 1334 ret = -EIO; 1335 1336 kfree(write_buf); 1337 return ret; 1338} 1339 1340static 1341int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1342 u8 *an) 1343{ 1344 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1345 struct intel_hdmi *hdmi = &dig_port->hdmi; 1346 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1347 hdmi->ddc_bus); 1348 int ret; 1349 1350 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1351 DRM_HDCP_AN_LEN); 1352 if (ret) { 1353 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1354 ret); 1355 return ret; 1356 } 1357 1358 ret = intel_gmbus_output_aksv(adapter); 1359 if (ret < 0) { 1360 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1361 return ret; 1362 } 1363 return 0; 1364} 1365 1366static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1367 u8 *bksv) 1368{ 1369 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1370 1371 int ret; 1372 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1373 DRM_HDCP_KSV_LEN); 1374 if (ret) 1375 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1376 ret); 1377 return ret; 1378} 1379 1380static 1381int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1382 u8 *bstatus) 1383{ 1384 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1385 1386 int ret; 1387 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1388 bstatus, DRM_HDCP_BSTATUS_LEN); 1389 if (ret) 1390 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1391 ret); 1392 return ret; 1393} 1394 1395static 1396int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1397 bool *repeater_present) 1398{ 1399 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1400 int ret; 1401 u8 val; 1402 1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1404 if (ret) { 1405 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1406 ret); 1407 return ret; 1408 } 1409 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1410 return 0; 1411} 1412 1413static 1414int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1415 u8 *ri_prime) 1416{ 1417 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1418 1419 int ret; 1420 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1421 ri_prime, DRM_HDCP_RI_LEN); 1422 if (ret) 1423 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1424 ret); 1425 return ret; 1426} 1427 1428static 1429int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1430 bool *ksv_ready) 1431{ 1432 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1433 int ret; 1434 u8 val; 1435 1436 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1437 if (ret) { 1438 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1439 ret); 1440 return ret; 1441 } 1442 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1443 return 0; 1444} 1445 1446static 1447int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1448 int num_downstream, u8 *ksv_fifo) 1449{ 1450 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1451 int ret; 1452 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1453 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1454 if (ret) { 1455 drm_dbg_kms(&i915->drm, 1456 "Read ksv fifo over DDC failed (%d)\n", ret); 1457 return ret; 1458 } 1459 return 0; 1460} 1461 1462static 1463int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1464 int i, u32 *part) 1465{ 1466 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1467 int ret; 1468 1469 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1470 return -EINVAL; 1471 1472 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1473 part, DRM_HDCP_V_PRIME_PART_LEN); 1474 if (ret) 1475 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1476 i, ret); 1477 return ret; 1478} 1479 1480static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1481 enum transcoder cpu_transcoder) 1482{ 1483 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1484 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1485 struct drm_crtc *crtc = connector->base.state->crtc; 1486 struct intel_crtc *intel_crtc = container_of(crtc, 1487 struct intel_crtc, base); 1488 u32 scanline; 1489 int ret; 1490 1491 for (;;) { 1492 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); 1493 if (scanline > 100 && scanline < 200) 1494 break; 1495 usleep_range(25, 50); 1496 } 1497 1498 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, 1499 false); 1500 if (ret) { 1501 drm_err(&dev_priv->drm, 1502 "Disable HDCP signalling failed (%d)\n", ret); 1503 return ret; 1504 } 1505 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, 1506 true); 1507 if (ret) { 1508 drm_err(&dev_priv->drm, 1509 "Enable HDCP signalling failed (%d)\n", ret); 1510 return ret; 1511 } 1512 1513 return 0; 1514} 1515 1516static 1517int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1518 enum transcoder cpu_transcoder, 1519 bool enable) 1520{ 1521 struct intel_hdmi *hdmi = &dig_port->hdmi; 1522 struct intel_connector *connector = hdmi->attached_connector; 1523 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1524 int ret; 1525 1526 if (!enable) 1527 usleep_range(6, 60); /* Bspec says >= 6us */ 1528 1529 ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, 1530 enable); 1531 if (ret) { 1532 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1533 enable ? "Enable" : "Disable", ret); 1534 return ret; 1535 } 1536 1537 /* 1538 * WA: To fix incorrect positioning of the window of 1539 * opportunity and enc_en signalling in KABYLAKE. 1540 */ 1541 if (IS_KABYLAKE(dev_priv) && enable) 1542 return kbl_repositioning_enc_en_signal(connector, 1543 cpu_transcoder); 1544 1545 return 0; 1546} 1547 1548static 1549bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1550 struct intel_connector *connector) 1551{ 1552 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1553 enum port port = dig_port->base.port; 1554 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1555 int ret; 1556 union { 1557 u32 reg; 1558 u8 shim[DRM_HDCP_RI_LEN]; 1559 } ri; 1560 1561 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1562 if (ret) 1563 return false; 1564 1565 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1566 1567 /* Wait for Ri prime match */ 1568 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1569 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1570 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1571 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1572 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1573 port))); 1574 return false; 1575 } 1576 return true; 1577} 1578 1579static 1580bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1581 struct intel_connector *connector) 1582{ 1583 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1584 int retry; 1585 1586 for (retry = 0; retry < 3; retry++) 1587 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1588 return true; 1589 1590 drm_err(&i915->drm, "Link check failed\n"); 1591 return false; 1592} 1593 1594struct hdcp2_hdmi_msg_timeout { 1595 u8 msg_id; 1596 u16 timeout; 1597}; 1598 1599static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1600 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1601 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1602 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1603 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1604 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1605}; 1606 1607static 1608int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1609 u8 *rx_status) 1610{ 1611 return intel_hdmi_hdcp_read(dig_port, 1612 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1613 rx_status, 1614 HDCP_2_2_HDMI_RXSTATUS_LEN); 1615} 1616 1617static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1618{ 1619 int i; 1620 1621 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1622 if (is_paired) 1623 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1624 else 1625 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1626 } 1627 1628 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1629 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1630 return hdcp2_msg_timeout[i].timeout; 1631 } 1632 1633 return -EINVAL; 1634} 1635 1636static int 1637hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1638 u8 msg_id, bool *msg_ready, 1639 ssize_t *msg_sz) 1640{ 1641 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1642 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1643 int ret; 1644 1645 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1646 if (ret < 0) { 1647 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1648 ret); 1649 return ret; 1650 } 1651 1652 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1653 rx_status[0]); 1654 1655 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1656 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1657 *msg_sz); 1658 else 1659 *msg_ready = *msg_sz; 1660 1661 return 0; 1662} 1663 1664static ssize_t 1665intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1666 u8 msg_id, bool paired) 1667{ 1668 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1669 bool msg_ready = false; 1670 int timeout, ret; 1671 ssize_t msg_sz = 0; 1672 1673 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1674 if (timeout < 0) 1675 return timeout; 1676 1677 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1678 msg_id, &msg_ready, 1679 &msg_sz), 1680 !ret && msg_ready && msg_sz, timeout * 1000, 1681 1000, 5 * 1000); 1682 if (ret) 1683 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1684 msg_id, ret, timeout); 1685 1686 return ret ? ret : msg_sz; 1687} 1688 1689static 1690int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1691 void *buf, size_t size) 1692{ 1693 unsigned int offset; 1694 1695 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1696 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1697} 1698 1699static 1700int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1701 u8 msg_id, void *buf, size_t size) 1702{ 1703 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1704 struct intel_hdmi *hdmi = &dig_port->hdmi; 1705 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1706 unsigned int offset; 1707 ssize_t ret; 1708 1709 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1710 hdcp->is_paired); 1711 if (ret < 0) 1712 return ret; 1713 1714 /* 1715 * Available msg size should be equal to or lesser than the 1716 * available buffer. 1717 */ 1718 if (ret > size) { 1719 drm_dbg_kms(&i915->drm, 1720 "msg_sz(%zd) is more than exp size(%zu)\n", 1721 ret, size); 1722 return -1; 1723 } 1724 1725 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1726 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1727 if (ret) 1728 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1729 msg_id, ret); 1730 1731 return ret; 1732} 1733 1734static 1735int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port) 1736{ 1737 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1738 int ret; 1739 1740 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1741 if (ret) 1742 return ret; 1743 1744 /* 1745 * Re-auth request and Link Integrity Failures are represented by 1746 * same bit. i.e reauth_req. 1747 */ 1748 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1749 ret = HDCP_REAUTH_REQUEST; 1750 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1751 ret = HDCP_TOPOLOGY_CHANGE; 1752 1753 return ret; 1754} 1755 1756static 1757int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1758 bool *capable) 1759{ 1760 u8 hdcp2_version; 1761 int ret; 1762 1763 *capable = false; 1764 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1765 &hdcp2_version, sizeof(hdcp2_version)); 1766 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1767 *capable = true; 1768 1769 return ret; 1770} 1771 1772static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1773 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1774 .read_bksv = intel_hdmi_hdcp_read_bksv, 1775 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1776 .repeater_present = intel_hdmi_hdcp_repeater_present, 1777 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1778 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1779 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1780 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1781 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1782 .check_link = intel_hdmi_hdcp_check_link, 1783 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1784 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1785 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1786 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1787 .protocol = HDCP_PROTOCOL_HDMI, 1788}; 1789 1790static void intel_hdmi_prepare(struct intel_encoder *encoder, 1791 const struct intel_crtc_state *crtc_state) 1792{ 1793 struct drm_device *dev = encoder->base.dev; 1794 struct drm_i915_private *dev_priv = to_i915(dev); 1795 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1796 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1797 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1798 u32 hdmi_val; 1799 1800 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1801 1802 hdmi_val = SDVO_ENCODING_HDMI; 1803 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1804 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1805 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1806 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1807 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1808 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1809 1810 if (crtc_state->pipe_bpp > 24) 1811 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1812 else 1813 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1814 1815 if (crtc_state->has_hdmi_sink) 1816 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1817 1818 if (HAS_PCH_CPT(dev_priv)) 1819 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1820 else if (IS_CHERRYVIEW(dev_priv)) 1821 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1822 else 1823 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1824 1825 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 1826 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1827} 1828 1829static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1830 enum pipe *pipe) 1831{ 1832 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1833 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1834 intel_wakeref_t wakeref; 1835 bool ret; 1836 1837 wakeref = intel_display_power_get_if_enabled(dev_priv, 1838 encoder->power_domain); 1839 if (!wakeref) 1840 return false; 1841 1842 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1843 1844 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1845 1846 return ret; 1847} 1848 1849static void intel_hdmi_get_config(struct intel_encoder *encoder, 1850 struct intel_crtc_state *pipe_config) 1851{ 1852 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1853 struct drm_device *dev = encoder->base.dev; 1854 struct drm_i915_private *dev_priv = to_i915(dev); 1855 u32 tmp, flags = 0; 1856 int dotclock; 1857 1858 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1859 1860 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1861 1862 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1863 flags |= DRM_MODE_FLAG_PHSYNC; 1864 else 1865 flags |= DRM_MODE_FLAG_NHSYNC; 1866 1867 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1868 flags |= DRM_MODE_FLAG_PVSYNC; 1869 else 1870 flags |= DRM_MODE_FLAG_NVSYNC; 1871 1872 if (tmp & HDMI_MODE_SELECT_HDMI) 1873 pipe_config->has_hdmi_sink = true; 1874 1875 pipe_config->infoframes.enable |= 1876 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1877 1878 if (pipe_config->infoframes.enable) 1879 pipe_config->has_infoframe = true; 1880 1881 if (tmp & HDMI_AUDIO_ENABLE) 1882 pipe_config->has_audio = true; 1883 1884 if (!HAS_PCH_SPLIT(dev_priv) && 1885 tmp & HDMI_COLOR_RANGE_16_235) 1886 pipe_config->limited_color_range = true; 1887 1888 pipe_config->hw.adjusted_mode.flags |= flags; 1889 1890 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1891 dotclock = pipe_config->port_clock * 2 / 3; 1892 else 1893 dotclock = pipe_config->port_clock; 1894 1895 if (pipe_config->pixel_multiplier) 1896 dotclock /= pipe_config->pixel_multiplier; 1897 1898 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1899 1900 pipe_config->lane_count = 4; 1901 1902 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1903 1904 intel_read_infoframe(encoder, pipe_config, 1905 HDMI_INFOFRAME_TYPE_AVI, 1906 &pipe_config->infoframes.avi); 1907 intel_read_infoframe(encoder, pipe_config, 1908 HDMI_INFOFRAME_TYPE_SPD, 1909 &pipe_config->infoframes.spd); 1910 intel_read_infoframe(encoder, pipe_config, 1911 HDMI_INFOFRAME_TYPE_VENDOR, 1912 &pipe_config->infoframes.hdmi); 1913} 1914 1915static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1916 const struct intel_crtc_state *pipe_config, 1917 const struct drm_connector_state *conn_state) 1918{ 1919 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1920 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1921 1922 drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink); 1923 drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n", 1924 pipe_name(crtc->pipe)); 1925 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1926} 1927 1928static void g4x_enable_hdmi(struct intel_atomic_state *state, 1929 struct intel_encoder *encoder, 1930 const struct intel_crtc_state *pipe_config, 1931 const struct drm_connector_state *conn_state) 1932{ 1933 struct drm_device *dev = encoder->base.dev; 1934 struct drm_i915_private *dev_priv = to_i915(dev); 1935 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1936 u32 temp; 1937 1938 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1939 1940 temp |= SDVO_ENABLE; 1941 if (pipe_config->has_audio) 1942 temp |= HDMI_AUDIO_ENABLE; 1943 1944 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1945 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1946 1947 if (pipe_config->has_audio) 1948 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1949} 1950 1951static void ibx_enable_hdmi(struct intel_atomic_state *state, 1952 struct intel_encoder *encoder, 1953 const struct intel_crtc_state *pipe_config, 1954 const struct drm_connector_state *conn_state) 1955{ 1956 struct drm_device *dev = encoder->base.dev; 1957 struct drm_i915_private *dev_priv = to_i915(dev); 1958 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1959 u32 temp; 1960 1961 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1962 1963 temp |= SDVO_ENABLE; 1964 if (pipe_config->has_audio) 1965 temp |= HDMI_AUDIO_ENABLE; 1966 1967 /* 1968 * HW workaround, need to write this twice for issue 1969 * that may result in first write getting masked. 1970 */ 1971 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1972 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1973 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1974 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1975 1976 /* 1977 * HW workaround, need to toggle enable bit off and on 1978 * for 12bpc with pixel repeat. 1979 * 1980 * FIXME: BSpec says this should be done at the end of 1981 * of the modeset sequence, so not sure if this isn't too soon. 1982 */ 1983 if (pipe_config->pipe_bpp > 24 && 1984 pipe_config->pixel_multiplier > 1) { 1985 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 1986 temp & ~SDVO_ENABLE); 1987 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1988 1989 /* 1990 * HW workaround, need to write this twice for issue 1991 * that may result in first write getting masked. 1992 */ 1993 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1994 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1995 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1996 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1997 } 1998 1999 if (pipe_config->has_audio) 2000 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2001} 2002 2003static void cpt_enable_hdmi(struct intel_atomic_state *state, 2004 struct intel_encoder *encoder, 2005 const struct intel_crtc_state *pipe_config, 2006 const struct drm_connector_state *conn_state) 2007{ 2008 struct drm_device *dev = encoder->base.dev; 2009 struct drm_i915_private *dev_priv = to_i915(dev); 2010 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2011 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2012 enum pipe pipe = crtc->pipe; 2013 u32 temp; 2014 2015 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2016 2017 temp |= SDVO_ENABLE; 2018 if (pipe_config->has_audio) 2019 temp |= HDMI_AUDIO_ENABLE; 2020 2021 /* 2022 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 2023 * 2024 * The procedure for 12bpc is as follows: 2025 * 1. disable HDMI clock gating 2026 * 2. enable HDMI with 8bpc 2027 * 3. enable HDMI with 12bpc 2028 * 4. enable HDMI clock gating 2029 */ 2030 2031 if (pipe_config->pipe_bpp > 24) { 2032 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2033 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2034 2035 temp &= ~SDVO_COLOR_FORMAT_MASK; 2036 temp |= SDVO_COLOR_FORMAT_8bpc; 2037 } 2038 2039 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2040 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2041 2042 if (pipe_config->pipe_bpp > 24) { 2043 temp &= ~SDVO_COLOR_FORMAT_MASK; 2044 temp |= HDMI_COLOR_FORMAT_12bpc; 2045 2046 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2047 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2048 2049 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2050 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2051 } 2052 2053 if (pipe_config->has_audio) 2054 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2055} 2056 2057static void vlv_enable_hdmi(struct intel_atomic_state *state, 2058 struct intel_encoder *encoder, 2059 const struct intel_crtc_state *pipe_config, 2060 const struct drm_connector_state *conn_state) 2061{ 2062} 2063 2064static void intel_disable_hdmi(struct intel_atomic_state *state, 2065 struct intel_encoder *encoder, 2066 const struct intel_crtc_state *old_crtc_state, 2067 const struct drm_connector_state *old_conn_state) 2068{ 2069 struct drm_device *dev = encoder->base.dev; 2070 struct drm_i915_private *dev_priv = to_i915(dev); 2071 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2072 struct intel_digital_port *dig_port = 2073 hdmi_to_dig_port(intel_hdmi); 2074 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2075 u32 temp; 2076 2077 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2078 2079 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2080 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2081 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2082 2083 /* 2084 * HW workaround for IBX, we need to move the port 2085 * to transcoder A after disabling it to allow the 2086 * matching DP port to be enabled on transcoder A. 2087 */ 2088 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2089 /* 2090 * We get CPU/PCH FIFO underruns on the other pipe when 2091 * doing the workaround. Sweep them under the rug. 2092 */ 2093 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2094 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2095 2096 temp &= ~SDVO_PIPE_SEL_MASK; 2097 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2098 /* 2099 * HW workaround, need to write this twice for issue 2100 * that may result in first write getting masked. 2101 */ 2102 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2103 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2104 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2105 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2106 2107 temp &= ~SDVO_ENABLE; 2108 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2109 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2110 2111 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2112 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2113 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2114 } 2115 2116 dig_port->set_infoframes(encoder, 2117 false, 2118 old_crtc_state, old_conn_state); 2119 2120 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2121} 2122 2123static void g4x_disable_hdmi(struct intel_atomic_state *state, 2124 struct intel_encoder *encoder, 2125 const struct intel_crtc_state *old_crtc_state, 2126 const struct drm_connector_state *old_conn_state) 2127{ 2128 if (old_crtc_state->has_audio) 2129 intel_audio_codec_disable(encoder, 2130 old_crtc_state, old_conn_state); 2131 2132 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 2133} 2134 2135static void pch_disable_hdmi(struct intel_atomic_state *state, 2136 struct intel_encoder *encoder, 2137 const struct intel_crtc_state *old_crtc_state, 2138 const struct drm_connector_state *old_conn_state) 2139{ 2140 if (old_crtc_state->has_audio) 2141 intel_audio_codec_disable(encoder, 2142 old_crtc_state, old_conn_state); 2143} 2144 2145static void pch_post_disable_hdmi(struct intel_atomic_state *state, 2146 struct intel_encoder *encoder, 2147 const struct intel_crtc_state *old_crtc_state, 2148 const struct drm_connector_state *old_conn_state) 2149{ 2150 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 2151} 2152 2153static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2154{ 2155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2156 int max_tmds_clock, vbt_max_tmds_clock; 2157 2158 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2159 max_tmds_clock = 594000; 2160 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2161 max_tmds_clock = 300000; 2162 else if (INTEL_GEN(dev_priv) >= 5) 2163 max_tmds_clock = 225000; 2164 else 2165 max_tmds_clock = 165000; 2166 2167 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 2168 if (vbt_max_tmds_clock) 2169 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 2170 2171 return max_tmds_clock; 2172} 2173 2174static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 2175 const struct drm_connector_state *conn_state) 2176{ 2177 return hdmi->has_hdmi_sink && 2178 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 2179} 2180 2181static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2182 bool respect_downstream_limits, 2183 bool has_hdmi_sink) 2184{ 2185 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2186 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2187 2188 if (respect_downstream_limits) { 2189 struct intel_connector *connector = hdmi->attached_connector; 2190 const struct drm_display_info *info = &connector->base.display_info; 2191 2192 if (hdmi->dp_dual_mode.max_tmds_clock) 2193 max_tmds_clock = min(max_tmds_clock, 2194 hdmi->dp_dual_mode.max_tmds_clock); 2195 2196 if (info->max_tmds_clock) 2197 max_tmds_clock = min(max_tmds_clock, 2198 info->max_tmds_clock); 2199 else if (!has_hdmi_sink) 2200 max_tmds_clock = min(max_tmds_clock, 165000); 2201 } 2202 2203 return max_tmds_clock; 2204} 2205 2206static enum drm_mode_status 2207hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2208 int clock, bool respect_downstream_limits, 2209 bool has_hdmi_sink) 2210{ 2211 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2212 2213 if (clock < 25000) 2214 return MODE_CLOCK_LOW; 2215 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 2216 has_hdmi_sink)) 2217 return MODE_CLOCK_HIGH; 2218 2219 /* GLK DPLL can't generate 446-480 MHz */ 2220 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 2221 return MODE_CLOCK_RANGE; 2222 2223 /* BXT/GLK DPLL can't generate 223-240 MHz */ 2224 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2225 return MODE_CLOCK_RANGE; 2226 2227 /* CHV DPLL can't generate 216-240 MHz */ 2228 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2229 return MODE_CLOCK_RANGE; 2230 2231 return MODE_OK; 2232} 2233 2234static enum drm_mode_status 2235intel_hdmi_mode_valid(struct drm_connector *connector, 2236 struct drm_display_mode *mode) 2237{ 2238 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2239 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2240 struct drm_i915_private *dev_priv = to_i915(dev); 2241 enum drm_mode_status status; 2242 int clock = mode->clock; 2243 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2244 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2245 2246 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2247 return MODE_NO_DBLESCAN; 2248 2249 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2250 clock *= 2; 2251 2252 if (clock > max_dotclk) 2253 return MODE_CLOCK_HIGH; 2254 2255 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2256 if (!has_hdmi_sink) 2257 return MODE_CLOCK_LOW; 2258 clock *= 2; 2259 } 2260 2261 if (drm_mode_is_420_only(&connector->display_info, mode)) 2262 clock /= 2; 2263 2264 /* check if we can do 8bpc */ 2265 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); 2266 2267 if (has_hdmi_sink) { 2268 /* if we can't do 8bpc we may still be able to do 12bpc */ 2269 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2270 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2271 true, has_hdmi_sink); 2272 2273 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2274 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2275 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2276 true, has_hdmi_sink); 2277 } 2278 if (status != MODE_OK) 2279 return status; 2280 2281 return intel_mode_valid_max_plane_size(dev_priv, mode); 2282} 2283 2284bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2285 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 2286{ 2287 struct drm_atomic_state *state = crtc_state->uapi.state; 2288 struct drm_connector_state *connector_state; 2289 struct drm_connector *connector; 2290 int i; 2291 2292 if (crtc_state->pipe_bpp < bpc * 3) 2293 return false; 2294 2295 if (!has_hdmi_sink) 2296 return false; 2297 2298 for_each_new_connector_in_state(state, connector, connector_state, i) { 2299 const struct drm_display_info *info = &connector->display_info; 2300 2301 if (connector_state->crtc != crtc_state->uapi.crtc) 2302 continue; 2303 2304 if (ycbcr420_output) { 2305 const struct drm_hdmi_info *hdmi = &info->hdmi; 2306 2307 if (bpc == 12 && !(hdmi->y420_dc_modes & 2308 DRM_EDID_YCBCR420_DC_36)) 2309 return false; 2310 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2311 DRM_EDID_YCBCR420_DC_30)) 2312 return false; 2313 } else { 2314 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2315 DRM_EDID_HDMI_DC_36)) 2316 return false; 2317 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2318 DRM_EDID_HDMI_DC_30)) 2319 return false; 2320 } 2321 } 2322 2323 return true; 2324} 2325 2326static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2327 int bpc) 2328{ 2329 struct drm_i915_private *dev_priv = 2330 to_i915(crtc_state->uapi.crtc->dev); 2331 const struct drm_display_mode *adjusted_mode = 2332 &crtc_state->hw.adjusted_mode; 2333 2334 if (HAS_GMCH(dev_priv)) 2335 return false; 2336 2337 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2338 return false; 2339 2340 /* 2341 * HDMI deep color affects the clocks, so it's only possible 2342 * when not cloning with other encoder types. 2343 */ 2344 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) 2345 return false; 2346 2347 /* Display Wa_1405510057:icl,ehl */ 2348 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2349 bpc == 10 && IS_GEN(dev_priv, 11) && 2350 (adjusted_mode->crtc_hblank_end - 2351 adjusted_mode->crtc_hblank_start) % 8 == 2) 2352 return false; 2353 2354 return intel_hdmi_deep_color_possible(crtc_state, bpc, 2355 crtc_state->has_hdmi_sink, 2356 crtc_state->output_format == 2357 INTEL_OUTPUT_FORMAT_YCBCR420); 2358} 2359 2360static int 2361intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state, 2362 const struct drm_connector_state *conn_state) 2363{ 2364 struct drm_connector *connector = conn_state->connector; 2365 struct drm_i915_private *i915 = to_i915(connector->dev); 2366 const struct drm_display_mode *adjusted_mode = 2367 &crtc_state->hw.adjusted_mode; 2368 2369 if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode)) 2370 return 0; 2371 2372 if (!connector->ycbcr_420_allowed) { 2373 drm_err(&i915->drm, 2374 "Platform doesn't support YCBCR420 output\n"); 2375 return -EINVAL; 2376 } 2377 2378 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2379 2380 return intel_pch_panel_fitting(crtc_state, conn_state); 2381} 2382 2383static int intel_hdmi_port_clock(int clock, int bpc) 2384{ 2385 /* 2386 * Need to adjust the port link by: 2387 * 1.5x for 12bpc 2388 * 1.25x for 10bpc 2389 */ 2390 return clock * bpc / 8; 2391} 2392 2393static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2394 struct intel_crtc_state *crtc_state, 2395 int clock) 2396{ 2397 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2398 int bpc; 2399 2400 for (bpc = 12; bpc >= 10; bpc -= 2) { 2401 if (hdmi_deep_color_possible(crtc_state, bpc) && 2402 hdmi_port_clock_valid(intel_hdmi, 2403 intel_hdmi_port_clock(clock, bpc), 2404 true, crtc_state->has_hdmi_sink) == MODE_OK) 2405 return bpc; 2406 } 2407 2408 return 8; 2409} 2410 2411static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2412 struct intel_crtc_state *crtc_state) 2413{ 2414 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2415 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2416 const struct drm_display_mode *adjusted_mode = 2417 &crtc_state->hw.adjusted_mode; 2418 int bpc, clock = adjusted_mode->crtc_clock; 2419 2420 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2421 clock *= 2; 2422 2423 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2424 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2425 clock /= 2; 2426 2427 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2428 2429 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2430 2431 /* 2432 * pipe_bpp could already be below 8bpc due to 2433 * FDI bandwidth constraints. We shouldn't bump it 2434 * back up to 8bpc in that case. 2435 */ 2436 if (crtc_state->pipe_bpp > bpc * 3) 2437 crtc_state->pipe_bpp = bpc * 3; 2438 2439 drm_dbg_kms(&i915->drm, 2440 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2441 bpc, crtc_state->pipe_bpp); 2442 2443 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2444 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2445 drm_dbg_kms(&i915->drm, 2446 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2447 crtc_state->port_clock); 2448 return -EINVAL; 2449 } 2450 2451 return 0; 2452} 2453 2454bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2455 const struct drm_connector_state *conn_state) 2456{ 2457 const struct intel_digital_connector_state *intel_conn_state = 2458 to_intel_digital_connector_state(conn_state); 2459 const struct drm_display_mode *adjusted_mode = 2460 &crtc_state->hw.adjusted_mode; 2461 2462 /* 2463 * Our YCbCr output is always limited range. 2464 * crtc_state->limited_color_range only applies to RGB, 2465 * and it must never be set for YCbCr or we risk setting 2466 * some conflicting bits in PIPECONF which will mess up 2467 * the colors on the monitor. 2468 */ 2469 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2470 return false; 2471 2472 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2473 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2474 return crtc_state->has_hdmi_sink && 2475 drm_default_rgb_quant_range(adjusted_mode) == 2476 HDMI_QUANTIZATION_RANGE_LIMITED; 2477 } else { 2478 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2479 } 2480} 2481 2482static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2483 const struct intel_crtc_state *crtc_state, 2484 const struct drm_connector_state *conn_state) 2485{ 2486 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2487 const struct intel_digital_connector_state *intel_conn_state = 2488 to_intel_digital_connector_state(conn_state); 2489 2490 if (!crtc_state->has_hdmi_sink) 2491 return false; 2492 2493 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2494 return intel_hdmi->has_audio; 2495 else 2496 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2497} 2498 2499int intel_hdmi_compute_config(struct intel_encoder *encoder, 2500 struct intel_crtc_state *pipe_config, 2501 struct drm_connector_state *conn_state) 2502{ 2503 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2505 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2506 struct drm_connector *connector = conn_state->connector; 2507 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2508 int ret; 2509 2510 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2511 return -EINVAL; 2512 2513 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2514 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2515 conn_state); 2516 2517 if (pipe_config->has_hdmi_sink) 2518 pipe_config->has_infoframe = true; 2519 2520 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2521 pipe_config->pixel_multiplier = 2; 2522 2523 ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state); 2524 if (ret) 2525 return ret; 2526 2527 pipe_config->limited_color_range = 2528 intel_hdmi_limited_color_range(pipe_config, conn_state); 2529 2530 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2531 pipe_config->has_pch_encoder = true; 2532 2533 pipe_config->has_audio = 2534 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2535 2536 ret = intel_hdmi_compute_clock(encoder, pipe_config); 2537 if (ret) 2538 return ret; 2539 2540 if (conn_state->picture_aspect_ratio) 2541 adjusted_mode->picture_aspect_ratio = 2542 conn_state->picture_aspect_ratio; 2543 2544 pipe_config->lane_count = 4; 2545 2546 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2547 IS_GEMINILAKE(dev_priv))) { 2548 if (scdc->scrambling.low_rates) 2549 pipe_config->hdmi_scrambling = true; 2550 2551 if (pipe_config->port_clock > 340000) { 2552 pipe_config->hdmi_scrambling = true; 2553 pipe_config->hdmi_high_tmds_clock_ratio = true; 2554 } 2555 } 2556 2557 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2558 conn_state); 2559 2560 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2561 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2562 return -EINVAL; 2563 } 2564 2565 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2566 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2567 return -EINVAL; 2568 } 2569 2570 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2571 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2572 return -EINVAL; 2573 } 2574 2575 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2576 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2577 return -EINVAL; 2578 } 2579 2580 return 0; 2581} 2582 2583static void 2584intel_hdmi_unset_edid(struct drm_connector *connector) 2585{ 2586 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2587 2588 intel_hdmi->has_hdmi_sink = false; 2589 intel_hdmi->has_audio = false; 2590 2591 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2592 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2593 2594 kfree(to_intel_connector(connector)->detect_edid); 2595 to_intel_connector(connector)->detect_edid = NULL; 2596} 2597 2598static void 2599intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2600{ 2601 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2602 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2603 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2604 struct i2c_adapter *adapter = 2605 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2606 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2607 2608 /* 2609 * Type 1 DVI adaptors are not required to implement any 2610 * registers, so we can't always detect their presence. 2611 * Ideally we should be able to check the state of the 2612 * CONFIG1 pin, but no such luck on our hardware. 2613 * 2614 * The only method left to us is to check the VBT to see 2615 * if the port is a dual mode capable DP port. But let's 2616 * only do that when we sucesfully read the EDID, to avoid 2617 * confusing log messages about DP dual mode adaptors when 2618 * there's nothing connected to the port. 2619 */ 2620 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2621 /* An overridden EDID imply that we want this port for testing. 2622 * Make sure not to set limits for that port. 2623 */ 2624 if (has_edid && !connector->override_edid && 2625 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2626 drm_dbg_kms(&dev_priv->drm, 2627 "Assuming DP dual mode adaptor presence based on VBT\n"); 2628 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2629 } else { 2630 type = DRM_DP_DUAL_MODE_NONE; 2631 } 2632 } 2633 2634 if (type == DRM_DP_DUAL_MODE_NONE) 2635 return; 2636 2637 hdmi->dp_dual_mode.type = type; 2638 hdmi->dp_dual_mode.max_tmds_clock = 2639 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2640 2641 drm_dbg_kms(&dev_priv->drm, 2642 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2643 drm_dp_get_dual_mode_type_name(type), 2644 hdmi->dp_dual_mode.max_tmds_clock); 2645} 2646 2647static bool 2648intel_hdmi_set_edid(struct drm_connector *connector) 2649{ 2650 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2651 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2652 intel_wakeref_t wakeref; 2653 struct edid *edid; 2654 bool connected = false; 2655 struct i2c_adapter *i2c; 2656 2657 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2658 2659 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2660 2661 edid = drm_get_edid(connector, i2c); 2662 2663 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2664 drm_dbg_kms(&dev_priv->drm, 2665 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2666 intel_gmbus_force_bit(i2c, true); 2667 edid = drm_get_edid(connector, i2c); 2668 intel_gmbus_force_bit(i2c, false); 2669 } 2670 2671 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2672 2673 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2674 2675 to_intel_connector(connector)->detect_edid = edid; 2676 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2677 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2678 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2679 2680 connected = true; 2681 } 2682 2683 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2684 2685 return connected; 2686} 2687 2688static enum drm_connector_status 2689intel_hdmi_detect(struct drm_connector *connector, bool force) 2690{ 2691 enum drm_connector_status status = connector_status_disconnected; 2692 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2693 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2694 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2695 intel_wakeref_t wakeref; 2696 2697 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2698 connector->base.id, connector->name); 2699 2700 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2701 return connector_status_disconnected; 2702 2703 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2704 2705 if (INTEL_GEN(dev_priv) >= 11 && 2706 !intel_digital_port_connected(encoder)) 2707 goto out; 2708 2709 intel_hdmi_unset_edid(connector); 2710 2711 if (intel_hdmi_set_edid(connector)) 2712 status = connector_status_connected; 2713 2714out: 2715 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2716 2717 if (status != connector_status_connected) 2718 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2719 2720 /* 2721 * Make sure the refs for power wells enabled during detect are 2722 * dropped to avoid a new detect cycle triggered by HPD polling. 2723 */ 2724 intel_display_power_flush_work(dev_priv); 2725 2726 return status; 2727} 2728 2729static void 2730intel_hdmi_force(struct drm_connector *connector) 2731{ 2732 struct drm_i915_private *i915 = to_i915(connector->dev); 2733 2734 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2735 connector->base.id, connector->name); 2736 2737 intel_hdmi_unset_edid(connector); 2738 2739 if (connector->status != connector_status_connected) 2740 return; 2741 2742 intel_hdmi_set_edid(connector); 2743} 2744 2745static int intel_hdmi_get_modes(struct drm_connector *connector) 2746{ 2747 struct edid *edid; 2748 2749 edid = to_intel_connector(connector)->detect_edid; 2750 if (edid == NULL) 2751 return 0; 2752 2753 return intel_connector_update_modes(connector, edid); 2754} 2755 2756static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 2757 struct intel_encoder *encoder, 2758 const struct intel_crtc_state *pipe_config, 2759 const struct drm_connector_state *conn_state) 2760{ 2761 struct intel_digital_port *dig_port = 2762 enc_to_dig_port(encoder); 2763 2764 intel_hdmi_prepare(encoder, pipe_config); 2765 2766 dig_port->set_infoframes(encoder, 2767 pipe_config->has_infoframe, 2768 pipe_config, conn_state); 2769} 2770 2771static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 2772 struct intel_encoder *encoder, 2773 const struct intel_crtc_state *pipe_config, 2774 const struct drm_connector_state *conn_state) 2775{ 2776 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2777 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2778 2779 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2780 2781 /* HDMI 1.0V-2dB */ 2782 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 2783 0x2b247878); 2784 2785 dig_port->set_infoframes(encoder, 2786 pipe_config->has_infoframe, 2787 pipe_config, conn_state); 2788 2789 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 2790 2791 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 2792} 2793 2794static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 2795 struct intel_encoder *encoder, 2796 const struct intel_crtc_state *pipe_config, 2797 const struct drm_connector_state *conn_state) 2798{ 2799 intel_hdmi_prepare(encoder, pipe_config); 2800 2801 vlv_phy_pre_pll_enable(encoder, pipe_config); 2802} 2803 2804static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 2805 struct intel_encoder *encoder, 2806 const struct intel_crtc_state *pipe_config, 2807 const struct drm_connector_state *conn_state) 2808{ 2809 intel_hdmi_prepare(encoder, pipe_config); 2810 2811 chv_phy_pre_pll_enable(encoder, pipe_config); 2812} 2813 2814static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 2815 struct intel_encoder *encoder, 2816 const struct intel_crtc_state *old_crtc_state, 2817 const struct drm_connector_state *old_conn_state) 2818{ 2819 chv_phy_post_pll_disable(encoder, old_crtc_state); 2820} 2821 2822static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 2823 struct intel_encoder *encoder, 2824 const struct intel_crtc_state *old_crtc_state, 2825 const struct drm_connector_state *old_conn_state) 2826{ 2827 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2828 vlv_phy_reset_lanes(encoder, old_crtc_state); 2829} 2830 2831static void chv_hdmi_post_disable(struct intel_atomic_state *state, 2832 struct intel_encoder *encoder, 2833 const struct intel_crtc_state *old_crtc_state, 2834 const struct drm_connector_state *old_conn_state) 2835{ 2836 struct drm_device *dev = encoder->base.dev; 2837 struct drm_i915_private *dev_priv = to_i915(dev); 2838 2839 vlv_dpio_get(dev_priv); 2840 2841 /* Assert data lane reset */ 2842 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2843 2844 vlv_dpio_put(dev_priv); 2845} 2846 2847static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 2848 struct intel_encoder *encoder, 2849 const struct intel_crtc_state *pipe_config, 2850 const struct drm_connector_state *conn_state) 2851{ 2852 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2853 struct drm_device *dev = encoder->base.dev; 2854 struct drm_i915_private *dev_priv = to_i915(dev); 2855 2856 chv_phy_pre_encoder_enable(encoder, pipe_config); 2857 2858 /* FIXME: Program the support xxx V-dB */ 2859 /* Use 800mV-0dB */ 2860 chv_set_phy_signal_level(encoder, 128, 102, false); 2861 2862 dig_port->set_infoframes(encoder, 2863 pipe_config->has_infoframe, 2864 pipe_config, conn_state); 2865 2866 g4x_enable_hdmi(state, encoder, pipe_config, conn_state); 2867 2868 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 2869 2870 /* Second common lane will stay alive on its own now */ 2871 chv_phy_release_cl2_override(encoder); 2872} 2873 2874static struct i2c_adapter * 2875intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2876{ 2877 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2878 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2879 2880 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2881} 2882 2883static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2884{ 2885 struct drm_i915_private *i915 = to_i915(connector->dev); 2886 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2887 struct kobject *i2c_kobj = &adapter->dev.kobj; 2888 struct kobject *connector_kobj = &connector->kdev->kobj; 2889 int ret; 2890 2891 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2892 if (ret) 2893 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2894} 2895 2896static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2897{ 2898 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2899 struct kobject *i2c_kobj = &adapter->dev.kobj; 2900 struct kobject *connector_kobj = &connector->kdev->kobj; 2901 2902 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2903} 2904 2905static int 2906intel_hdmi_connector_register(struct drm_connector *connector) 2907{ 2908 int ret; 2909 2910 ret = intel_connector_register(connector); 2911 if (ret) 2912 return ret; 2913 2914 intel_hdmi_create_i2c_symlink(connector); 2915 2916 return ret; 2917} 2918 2919static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2920{ 2921 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2922 2923 cec_notifier_conn_unregister(n); 2924 2925 intel_hdmi_remove_i2c_symlink(connector); 2926 intel_connector_unregister(connector); 2927} 2928 2929static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2930 .detect = intel_hdmi_detect, 2931 .force = intel_hdmi_force, 2932 .fill_modes = drm_helper_probe_single_connector_modes, 2933 .atomic_get_property = intel_digital_connector_atomic_get_property, 2934 .atomic_set_property = intel_digital_connector_atomic_set_property, 2935 .late_register = intel_hdmi_connector_register, 2936 .early_unregister = intel_hdmi_connector_unregister, 2937 .destroy = intel_connector_destroy, 2938 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2939 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2940}; 2941 2942static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2943 .get_modes = intel_hdmi_get_modes, 2944 .mode_valid = intel_hdmi_mode_valid, 2945 .atomic_check = intel_digital_connector_atomic_check, 2946}; 2947 2948static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2949 .destroy = intel_encoder_destroy, 2950}; 2951 2952static void 2953intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2954{ 2955 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2956 struct intel_digital_port *dig_port = 2957 hdmi_to_dig_port(intel_hdmi); 2958 2959 intel_attach_force_audio_property(connector); 2960 intel_attach_broadcast_rgb_property(connector); 2961 intel_attach_aspect_ratio_property(connector); 2962 2963 /* 2964 * Attach Colorspace property for Non LSPCON based device 2965 * ToDo: This needs to be extended for LSPCON implementation 2966 * as well. Will be implemented separately. 2967 */ 2968 if (!dig_port->lspcon.active) 2969 intel_attach_colorspace_property(connector); 2970 2971 drm_connector_attach_content_type_property(connector); 2972 2973 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2974 drm_object_attach_property(&connector->base, 2975 connector->dev->mode_config.hdr_output_metadata_property, 0); 2976 2977 if (!HAS_GMCH(dev_priv)) 2978 drm_connector_attach_max_bpc_property(connector, 8, 12); 2979} 2980 2981/* 2982 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2983 * @encoder: intel_encoder 2984 * @connector: drm_connector 2985 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2986 * or reset the high tmds clock ratio for scrambling 2987 * @scrambling: bool to Indicate if the function needs to set or reset 2988 * sink scrambling 2989 * 2990 * This function handles scrambling on HDMI 2.0 capable sinks. 2991 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2992 * it enables scrambling. This should be called before enabling the HDMI 2993 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2994 * detect a scrambled clock within 100 ms. 2995 * 2996 * Returns: 2997 * True on success, false on failure. 2998 */ 2999bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 3000 struct drm_connector *connector, 3001 bool high_tmds_clock_ratio, 3002 bool scrambling) 3003{ 3004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3005 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 3006 struct drm_scrambling *sink_scrambling = 3007 &connector->display_info.hdmi.scdc.scrambling; 3008 struct i2c_adapter *adapter = 3009 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3010 3011 if (!sink_scrambling->supported) 3012 return true; 3013 3014 drm_dbg_kms(&dev_priv->drm, 3015 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 3016 connector->base.id, connector->name, 3017 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 3018 3019 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 3020 return drm_scdc_set_high_tmds_clock_ratio(adapter, 3021 high_tmds_clock_ratio) && 3022 drm_scdc_set_scrambling(adapter, scrambling); 3023} 3024 3025static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3026{ 3027 u8 ddc_pin; 3028 3029 switch (port) { 3030 case PORT_B: 3031 ddc_pin = GMBUS_PIN_DPB; 3032 break; 3033 case PORT_C: 3034 ddc_pin = GMBUS_PIN_DPC; 3035 break; 3036 case PORT_D: 3037 ddc_pin = GMBUS_PIN_DPD_CHV; 3038 break; 3039 default: 3040 MISSING_CASE(port); 3041 ddc_pin = GMBUS_PIN_DPB; 3042 break; 3043 } 3044 return ddc_pin; 3045} 3046 3047static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3048{ 3049 u8 ddc_pin; 3050 3051 switch (port) { 3052 case PORT_B: 3053 ddc_pin = GMBUS_PIN_1_BXT; 3054 break; 3055 case PORT_C: 3056 ddc_pin = GMBUS_PIN_2_BXT; 3057 break; 3058 default: 3059 MISSING_CASE(port); 3060 ddc_pin = GMBUS_PIN_1_BXT; 3061 break; 3062 } 3063 return ddc_pin; 3064} 3065 3066static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3067 enum port port) 3068{ 3069 u8 ddc_pin; 3070 3071 switch (port) { 3072 case PORT_B: 3073 ddc_pin = GMBUS_PIN_1_BXT; 3074 break; 3075 case PORT_C: 3076 ddc_pin = GMBUS_PIN_2_BXT; 3077 break; 3078 case PORT_D: 3079 ddc_pin = GMBUS_PIN_4_CNP; 3080 break; 3081 case PORT_F: 3082 ddc_pin = GMBUS_PIN_3_BXT; 3083 break; 3084 default: 3085 MISSING_CASE(port); 3086 ddc_pin = GMBUS_PIN_1_BXT; 3087 break; 3088 } 3089 return ddc_pin; 3090} 3091 3092static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3093{ 3094 enum phy phy = intel_port_to_phy(dev_priv, port); 3095 3096 if (intel_phy_is_combo(dev_priv, phy)) 3097 return GMBUS_PIN_1_BXT + port; 3098 else if (intel_phy_is_tc(dev_priv, phy)) 3099 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 3100 3101 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 3102 return GMBUS_PIN_2_BXT; 3103} 3104 3105static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3106{ 3107 enum phy phy = intel_port_to_phy(dev_priv, port); 3108 u8 ddc_pin; 3109 3110 switch (phy) { 3111 case PHY_A: 3112 ddc_pin = GMBUS_PIN_1_BXT; 3113 break; 3114 case PHY_B: 3115 ddc_pin = GMBUS_PIN_2_BXT; 3116 break; 3117 case PHY_C: 3118 ddc_pin = GMBUS_PIN_9_TC1_ICP; 3119 break; 3120 default: 3121 MISSING_CASE(phy); 3122 ddc_pin = GMBUS_PIN_1_BXT; 3123 break; 3124 } 3125 return ddc_pin; 3126} 3127 3128static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3129{ 3130 enum phy phy = intel_port_to_phy(dev_priv, port); 3131 3132 WARN_ON(port == PORT_C); 3133 3134 /* 3135 * Pin mapping for RKL depends on which PCH is present. With TGP, the 3136 * final two outputs use type-c pins, even though they're actually 3137 * combo outputs. With CMP, the traditional DDI A-D pins are used for 3138 * all outputs. 3139 */ 3140 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 3141 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 3142 3143 return GMBUS_PIN_1_BXT + phy; 3144} 3145 3146static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3147 enum port port) 3148{ 3149 u8 ddc_pin; 3150 3151 switch (port) { 3152 case PORT_B: 3153 ddc_pin = GMBUS_PIN_DPB; 3154 break; 3155 case PORT_C: 3156 ddc_pin = GMBUS_PIN_DPC; 3157 break; 3158 case PORT_D: 3159 ddc_pin = GMBUS_PIN_DPD; 3160 break; 3161 default: 3162 MISSING_CASE(port); 3163 ddc_pin = GMBUS_PIN_DPB; 3164 break; 3165 } 3166 return ddc_pin; 3167} 3168 3169static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 3170{ 3171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3172 enum port port = encoder->port; 3173 u8 ddc_pin; 3174 3175 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 3176 if (ddc_pin) { 3177 drm_dbg_kms(&dev_priv->drm, 3178 "Using DDC pin 0x%x for port %c (VBT)\n", 3179 ddc_pin, port_name(port)); 3180 return ddc_pin; 3181 } 3182 3183 if (IS_ROCKETLAKE(dev_priv)) 3184 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 3185 else if (HAS_PCH_MCC(dev_priv)) 3186 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3187 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3188 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3189 else if (HAS_PCH_CNP(dev_priv)) 3190 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3191 else if (IS_GEN9_LP(dev_priv)) 3192 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3193 else if (IS_CHERRYVIEW(dev_priv)) 3194 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3195 else 3196 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3197 3198 drm_dbg_kms(&dev_priv->drm, 3199 "Using DDC pin 0x%x for port %c (platform default)\n", 3200 ddc_pin, port_name(port)); 3201 3202 return ddc_pin; 3203} 3204 3205void intel_infoframe_init(struct intel_digital_port *dig_port) 3206{ 3207 struct drm_i915_private *dev_priv = 3208 to_i915(dig_port->base.base.dev); 3209 3210 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3211 dig_port->write_infoframe = vlv_write_infoframe; 3212 dig_port->read_infoframe = vlv_read_infoframe; 3213 dig_port->set_infoframes = vlv_set_infoframes; 3214 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3215 } else if (IS_G4X(dev_priv)) { 3216 dig_port->write_infoframe = g4x_write_infoframe; 3217 dig_port->read_infoframe = g4x_read_infoframe; 3218 dig_port->set_infoframes = g4x_set_infoframes; 3219 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3220 } else if (HAS_DDI(dev_priv)) { 3221 if (dig_port->lspcon.active) { 3222 dig_port->write_infoframe = lspcon_write_infoframe; 3223 dig_port->read_infoframe = lspcon_read_infoframe; 3224 dig_port->set_infoframes = lspcon_set_infoframes; 3225 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3226 } else { 3227 dig_port->write_infoframe = hsw_write_infoframe; 3228 dig_port->read_infoframe = hsw_read_infoframe; 3229 dig_port->set_infoframes = hsw_set_infoframes; 3230 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3231 } 3232 } else if (HAS_PCH_IBX(dev_priv)) { 3233 dig_port->write_infoframe = ibx_write_infoframe; 3234 dig_port->read_infoframe = ibx_read_infoframe; 3235 dig_port->set_infoframes = ibx_set_infoframes; 3236 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3237 } else { 3238 dig_port->write_infoframe = cpt_write_infoframe; 3239 dig_port->read_infoframe = cpt_read_infoframe; 3240 dig_port->set_infoframes = cpt_set_infoframes; 3241 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3242 } 3243} 3244 3245void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3246 struct intel_connector *intel_connector) 3247{ 3248 struct drm_connector *connector = &intel_connector->base; 3249 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3250 struct intel_encoder *intel_encoder = &dig_port->base; 3251 struct drm_device *dev = intel_encoder->base.dev; 3252 struct drm_i915_private *dev_priv = to_i915(dev); 3253 struct i2c_adapter *ddc; 3254 enum port port = intel_encoder->port; 3255 struct cec_connector_info conn_info; 3256 3257 drm_dbg_kms(&dev_priv->drm, 3258 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3259 intel_encoder->base.base.id, intel_encoder->base.name); 3260 3261 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3262 return; 3263 3264 if (drm_WARN(dev, dig_port->max_lanes < 4, 3265 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3266 dig_port->max_lanes, intel_encoder->base.base.id, 3267 intel_encoder->base.name)) 3268 return; 3269 3270 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 3271 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3272 3273 drm_connector_init_with_ddc(dev, connector, 3274 &intel_hdmi_connector_funcs, 3275 DRM_MODE_CONNECTOR_HDMIA, 3276 ddc); 3277 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3278 3279 connector->interlace_allowed = 1; 3280 connector->doublescan_allowed = 0; 3281 connector->stereo_allowed = 1; 3282 3283 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3284 connector->ycbcr_420_allowed = true; 3285 3286 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3287 3288 if (HAS_DDI(dev_priv)) 3289 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3290 else 3291 intel_connector->get_hw_state = intel_connector_get_hw_state; 3292 3293 intel_hdmi_add_properties(intel_hdmi, connector); 3294 3295 intel_connector_attach_encoder(intel_connector, intel_encoder); 3296 intel_hdmi->attached_connector = intel_connector; 3297 3298 if (is_hdcp_supported(dev_priv, port)) { 3299 int ret = intel_hdcp_init(intel_connector, port, 3300 &intel_hdmi_hdcp_shim); 3301 if (ret) 3302 drm_dbg_kms(&dev_priv->drm, 3303 "HDCP init failed, skipping.\n"); 3304 } 3305 3306 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3307 * 0xd. Failure to do so will result in spurious interrupts being 3308 * generated on the port when a cable is not attached. 3309 */ 3310 if (IS_G45(dev_priv)) { 3311 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 3312 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 3313 (temp & ~0xf) | 0xd); 3314 } 3315 3316 cec_fill_conn_info_from_drm(&conn_info, connector); 3317 3318 intel_hdmi->cec_notifier = 3319 cec_notifier_conn_register(dev->dev, port_identifier(port), 3320 &conn_info); 3321 if (!intel_hdmi->cec_notifier) 3322 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3323} 3324 3325static enum intel_hotplug_state 3326intel_hdmi_hotplug(struct intel_encoder *encoder, 3327 struct intel_connector *connector) 3328{ 3329 enum intel_hotplug_state state; 3330 3331 state = intel_encoder_hotplug(encoder, connector); 3332 3333 /* 3334 * On many platforms the HDMI live state signal is known to be 3335 * unreliable, so we can't use it to detect if a sink is connected or 3336 * not. Instead we detect if it's connected based on whether we can 3337 * read the EDID or not. That in turn has a problem during disconnect, 3338 * since the HPD interrupt may be raised before the DDC lines get 3339 * disconnected (due to how the required length of DDC vs. HPD 3340 * connector pins are specified) and so we'll still be able to get a 3341 * valid EDID. To solve this schedule another detection cycle if this 3342 * time around we didn't detect any change in the sink's connection 3343 * status. 3344 */ 3345 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 3346 state = INTEL_HOTPLUG_RETRY; 3347 3348 return state; 3349} 3350 3351void intel_hdmi_init(struct drm_i915_private *dev_priv, 3352 i915_reg_t hdmi_reg, enum port port) 3353{ 3354 struct intel_digital_port *dig_port; 3355 struct intel_encoder *intel_encoder; 3356 struct intel_connector *intel_connector; 3357 3358 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 3359 if (!dig_port) 3360 return; 3361 3362 intel_connector = intel_connector_alloc(); 3363 if (!intel_connector) { 3364 kfree(dig_port); 3365 return; 3366 } 3367 3368 intel_encoder = &dig_port->base; 3369 3370 mutex_init(&dig_port->hdcp_mutex); 3371 3372 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3373 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3374 "HDMI %c", port_name(port)); 3375 3376 intel_encoder->hotplug = intel_hdmi_hotplug; 3377 intel_encoder->compute_config = intel_hdmi_compute_config; 3378 if (HAS_PCH_SPLIT(dev_priv)) { 3379 intel_encoder->disable = pch_disable_hdmi; 3380 intel_encoder->post_disable = pch_post_disable_hdmi; 3381 } else { 3382 intel_encoder->disable = g4x_disable_hdmi; 3383 } 3384 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3385 intel_encoder->get_config = intel_hdmi_get_config; 3386 if (IS_CHERRYVIEW(dev_priv)) { 3387 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3388 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3389 intel_encoder->enable = vlv_enable_hdmi; 3390 intel_encoder->post_disable = chv_hdmi_post_disable; 3391 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3392 } else if (IS_VALLEYVIEW(dev_priv)) { 3393 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3394 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3395 intel_encoder->enable = vlv_enable_hdmi; 3396 intel_encoder->post_disable = vlv_hdmi_post_disable; 3397 } else { 3398 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3399 if (HAS_PCH_CPT(dev_priv)) 3400 intel_encoder->enable = cpt_enable_hdmi; 3401 else if (HAS_PCH_IBX(dev_priv)) 3402 intel_encoder->enable = ibx_enable_hdmi; 3403 else 3404 intel_encoder->enable = g4x_enable_hdmi; 3405 } 3406 3407 intel_encoder->type = INTEL_OUTPUT_HDMI; 3408 intel_encoder->power_domain = intel_port_to_power_domain(port); 3409 intel_encoder->port = port; 3410 if (IS_CHERRYVIEW(dev_priv)) { 3411 if (port == PORT_D) 3412 intel_encoder->pipe_mask = BIT(PIPE_C); 3413 else 3414 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 3415 } else { 3416 intel_encoder->pipe_mask = ~0; 3417 } 3418 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3419 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3420 /* 3421 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3422 * to work on real hardware. And since g4x can send infoframes to 3423 * only one port anyway, nothing is lost by allowing it. 3424 */ 3425 if (IS_G4X(dev_priv)) 3426 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3427 3428 dig_port->hdmi.hdmi_reg = hdmi_reg; 3429 dig_port->dp.output_reg = INVALID_MMIO_REG; 3430 dig_port->max_lanes = 4; 3431 3432 intel_infoframe_init(dig_port); 3433 3434 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3435 intel_hdmi_init_connector(dig_port, intel_connector); 3436} 3437