1/* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28#include <drm/drm_scdc_helper.h> 29 30#include "i915_drv.h" 31#include "intel_audio.h" 32#include "intel_combo_phy.h" 33#include "intel_connector.h" 34#include "intel_ddi.h" 35#include "intel_display_types.h" 36#include "intel_dp.h" 37#include "intel_dp_mst.h" 38#include "intel_dp_link_training.h" 39#include "intel_dpio_phy.h" 40#include "intel_dsi.h" 41#include "intel_fifo_underrun.h" 42#include "intel_gmbus.h" 43#include "intel_hdcp.h" 44#include "intel_hdmi.h" 45#include "intel_hotplug.h" 46#include "intel_lspcon.h" 47#include "intel_panel.h" 48#include "intel_psr.h" 49#include "intel_sprite.h" 50#include "intel_tc.h" 51#include "intel_vdsc.h" 52 53struct ddi_buf_trans { 54 u32 trans1; /* balance leg enable, de-emph level */ 55 u32 trans2; /* vref sel, vswing */ 56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 57}; 58 59static const u8 index_to_dp_signal_levels[] = { 60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70}; 71 72/* HDMI/DVI modes ignore everything but the last 2 items. So we share 73 * them for both DP and FDI transports, allowing those ports to 74 * automatically adapt to HDMI connections as well 75 */ 76static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 77 { 0x00FFFFFF, 0x0006000E, 0x0 }, 78 { 0x00D75FFF, 0x0005000A, 0x0 }, 79 { 0x00C30FFF, 0x00040006, 0x0 }, 80 { 0x80AAAFFF, 0x000B0000, 0x0 }, 81 { 0x00FFFFFF, 0x0005000A, 0x0 }, 82 { 0x00D75FFF, 0x000C0004, 0x0 }, 83 { 0x80C30FFF, 0x000B0000, 0x0 }, 84 { 0x00FFFFFF, 0x00040006, 0x0 }, 85 { 0x80D75FFF, 0x000B0000, 0x0 }, 86}; 87 88static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 89 { 0x00FFFFFF, 0x0007000E, 0x0 }, 90 { 0x00D75FFF, 0x000F000A, 0x0 }, 91 { 0x00C30FFF, 0x00060006, 0x0 }, 92 { 0x00AAAFFF, 0x001E0000, 0x0 }, 93 { 0x00FFFFFF, 0x000F000A, 0x0 }, 94 { 0x00D75FFF, 0x00160004, 0x0 }, 95 { 0x00C30FFF, 0x001E0000, 0x0 }, 96 { 0x00FFFFFF, 0x00060006, 0x0 }, 97 { 0x00D75FFF, 0x001E0000, 0x0 }, 98}; 99 100static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 101 /* Idx NT mV d T mV d db */ 102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 114}; 115 116static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 117 { 0x00FFFFFF, 0x00000012, 0x0 }, 118 { 0x00EBAFFF, 0x00020011, 0x0 }, 119 { 0x00C71FFF, 0x0006000F, 0x0 }, 120 { 0x00AAAFFF, 0x000E000A, 0x0 }, 121 { 0x00FFFFFF, 0x00020011, 0x0 }, 122 { 0x00DB6FFF, 0x0005000F, 0x0 }, 123 { 0x00BEEFFF, 0x000A000C, 0x0 }, 124 { 0x00FFFFFF, 0x0005000F, 0x0 }, 125 { 0x00DB6FFF, 0x000A000C, 0x0 }, 126}; 127 128static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 129 { 0x00FFFFFF, 0x0007000E, 0x0 }, 130 { 0x00D75FFF, 0x000E000A, 0x0 }, 131 { 0x00BEFFFF, 0x00140006, 0x0 }, 132 { 0x80B2CFFF, 0x001B0002, 0x0 }, 133 { 0x00FFFFFF, 0x000E000A, 0x0 }, 134 { 0x00DB6FFF, 0x00160005, 0x0 }, 135 { 0x80C71FFF, 0x001A0002, 0x0 }, 136 { 0x00F7DFFF, 0x00180004, 0x0 }, 137 { 0x80D75FFF, 0x001B0002, 0x0 }, 138}; 139 140static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 141 { 0x00FFFFFF, 0x0001000E, 0x0 }, 142 { 0x00D75FFF, 0x0004000A, 0x0 }, 143 { 0x00C30FFF, 0x00070006, 0x0 }, 144 { 0x00AAAFFF, 0x000C0000, 0x0 }, 145 { 0x00FFFFFF, 0x0004000A, 0x0 }, 146 { 0x00D75FFF, 0x00090004, 0x0 }, 147 { 0x00C30FFF, 0x000C0000, 0x0 }, 148 { 0x00FFFFFF, 0x00070006, 0x0 }, 149 { 0x00D75FFF, 0x000C0000, 0x0 }, 150}; 151 152static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 153 /* Idx NT mV d T mV df db */ 154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 164}; 165 166/* Skylake H and S */ 167static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 168 { 0x00002016, 0x000000A0, 0x0 }, 169 { 0x00005012, 0x0000009B, 0x0 }, 170 { 0x00007011, 0x00000088, 0x0 }, 171 { 0x80009010, 0x000000C0, 0x1 }, 172 { 0x00002016, 0x0000009B, 0x0 }, 173 { 0x00005012, 0x00000088, 0x0 }, 174 { 0x80007011, 0x000000C0, 0x1 }, 175 { 0x00002016, 0x000000DF, 0x0 }, 176 { 0x80005012, 0x000000C0, 0x1 }, 177}; 178 179/* Skylake U */ 180static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 181 { 0x0000201B, 0x000000A2, 0x0 }, 182 { 0x00005012, 0x00000088, 0x0 }, 183 { 0x80007011, 0x000000CD, 0x1 }, 184 { 0x80009010, 0x000000C0, 0x1 }, 185 { 0x0000201B, 0x0000009D, 0x0 }, 186 { 0x80005012, 0x000000C0, 0x1 }, 187 { 0x80007011, 0x000000C0, 0x1 }, 188 { 0x00002016, 0x00000088, 0x0 }, 189 { 0x80005012, 0x000000C0, 0x1 }, 190}; 191 192/* Skylake Y */ 193static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 194 { 0x00000018, 0x000000A2, 0x0 }, 195 { 0x00005012, 0x00000088, 0x0 }, 196 { 0x80007011, 0x000000CD, 0x3 }, 197 { 0x80009010, 0x000000C0, 0x3 }, 198 { 0x00000018, 0x0000009D, 0x0 }, 199 { 0x80005012, 0x000000C0, 0x3 }, 200 { 0x80007011, 0x000000C0, 0x3 }, 201 { 0x00000018, 0x00000088, 0x0 }, 202 { 0x80005012, 0x000000C0, 0x3 }, 203}; 204 205/* Kabylake H and S */ 206static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { 207 { 0x00002016, 0x000000A0, 0x0 }, 208 { 0x00005012, 0x0000009B, 0x0 }, 209 { 0x00007011, 0x00000088, 0x0 }, 210 { 0x80009010, 0x000000C0, 0x1 }, 211 { 0x00002016, 0x0000009B, 0x0 }, 212 { 0x00005012, 0x00000088, 0x0 }, 213 { 0x80007011, 0x000000C0, 0x1 }, 214 { 0x00002016, 0x00000097, 0x0 }, 215 { 0x80005012, 0x000000C0, 0x1 }, 216}; 217 218/* Kabylake U */ 219static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { 220 { 0x0000201B, 0x000000A1, 0x0 }, 221 { 0x00005012, 0x00000088, 0x0 }, 222 { 0x80007011, 0x000000CD, 0x3 }, 223 { 0x80009010, 0x000000C0, 0x3 }, 224 { 0x0000201B, 0x0000009D, 0x0 }, 225 { 0x80005012, 0x000000C0, 0x3 }, 226 { 0x80007011, 0x000000C0, 0x3 }, 227 { 0x00002016, 0x0000004F, 0x0 }, 228 { 0x80005012, 0x000000C0, 0x3 }, 229}; 230 231/* Kabylake Y */ 232static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { 233 { 0x00001017, 0x000000A1, 0x0 }, 234 { 0x00005012, 0x00000088, 0x0 }, 235 { 0x80007011, 0x000000CD, 0x3 }, 236 { 0x8000800F, 0x000000C0, 0x3 }, 237 { 0x00001017, 0x0000009D, 0x0 }, 238 { 0x80005012, 0x000000C0, 0x3 }, 239 { 0x80007011, 0x000000C0, 0x3 }, 240 { 0x00001017, 0x0000004C, 0x0 }, 241 { 0x80005012, 0x000000C0, 0x3 }, 242}; 243 244/* 245 * Skylake/Kabylake H and S 246 * eDP 1.4 low vswing translation parameters 247 */ 248static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 249 { 0x00000018, 0x000000A8, 0x0 }, 250 { 0x00004013, 0x000000A9, 0x0 }, 251 { 0x00007011, 0x000000A2, 0x0 }, 252 { 0x00009010, 0x0000009C, 0x0 }, 253 { 0x00000018, 0x000000A9, 0x0 }, 254 { 0x00006013, 0x000000A2, 0x0 }, 255 { 0x00007011, 0x000000A6, 0x0 }, 256 { 0x00000018, 0x000000AB, 0x0 }, 257 { 0x00007013, 0x0000009F, 0x0 }, 258 { 0x00000018, 0x000000DF, 0x0 }, 259}; 260 261/* 262 * Skylake/Kabylake U 263 * eDP 1.4 low vswing translation parameters 264 */ 265static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 266 { 0x00000018, 0x000000A8, 0x0 }, 267 { 0x00004013, 0x000000A9, 0x0 }, 268 { 0x00007011, 0x000000A2, 0x0 }, 269 { 0x00009010, 0x0000009C, 0x0 }, 270 { 0x00000018, 0x000000A9, 0x0 }, 271 { 0x00006013, 0x000000A2, 0x0 }, 272 { 0x00007011, 0x000000A6, 0x0 }, 273 { 0x00002016, 0x000000AB, 0x0 }, 274 { 0x00005013, 0x0000009F, 0x0 }, 275 { 0x00000018, 0x000000DF, 0x0 }, 276}; 277 278/* 279 * Skylake/Kabylake Y 280 * eDP 1.4 low vswing translation parameters 281 */ 282static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 283 { 0x00000018, 0x000000A8, 0x0 }, 284 { 0x00004013, 0x000000AB, 0x0 }, 285 { 0x00007011, 0x000000A4, 0x0 }, 286 { 0x00009010, 0x000000DF, 0x0 }, 287 { 0x00000018, 0x000000AA, 0x0 }, 288 { 0x00006013, 0x000000A4, 0x0 }, 289 { 0x00007011, 0x0000009D, 0x0 }, 290 { 0x00000018, 0x000000A0, 0x0 }, 291 { 0x00006012, 0x000000DF, 0x0 }, 292 { 0x00000018, 0x0000008A, 0x0 }, 293}; 294 295/* Skylake/Kabylake U, H and S */ 296static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 297 { 0x00000018, 0x000000AC, 0x0 }, 298 { 0x00005012, 0x0000009D, 0x0 }, 299 { 0x00007011, 0x00000088, 0x0 }, 300 { 0x00000018, 0x000000A1, 0x0 }, 301 { 0x00000018, 0x00000098, 0x0 }, 302 { 0x00004013, 0x00000088, 0x0 }, 303 { 0x80006012, 0x000000CD, 0x1 }, 304 { 0x00000018, 0x000000DF, 0x0 }, 305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */ 306 { 0x80003015, 0x000000C0, 0x1 }, 307 { 0x80000018, 0x000000C0, 0x1 }, 308}; 309 310/* Skylake/Kabylake Y */ 311static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 312 { 0x00000018, 0x000000A1, 0x0 }, 313 { 0x00005012, 0x000000DF, 0x0 }, 314 { 0x80007011, 0x000000CB, 0x3 }, 315 { 0x00000018, 0x000000A4, 0x0 }, 316 { 0x00000018, 0x0000009D, 0x0 }, 317 { 0x00004013, 0x00000080, 0x0 }, 318 { 0x80006013, 0x000000C0, 0x3 }, 319 { 0x00000018, 0x0000008A, 0x0 }, 320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */ 321 { 0x80003015, 0x000000C0, 0x3 }, 322 { 0x80000018, 0x000000C0, 0x3 }, 323}; 324 325struct bxt_ddi_buf_trans { 326 u8 margin; /* swing value */ 327 u8 scale; /* scale value */ 328 u8 enable; /* scale enable */ 329 u8 deemphasis; 330}; 331 332static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 333 /* Idx NT mV diff db */ 334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */ 337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */ 341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 344}; 345 346static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { 347 /* Idx NT mV diff db */ 348 { 26, 0, 0, 128, }, /* 0: 200 0 */ 349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */ 350 { 48, 0, 0, 96, }, /* 2: 200 4 */ 351 { 54, 0, 0, 69, }, /* 3: 200 6 */ 352 { 32, 0, 0, 128, }, /* 4: 250 0 */ 353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */ 354 { 54, 0, 0, 85, }, /* 6: 250 4 */ 355 { 43, 0, 0, 128, }, /* 7: 300 0 */ 356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */ 357 { 48, 0, 0, 128, }, /* 9: 300 0 */ 358}; 359 360/* BSpec has 2 recommended values - entries 0 and 8. 361 * Using the entry with higher vswing. 362 */ 363static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 364 /* Idx NT mV diff db */ 365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */ 366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */ 367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */ 368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */ 369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */ 370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */ 371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */ 372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */ 373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */ 374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */ 375}; 376 377struct cnl_ddi_buf_trans { 378 u8 dw2_swing_sel; 379 u8 dw7_n_scalar; 380 u8 dw4_cursor_coeff; 381 u8 dw4_post_cursor_2; 382 u8 dw4_post_cursor_1; 383}; 384 385/* Voltage Swing Programming for VccIO 0.85V for DP */ 386static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = { 387 /* NT mV Trans mV db */ 388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 398}; 399 400/* Voltage Swing Programming for VccIO 0.85V for HDMI */ 401static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = { 402 /* NT mV Trans mV db */ 403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */ 407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 410}; 411 412/* Voltage Swing Programming for VccIO 0.85V for eDP */ 413static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = { 414 /* NT mV Trans mV db */ 415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */ 422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */ 423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 424}; 425 426/* Voltage Swing Programming for VccIO 0.95V for DP */ 427static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = { 428 /* NT mV Trans mV db */ 429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */ 431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ 436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */ 437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 439}; 440 441/* Voltage Swing Programming for VccIO 0.95V for HDMI */ 442static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = { 443 /* NT mV Trans mV db */ 444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 455}; 456 457/* Voltage Swing Programming for VccIO 0.95V for eDP */ 458static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = { 459 /* NT mV Trans mV db */ 460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */ 469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 470}; 471 472/* Voltage Swing Programming for VccIO 1.05V for DP */ 473static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = { 474 /* NT mV Trans mV db */ 475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */ 479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */ 482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */ 483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */ 484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 485}; 486 487/* Voltage Swing Programming for VccIO 1.05V for HDMI */ 488static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = { 489 /* NT mV Trans mV db */ 490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */ 492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */ 493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */ 495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */ 497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */ 498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */ 499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */ 500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */ 501}; 502 503/* Voltage Swing Programming for VccIO 1.05V for eDP */ 504static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { 505 /* NT mV Trans mV db */ 506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */ 507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */ 508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */ 509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */ 510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */ 511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */ 512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */ 513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */ 514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ 515}; 516 517/* icl_combo_phy_ddi_translations */ 518static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = { 519 /* NT mV Trans mV db */ 520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 530}; 531 532static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = { 533 /* NT mV Trans mV db */ 534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */ 535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */ 536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */ 537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */ 538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */ 539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */ 540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */ 541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */ 542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */ 543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 544}; 545 546static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = { 547 /* NT mV Trans mV db */ 548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 558}; 559 560static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { 561 /* NT mV Trans mV db */ 562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */ 563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */ 564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */ 565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */ 566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */ 567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */ 568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ 569}; 570 571static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = { 572 /* NT mV Trans mV db */ 573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 575 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */ 576 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */ 577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 578 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */ 579 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ 581 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */ 582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 583}; 584 585struct icl_mg_phy_ddi_buf_trans { 586 u32 cri_txdeemph_override_11_6; 587 u32 cri_txdeemph_override_5_0; 588 u32 cri_txdeemph_override_17_12; 589}; 590 591static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = { 592 /* Voltage swing pre-emphasis */ 593 { 0x18, 0x00, 0x00 }, /* 0 0 */ 594 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 595 { 0x24, 0x00, 0x0C }, /* 0 2 */ 596 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 597 { 0x21, 0x00, 0x00 }, /* 1 0 */ 598 { 0x2B, 0x00, 0x08 }, /* 1 1 */ 599 { 0x30, 0x00, 0x0F }, /* 1 2 */ 600 { 0x31, 0x00, 0x03 }, /* 2 0 */ 601 { 0x34, 0x00, 0x0B }, /* 2 1 */ 602 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 603}; 604 605static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = { 606 /* Voltage swing pre-emphasis */ 607 { 0x18, 0x00, 0x00 }, /* 0 0 */ 608 { 0x1D, 0x00, 0x05 }, /* 0 1 */ 609 { 0x24, 0x00, 0x0C }, /* 0 2 */ 610 { 0x2B, 0x00, 0x14 }, /* 0 3 */ 611 { 0x26, 0x00, 0x00 }, /* 1 0 */ 612 { 0x2C, 0x00, 0x07 }, /* 1 1 */ 613 { 0x33, 0x00, 0x0C }, /* 1 2 */ 614 { 0x2E, 0x00, 0x00 }, /* 2 0 */ 615 { 0x36, 0x00, 0x09 }, /* 2 1 */ 616 { 0x3F, 0x00, 0x00 }, /* 3 0 */ 617}; 618 619static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = { 620 /* HDMI Preset VS Pre-emph */ 621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */ 622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */ 623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */ 624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */ 625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */ 626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */ 629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */ 631}; 632 633struct tgl_dkl_phy_ddi_buf_trans { 634 u32 dkl_vswing_control; 635 u32 dkl_preshoot_control; 636 u32 dkl_de_emphasis_control; 637}; 638 639static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = { 640 /* VS pre-emp Non-trans mV Pre-emph dB */ 641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */ 645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 651}; 652 653static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = { 654 /* VS pre-emp Non-trans mV Pre-emph dB */ 655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */ 656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */ 657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */ 658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */ 659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */ 660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */ 661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */ 662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */ 663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */ 664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */ 665}; 666 667static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { 668 /* HDMI Preset VS Pre-emph */ 669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */ 670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */ 671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */ 672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */ 673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */ 674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */ 675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */ 676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */ 677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */ 678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ 679}; 680 681static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { 682 /* NT mV Trans mV db */ 683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 693}; 694 695static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { 696 /* NT mV Trans mV db */ 697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ 699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ 700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ 701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ 703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ 704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ 706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 707}; 708 709static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { 710 /* NT mV Trans mV db */ 711 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ 712 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ 713 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ 714 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ 715 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ 716 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ 717 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ 718 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ 719 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ 720 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ 721}; 722 723/* 724 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries 725 * that DisplayPort specification requires 726 */ 727static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = { 728 /* VS pre-emp */ 729 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */ 730 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */ 731 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */ 732 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */ 733 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */ 734 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */ 735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */ 736 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */ 737 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */ 738}; 739 740static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table) 741{ 742 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 743} 744 745static const struct ddi_buf_trans * 746bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 747{ 748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 749 750 if (dev_priv->vbt.edp.low_vswing) { 751 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 752 return bdw_ddi_translations_edp; 753 } else { 754 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 755 return bdw_ddi_translations_dp; 756 } 757} 758 759static const struct ddi_buf_trans * 760skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 761{ 762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 763 764 if (IS_SKL_ULX(dev_priv)) { 765 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 766 return skl_y_ddi_translations_dp; 767 } else if (IS_SKL_ULT(dev_priv)) { 768 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 769 return skl_u_ddi_translations_dp; 770 } else { 771 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 772 return skl_ddi_translations_dp; 773 } 774} 775 776static const struct ddi_buf_trans * 777kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 778{ 779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 780 781 if (IS_KBL_ULX(dev_priv) || 782 IS_CFL_ULX(dev_priv) || 783 IS_CML_ULX(dev_priv)) { 784 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); 785 return kbl_y_ddi_translations_dp; 786 } else if (IS_KBL_ULT(dev_priv) || 787 IS_CFL_ULT(dev_priv) || 788 IS_CML_ULT(dev_priv)) { 789 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); 790 return kbl_u_ddi_translations_dp; 791 } else { 792 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); 793 return kbl_ddi_translations_dp; 794 } 795} 796 797static const struct ddi_buf_trans * 798skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 799{ 800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 801 802 if (dev_priv->vbt.edp.low_vswing) { 803 if (IS_SKL_ULX(dev_priv) || 804 IS_KBL_ULX(dev_priv) || 805 IS_CFL_ULX(dev_priv) || 806 IS_CML_ULX(dev_priv)) { 807 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 808 return skl_y_ddi_translations_edp; 809 } else if (IS_SKL_ULT(dev_priv) || 810 IS_KBL_ULT(dev_priv) || 811 IS_CFL_ULT(dev_priv) || 812 IS_CML_ULT(dev_priv)) { 813 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 814 return skl_u_ddi_translations_edp; 815 } else { 816 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 817 return skl_ddi_translations_edp; 818 } 819 } 820 821 if (IS_KABYLAKE(dev_priv) || 822 IS_COFFEELAKE(dev_priv) || 823 IS_COMETLAKE(dev_priv)) 824 return kbl_get_buf_trans_dp(encoder, n_entries); 825 else 826 return skl_get_buf_trans_dp(encoder, n_entries); 827} 828 829static const struct ddi_buf_trans * 830skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) 831{ 832 if (IS_SKL_ULX(dev_priv) || 833 IS_KBL_ULX(dev_priv) || 834 IS_CFL_ULX(dev_priv) || 835 IS_CML_ULX(dev_priv)) { 836 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 837 return skl_y_ddi_translations_hdmi; 838 } else { 839 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 840 return skl_ddi_translations_hdmi; 841 } 842} 843 844static int skl_buf_trans_num_entries(enum port port, int n_entries) 845{ 846 /* Only DDIA and DDIE can select the 10th register with DP */ 847 if (port == PORT_A || port == PORT_E) 848 return min(n_entries, 10); 849 else 850 return min(n_entries, 9); 851} 852 853static const struct ddi_buf_trans * 854intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 855{ 856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 857 858 if (IS_KABYLAKE(dev_priv) || 859 IS_COFFEELAKE(dev_priv) || 860 IS_COMETLAKE(dev_priv)) { 861 const struct ddi_buf_trans *ddi_translations = 862 kbl_get_buf_trans_dp(encoder, n_entries); 863 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 864 return ddi_translations; 865 } else if (IS_SKYLAKE(dev_priv)) { 866 const struct ddi_buf_trans *ddi_translations = 867 skl_get_buf_trans_dp(encoder, n_entries); 868 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 869 return ddi_translations; 870 } else if (IS_BROADWELL(dev_priv)) { 871 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 872 return bdw_ddi_translations_dp; 873 } else if (IS_HASWELL(dev_priv)) { 874 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 875 return hsw_ddi_translations_dp; 876 } 877 878 *n_entries = 0; 879 return NULL; 880} 881 882static const struct ddi_buf_trans * 883intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 884{ 885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 886 887 if (IS_GEN9_BC(dev_priv)) { 888 const struct ddi_buf_trans *ddi_translations = 889 skl_get_buf_trans_edp(encoder, n_entries); 890 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries); 891 return ddi_translations; 892 } else if (IS_BROADWELL(dev_priv)) { 893 return bdw_get_buf_trans_edp(encoder, n_entries); 894 } else if (IS_HASWELL(dev_priv)) { 895 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 896 return hsw_ddi_translations_dp; 897 } 898 899 *n_entries = 0; 900 return NULL; 901} 902 903static const struct ddi_buf_trans * 904intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 905 int *n_entries) 906{ 907 if (IS_BROADWELL(dev_priv)) { 908 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi); 909 return bdw_ddi_translations_fdi; 910 } else if (IS_HASWELL(dev_priv)) { 911 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi); 912 return hsw_ddi_translations_fdi; 913 } 914 915 *n_entries = 0; 916 return NULL; 917} 918 919static const struct ddi_buf_trans * 920intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 921 int *n_entries) 922{ 923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 924 925 if (IS_GEN9_BC(dev_priv)) { 926 return skl_get_buf_trans_hdmi(dev_priv, n_entries); 927 } else if (IS_BROADWELL(dev_priv)) { 928 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 929 return bdw_ddi_translations_hdmi; 930 } else if (IS_HASWELL(dev_priv)) { 931 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 932 return hsw_ddi_translations_hdmi; 933 } 934 935 *n_entries = 0; 936 return NULL; 937} 938 939static const struct bxt_ddi_buf_trans * 940bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 941{ 942 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 943 return bxt_ddi_translations_dp; 944} 945 946static const struct bxt_ddi_buf_trans * 947bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 948{ 949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 950 951 if (dev_priv->vbt.edp.low_vswing) { 952 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); 953 return bxt_ddi_translations_edp; 954 } 955 956 return bxt_get_buf_trans_dp(encoder, n_entries); 957} 958 959static const struct bxt_ddi_buf_trans * 960bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 961{ 962 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 963 return bxt_ddi_translations_hdmi; 964} 965 966static const struct cnl_ddi_buf_trans * 967cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) 968{ 969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 970 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 971 972 if (voltage == VOLTAGE_INFO_0_85V) { 973 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); 974 return cnl_ddi_translations_hdmi_0_85V; 975 } else if (voltage == VOLTAGE_INFO_0_95V) { 976 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V); 977 return cnl_ddi_translations_hdmi_0_95V; 978 } else if (voltage == VOLTAGE_INFO_1_05V) { 979 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V); 980 return cnl_ddi_translations_hdmi_1_05V; 981 } else { 982 *n_entries = 1; /* shut up gcc */ 983 MISSING_CASE(voltage); 984 } 985 return NULL; 986} 987 988static const struct cnl_ddi_buf_trans * 989cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) 990{ 991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 992 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 993 994 if (voltage == VOLTAGE_INFO_0_85V) { 995 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); 996 return cnl_ddi_translations_dp_0_85V; 997 } else if (voltage == VOLTAGE_INFO_0_95V) { 998 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V); 999 return cnl_ddi_translations_dp_0_95V; 1000 } else if (voltage == VOLTAGE_INFO_1_05V) { 1001 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V); 1002 return cnl_ddi_translations_dp_1_05V; 1003 } else { 1004 *n_entries = 1; /* shut up gcc */ 1005 MISSING_CASE(voltage); 1006 } 1007 return NULL; 1008} 1009 1010static const struct cnl_ddi_buf_trans * 1011cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 1012{ 1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1014 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 1015 1016 if (dev_priv->vbt.edp.low_vswing) { 1017 if (voltage == VOLTAGE_INFO_0_85V) { 1018 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V); 1019 return cnl_ddi_translations_edp_0_85V; 1020 } else if (voltage == VOLTAGE_INFO_0_95V) { 1021 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V); 1022 return cnl_ddi_translations_edp_0_95V; 1023 } else if (voltage == VOLTAGE_INFO_1_05V) { 1024 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V); 1025 return cnl_ddi_translations_edp_1_05V; 1026 } else { 1027 *n_entries = 1; /* shut up gcc */ 1028 MISSING_CASE(voltage); 1029 } 1030 return NULL; 1031 } else { 1032 return cnl_get_buf_trans_dp(encoder, n_entries); 1033 } 1034} 1035 1036static const struct cnl_ddi_buf_trans * 1037icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1038 int *n_entries) 1039{ 1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1041 1042 if (type == INTEL_OUTPUT_HDMI) { 1043 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1044 return icl_combo_phy_ddi_translations_hdmi; 1045 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) { 1046 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1047 return icl_combo_phy_ddi_translations_edp_hbr3; 1048 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { 1049 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1050 return icl_combo_phy_ddi_translations_edp_hbr2; 1051 } 1052 1053 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2); 1054 return icl_combo_phy_ddi_translations_dp_hbr2; 1055} 1056 1057static const struct icl_mg_phy_ddi_buf_trans * 1058icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate, 1059 int *n_entries) 1060{ 1061 if (type == INTEL_OUTPUT_HDMI) { 1062 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi); 1063 return icl_mg_phy_ddi_translations_hdmi; 1064 } else if (rate > 270000) { 1065 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3); 1066 return icl_mg_phy_ddi_translations_hbr2_hbr3; 1067 } 1068 1069 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr); 1070 return icl_mg_phy_ddi_translations_rbr_hbr; 1071} 1072 1073static const struct cnl_ddi_buf_trans * 1074ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1075 int *n_entries) 1076{ 1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1078 1079 switch (type) { 1080 case INTEL_OUTPUT_HDMI: 1081 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1082 return icl_combo_phy_ddi_translations_hdmi; 1083 case INTEL_OUTPUT_EDP: 1084 if (dev_priv->vbt.edp.low_vswing) { 1085 if (rate > 540000) { 1086 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1087 return icl_combo_phy_ddi_translations_edp_hbr3; 1088 } else { 1089 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1090 return icl_combo_phy_ddi_translations_edp_hbr2; 1091 } 1092 } 1093 /* fall through */ 1094 default: 1095 /* All combo DP and eDP ports that do not support low_vswing */ 1096 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp); 1097 return ehl_combo_phy_ddi_translations_dp; 1098 } 1099} 1100 1101static const struct cnl_ddi_buf_trans * 1102tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, 1103 int *n_entries) 1104{ 1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1106 1107 switch (type) { 1108 case INTEL_OUTPUT_HDMI: 1109 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); 1110 return icl_combo_phy_ddi_translations_hdmi; 1111 case INTEL_OUTPUT_EDP: 1112 if (dev_priv->vbt.edp.hobl) { 1113 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1114 1115 if (!intel_dp->hobl_failed && rate <= 540000) { 1116 /* Same table applies to TGL, RKL and DG1 */ 1117 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl); 1118 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl; 1119 } 1120 } 1121 1122 if (rate > 540000) { 1123 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3); 1124 return icl_combo_phy_ddi_translations_edp_hbr3; 1125 } else if (dev_priv->vbt.edp.low_vswing) { 1126 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2); 1127 return icl_combo_phy_ddi_translations_edp_hbr2; 1128 } 1129 /* fall through */ 1130 default: 1131 /* All combo DP and eDP ports that do not support low_vswing */ 1132 if (rate > 270000) { 1133 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1134 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); 1135 return tgl_uy_combo_phy_ddi_translations_dp_hbr2; 1136 } 1137 1138 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); 1139 return tgl_combo_phy_ddi_translations_dp_hbr2; 1140 } 1141 1142 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); 1143 return tgl_combo_phy_ddi_translations_dp_hbr; 1144 } 1145} 1146 1147static const struct tgl_dkl_phy_ddi_buf_trans * 1148tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate, 1149 int *n_entries) 1150{ 1151 if (type == INTEL_OUTPUT_HDMI) { 1152 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); 1153 return tgl_dkl_phy_hdmi_ddi_trans; 1154 } else if (rate > 270000) { 1155 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2); 1156 return tgl_dkl_phy_dp_ddi_trans_hbr2; 1157 } 1158 1159 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); 1160 return tgl_dkl_phy_dp_ddi_trans; 1161} 1162 1163static int intel_ddi_hdmi_level(struct intel_encoder *encoder) 1164{ 1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1166 int n_entries, level, default_entry; 1167 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1168 1169 if (INTEL_GEN(dev_priv) >= 12) { 1170 if (intel_phy_is_combo(dev_priv, phy)) 1171 tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 1172 0, &n_entries); 1173 else 1174 tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, 1175 &n_entries); 1176 default_entry = n_entries - 1; 1177 } else if (INTEL_GEN(dev_priv) == 11) { 1178 if (intel_phy_is_combo(dev_priv, phy)) 1179 icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 1180 0, &n_entries); 1181 else 1182 icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, 1183 &n_entries); 1184 default_entry = n_entries - 1; 1185 } else if (IS_CANNONLAKE(dev_priv)) { 1186 cnl_get_buf_trans_hdmi(encoder, &n_entries); 1187 default_entry = n_entries - 1; 1188 } else if (IS_GEN9_LP(dev_priv)) { 1189 bxt_get_buf_trans_hdmi(encoder, &n_entries); 1190 default_entry = n_entries - 1; 1191 } else if (IS_GEN9_BC(dev_priv)) { 1192 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1193 default_entry = 8; 1194 } else if (IS_BROADWELL(dev_priv)) { 1195 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1196 default_entry = 7; 1197 } else if (IS_HASWELL(dev_priv)) { 1198 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1199 default_entry = 6; 1200 } else { 1201 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); 1202 return 0; 1203 } 1204 1205 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) 1206 return 0; 1207 1208 level = intel_bios_hdmi_level_shift(encoder); 1209 if (level < 0) 1210 level = default_entry; 1211 1212 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1213 level = n_entries - 1; 1214 1215 return level; 1216} 1217 1218/* 1219 * Starting with Haswell, DDI port buffers must be programmed with correct 1220 * values in advance. This function programs the correct values for 1221 * DP/eDP/FDI use cases. 1222 */ 1223static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 1224 const struct intel_crtc_state *crtc_state) 1225{ 1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1227 u32 iboost_bit = 0; 1228 int i, n_entries; 1229 enum port port = encoder->port; 1230 const struct ddi_buf_trans *ddi_translations; 1231 1232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1233 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, 1234 &n_entries); 1235 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1236 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 1237 &n_entries); 1238 else 1239 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 1240 &n_entries); 1241 1242 /* If we're boosting the current, set bit 31 of trans1 */ 1243 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) 1244 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1245 1246 for (i = 0; i < n_entries; i++) { 1247 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 1248 ddi_translations[i].trans1 | iboost_bit); 1249 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 1250 ddi_translations[i].trans2); 1251 } 1252} 1253 1254/* 1255 * Starting with Haswell, DDI port buffers must be programmed with correct 1256 * values in advance. This function programs the correct values for 1257 * HDMI/DVI use cases. 1258 */ 1259static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 1260 int level) 1261{ 1262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1263 u32 iboost_bit = 0; 1264 int n_entries; 1265 enum port port = encoder->port; 1266 const struct ddi_buf_trans *ddi_translations; 1267 1268 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 1269 1270 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1271 return; 1272 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1273 level = n_entries - 1; 1274 1275 /* If we're boosting the current, set bit 31 of trans1 */ 1276 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) 1277 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 1278 1279 /* Entry 9 is for HDMI: */ 1280 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 1281 ddi_translations[level].trans1 | iboost_bit); 1282 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 1283 ddi_translations[level].trans2); 1284} 1285 1286static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 1287 enum port port) 1288{ 1289 if (IS_BROXTON(dev_priv)) { 1290 udelay(16); 1291 return; 1292 } 1293 1294 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1295 DDI_BUF_IS_IDLE), 8)) 1296 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 1297 port_name(port)); 1298} 1299 1300static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 1301 enum port port) 1302{ 1303 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 1304 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { 1305 usleep_range(518, 1000); 1306 return; 1307 } 1308 1309 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1310 DDI_BUF_IS_IDLE), 500)) 1311 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 1312 port_name(port)); 1313} 1314 1315static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 1316{ 1317 switch (pll->info->id) { 1318 case DPLL_ID_WRPLL1: 1319 return PORT_CLK_SEL_WRPLL1; 1320 case DPLL_ID_WRPLL2: 1321 return PORT_CLK_SEL_WRPLL2; 1322 case DPLL_ID_SPLL: 1323 return PORT_CLK_SEL_SPLL; 1324 case DPLL_ID_LCPLL_810: 1325 return PORT_CLK_SEL_LCPLL_810; 1326 case DPLL_ID_LCPLL_1350: 1327 return PORT_CLK_SEL_LCPLL_1350; 1328 case DPLL_ID_LCPLL_2700: 1329 return PORT_CLK_SEL_LCPLL_2700; 1330 default: 1331 MISSING_CASE(pll->info->id); 1332 return PORT_CLK_SEL_NONE; 1333 } 1334} 1335 1336static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 1337 const struct intel_crtc_state *crtc_state) 1338{ 1339 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1340 int clock = crtc_state->port_clock; 1341 const enum intel_dpll_id id = pll->info->id; 1342 1343 switch (id) { 1344 default: 1345 /* 1346 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 1347 * here, so do warn if this get passed in 1348 */ 1349 MISSING_CASE(id); 1350 return DDI_CLK_SEL_NONE; 1351 case DPLL_ID_ICL_TBTPLL: 1352 switch (clock) { 1353 case 162000: 1354 return DDI_CLK_SEL_TBT_162; 1355 case 270000: 1356 return DDI_CLK_SEL_TBT_270; 1357 case 540000: 1358 return DDI_CLK_SEL_TBT_540; 1359 case 810000: 1360 return DDI_CLK_SEL_TBT_810; 1361 default: 1362 MISSING_CASE(clock); 1363 return DDI_CLK_SEL_NONE; 1364 } 1365 case DPLL_ID_ICL_MGPLL1: 1366 case DPLL_ID_ICL_MGPLL2: 1367 case DPLL_ID_ICL_MGPLL3: 1368 case DPLL_ID_ICL_MGPLL4: 1369 case DPLL_ID_TGL_MGPLL5: 1370 case DPLL_ID_TGL_MGPLL6: 1371 return DDI_CLK_SEL_MG; 1372 } 1373} 1374 1375/* Starting with Haswell, different DDI ports can work in FDI mode for 1376 * connection to the PCH-located connectors. For this, it is necessary to train 1377 * both the DDI port and PCH receiver for the desired DDI buffer settings. 1378 * 1379 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 1380 * please note that when FDI mode is active on DDI E, it shares 2 lines with 1381 * DDI A (which is used for eDP) 1382 */ 1383 1384void hsw_fdi_link_train(struct intel_encoder *encoder, 1385 const struct intel_crtc_state *crtc_state) 1386{ 1387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1388 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1389 u32 temp, i, rx_ctl_val, ddi_pll_sel; 1390 1391 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 1392 1393 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 1394 * mode set "sequence for CRT port" document: 1395 * - TP1 to TP2 time with the default value 1396 * - FDI delay to 90h 1397 * 1398 * WaFDIAutoLinkSetTimingOverrride:hsw 1399 */ 1400 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 1401 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 1402 1403 /* Enable the PCH Receiver FDI PLL */ 1404 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1405 FDI_RX_PLL_ENABLE | 1406 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1407 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1408 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1409 udelay(220); 1410 1411 /* Switch from Rawclk to PCDclk */ 1412 rx_ctl_val |= FDI_PCDCLK; 1413 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1414 1415 /* Configure Port Clock Select */ 1416 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); 1417 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); 1418 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); 1419 1420 /* Start the training iterating through available voltages and emphasis, 1421 * testing each value twice. */ 1422 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 1423 /* Configure DP_TP_CTL with auto-training */ 1424 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1425 DP_TP_CTL_FDI_AUTOTRAIN | 1426 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1427 DP_TP_CTL_LINK_TRAIN_PAT1 | 1428 DP_TP_CTL_ENABLE); 1429 1430 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 1431 * DDI E does not support port reversal, the functionality is 1432 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 1433 * port reversal bit */ 1434 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 1435 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); 1436 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1437 1438 udelay(600); 1439 1440 /* Program PCH FDI Receiver TU */ 1441 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 1442 1443 /* Enable PCH FDI Receiver with auto-training */ 1444 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 1445 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1446 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1447 1448 /* Wait for FDI receiver lane calibration */ 1449 udelay(30); 1450 1451 /* Unset FDI_RX_MISC pwrdn lanes */ 1452 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1453 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1454 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1455 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1456 1457 /* Wait for FDI auto training time */ 1458 udelay(5); 1459 1460 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 1461 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 1462 drm_dbg_kms(&dev_priv->drm, 1463 "FDI link training done on step %d\n", i); 1464 break; 1465 } 1466 1467 /* 1468 * Leave things enabled even if we failed to train FDI. 1469 * Results in less fireworks from the state checker. 1470 */ 1471 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { 1472 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 1473 break; 1474 } 1475 1476 rx_ctl_val &= ~FDI_RX_ENABLE; 1477 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 1478 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 1479 1480 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1481 temp &= ~DDI_BUF_CTL_ENABLE; 1482 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); 1483 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 1484 1485 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 1486 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); 1487 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 1488 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1489 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); 1490 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 1491 1492 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1493 1494 /* Reset FDI_RX_MISC pwrdn lanes */ 1495 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1496 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 1497 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 1498 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); 1499 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 1500 } 1501 1502 /* Enable normal pixel sending for FDI */ 1503 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 1504 DP_TP_CTL_FDI_AUTOTRAIN | 1505 DP_TP_CTL_LINK_TRAIN_NORMAL | 1506 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 1507 DP_TP_CTL_ENABLE); 1508} 1509 1510static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 1511{ 1512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1513 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1514 1515 intel_dp->DP = dig_port->saved_port_bits | 1516 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 1517 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 1518} 1519 1520static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 1521 enum port port) 1522{ 1523 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 1524 1525 switch (val) { 1526 case DDI_CLK_SEL_NONE: 1527 return 0; 1528 case DDI_CLK_SEL_TBT_162: 1529 return 162000; 1530 case DDI_CLK_SEL_TBT_270: 1531 return 270000; 1532 case DDI_CLK_SEL_TBT_540: 1533 return 540000; 1534 case DDI_CLK_SEL_TBT_810: 1535 return 810000; 1536 default: 1537 MISSING_CASE(val); 1538 return 0; 1539 } 1540} 1541 1542static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1543{ 1544 int dotclock; 1545 1546 if (pipe_config->has_pch_encoder) 1547 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1548 &pipe_config->fdi_m_n); 1549 else if (intel_crtc_has_dp_encoder(pipe_config)) 1550 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1551 &pipe_config->dp_m_n); 1552 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 1553 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 1554 else 1555 dotclock = pipe_config->port_clock; 1556 1557 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 1558 !intel_crtc_has_dp_encoder(pipe_config)) 1559 dotclock *= 2; 1560 1561 if (pipe_config->pixel_multiplier) 1562 dotclock /= pipe_config->pixel_multiplier; 1563 1564 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1565} 1566 1567static void intel_ddi_clock_get(struct intel_encoder *encoder, 1568 struct intel_crtc_state *pipe_config) 1569{ 1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1571 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1572 1573 if (intel_phy_is_tc(dev_priv, phy) && 1574 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == 1575 DPLL_ID_ICL_TBTPLL) 1576 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, 1577 encoder->port); 1578 else 1579 pipe_config->port_clock = 1580 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); 1581 1582 ddi_dotclock_get(pipe_config); 1583} 1584 1585void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 1586 const struct drm_connector_state *conn_state) 1587{ 1588 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1591 u32 temp; 1592 1593 if (!intel_crtc_has_dp_encoder(crtc_state)) 1594 return; 1595 1596 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 1597 1598 temp = DP_MSA_MISC_SYNC_CLOCK; 1599 1600 switch (crtc_state->pipe_bpp) { 1601 case 18: 1602 temp |= DP_MSA_MISC_6_BPC; 1603 break; 1604 case 24: 1605 temp |= DP_MSA_MISC_8_BPC; 1606 break; 1607 case 30: 1608 temp |= DP_MSA_MISC_10_BPC; 1609 break; 1610 case 36: 1611 temp |= DP_MSA_MISC_12_BPC; 1612 break; 1613 default: 1614 MISSING_CASE(crtc_state->pipe_bpp); 1615 break; 1616 } 1617 1618 /* nonsense combination */ 1619 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 1620 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 1621 1622 if (crtc_state->limited_color_range) 1623 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 1624 1625 /* 1626 * As per DP 1.2 spec section 2.3.4.3 while sending 1627 * YCBCR 444 signals we should program MSA MISC1/0 fields with 1628 * colorspace information. 1629 */ 1630 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 1631 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 1632 1633 /* 1634 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 1635 * of Color Encoding Format and Content Color Gamut] while sending 1636 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 1637 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 1638 */ 1639 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1640 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 1641 1642 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 1643} 1644 1645static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 1646{ 1647 if (master_transcoder == TRANSCODER_EDP) 1648 return 0; 1649 else 1650 return master_transcoder + 1; 1651} 1652 1653/* 1654 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 1655 * 1656 * Only intended to be used by intel_ddi_enable_transcoder_func() and 1657 * intel_ddi_config_transcoder_func(). 1658 */ 1659static u32 1660intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 1661 const struct intel_crtc_state *crtc_state) 1662{ 1663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1665 enum pipe pipe = crtc->pipe; 1666 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1667 enum port port = encoder->port; 1668 u32 temp; 1669 1670 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1671 temp = TRANS_DDI_FUNC_ENABLE; 1672 if (INTEL_GEN(dev_priv) >= 12) 1673 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 1674 else 1675 temp |= TRANS_DDI_SELECT_PORT(port); 1676 1677 switch (crtc_state->pipe_bpp) { 1678 case 18: 1679 temp |= TRANS_DDI_BPC_6; 1680 break; 1681 case 24: 1682 temp |= TRANS_DDI_BPC_8; 1683 break; 1684 case 30: 1685 temp |= TRANS_DDI_BPC_10; 1686 break; 1687 case 36: 1688 temp |= TRANS_DDI_BPC_12; 1689 break; 1690 default: 1691 BUG(); 1692 } 1693 1694 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1695 temp |= TRANS_DDI_PVSYNC; 1696 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1697 temp |= TRANS_DDI_PHSYNC; 1698 1699 if (cpu_transcoder == TRANSCODER_EDP) { 1700 switch (pipe) { 1701 case PIPE_A: 1702 /* On Haswell, can only use the always-on power well for 1703 * eDP when not using the panel fitter, and when not 1704 * using motion blur mitigation (which we don't 1705 * support). */ 1706 if (crtc_state->pch_pfit.force_thru) 1707 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1708 else 1709 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1710 break; 1711 case PIPE_B: 1712 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1713 break; 1714 case PIPE_C: 1715 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1716 break; 1717 default: 1718 BUG(); 1719 break; 1720 } 1721 } 1722 1723 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1724 if (crtc_state->has_hdmi_sink) 1725 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1726 else 1727 temp |= TRANS_DDI_MODE_SELECT_DVI; 1728 1729 if (crtc_state->hdmi_scrambling) 1730 temp |= TRANS_DDI_HDMI_SCRAMBLING; 1731 if (crtc_state->hdmi_high_tmds_clock_ratio) 1732 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 1733 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1734 temp |= TRANS_DDI_MODE_SELECT_FDI; 1735 temp |= (crtc_state->fdi_lanes - 1) << 1; 1736 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 1737 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1738 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1739 1740 if (INTEL_GEN(dev_priv) >= 12) { 1741 enum transcoder master; 1742 1743 master = crtc_state->mst_master_transcoder; 1744 drm_WARN_ON(&dev_priv->drm, 1745 master == INVALID_TRANSCODER); 1746 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 1747 } 1748 } else { 1749 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1750 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 1751 } 1752 1753 if (IS_GEN_RANGE(dev_priv, 8, 10) && 1754 crtc_state->master_transcoder != INVALID_TRANSCODER) { 1755 u8 master_select = 1756 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 1757 1758 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 1759 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 1760 } 1761 1762 return temp; 1763} 1764 1765void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 1766 const struct intel_crtc_state *crtc_state) 1767{ 1768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1771 1772 if (INTEL_GEN(dev_priv) >= 11) { 1773 enum transcoder master_transcoder = crtc_state->master_transcoder; 1774 u32 ctl2 = 0; 1775 1776 if (master_transcoder != INVALID_TRANSCODER) { 1777 u8 master_select = 1778 bdw_trans_port_sync_master_select(master_transcoder); 1779 1780 ctl2 |= PORT_SYNC_MODE_ENABLE | 1781 PORT_SYNC_MODE_MASTER_SELECT(master_select); 1782 } 1783 1784 intel_de_write(dev_priv, 1785 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 1786 } 1787 1788 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 1789 intel_ddi_transcoder_func_reg_val_get(encoder, 1790 crtc_state)); 1791} 1792 1793/* 1794 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 1795 * bit. 1796 */ 1797static void 1798intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 1799 const struct intel_crtc_state *crtc_state) 1800{ 1801 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1803 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1804 u32 ctl; 1805 1806 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 1807 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1808 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1809} 1810 1811void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 1812{ 1813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1814 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1815 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1816 u32 ctl; 1817 1818 if (INTEL_GEN(dev_priv) >= 11) 1819 intel_de_write(dev_priv, 1820 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 1821 1822 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1823 1824 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 1825 1826 ctl &= ~TRANS_DDI_FUNC_ENABLE; 1827 1828 if (IS_GEN_RANGE(dev_priv, 8, 10)) 1829 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 1830 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 1831 1832 if (INTEL_GEN(dev_priv) >= 12) { 1833 if (!intel_dp_mst_is_master_trans(crtc_state)) { 1834 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 1835 TRANS_DDI_MODE_SELECT_MASK); 1836 } 1837 } else { 1838 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 1839 } 1840 1841 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 1842 1843 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 1844 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1845 drm_dbg_kms(&dev_priv->drm, 1846 "Quirk Increase DDI disabled time\n"); 1847 /* Quirk time at 100ms for reliable operation */ 1848 msleep(100); 1849 } 1850} 1851 1852int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 1853 enum transcoder cpu_transcoder, 1854 bool enable) 1855{ 1856 struct drm_device *dev = intel_encoder->base.dev; 1857 struct drm_i915_private *dev_priv = to_i915(dev); 1858 intel_wakeref_t wakeref; 1859 int ret = 0; 1860 u32 tmp; 1861 1862 wakeref = intel_display_power_get_if_enabled(dev_priv, 1863 intel_encoder->power_domain); 1864 if (drm_WARN_ON(dev, !wakeref)) 1865 return -ENXIO; 1866 1867 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1868 if (enable) 1869 tmp |= TRANS_DDI_HDCP_SIGNALLING; 1870 else 1871 tmp &= ~TRANS_DDI_HDCP_SIGNALLING; 1872 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 1873 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 1874 return ret; 1875} 1876 1877bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1878{ 1879 struct drm_device *dev = intel_connector->base.dev; 1880 struct drm_i915_private *dev_priv = to_i915(dev); 1881 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 1882 int type = intel_connector->base.connector_type; 1883 enum port port = encoder->port; 1884 enum transcoder cpu_transcoder; 1885 intel_wakeref_t wakeref; 1886 enum pipe pipe = 0; 1887 u32 tmp; 1888 bool ret; 1889 1890 wakeref = intel_display_power_get_if_enabled(dev_priv, 1891 encoder->power_domain); 1892 if (!wakeref) 1893 return false; 1894 1895 if (!encoder->get_hw_state(encoder, &pipe)) { 1896 ret = false; 1897 goto out; 1898 } 1899 1900 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 1901 cpu_transcoder = TRANSCODER_EDP; 1902 else 1903 cpu_transcoder = (enum transcoder) pipe; 1904 1905 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1906 1907 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1908 case TRANS_DDI_MODE_SELECT_HDMI: 1909 case TRANS_DDI_MODE_SELECT_DVI: 1910 ret = type == DRM_MODE_CONNECTOR_HDMIA; 1911 break; 1912 1913 case TRANS_DDI_MODE_SELECT_DP_SST: 1914 ret = type == DRM_MODE_CONNECTOR_eDP || 1915 type == DRM_MODE_CONNECTOR_DisplayPort; 1916 break; 1917 1918 case TRANS_DDI_MODE_SELECT_DP_MST: 1919 /* if the transcoder is in MST state then 1920 * connector isn't connected */ 1921 ret = false; 1922 break; 1923 1924 case TRANS_DDI_MODE_SELECT_FDI: 1925 ret = type == DRM_MODE_CONNECTOR_VGA; 1926 break; 1927 1928 default: 1929 ret = false; 1930 break; 1931 } 1932 1933out: 1934 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1935 1936 return ret; 1937} 1938 1939static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 1940 u8 *pipe_mask, bool *is_dp_mst) 1941{ 1942 struct drm_device *dev = encoder->base.dev; 1943 struct drm_i915_private *dev_priv = to_i915(dev); 1944 enum port port = encoder->port; 1945 intel_wakeref_t wakeref; 1946 enum pipe p; 1947 u32 tmp; 1948 u8 mst_pipe_mask; 1949 1950 *pipe_mask = 0; 1951 *is_dp_mst = false; 1952 1953 wakeref = intel_display_power_get_if_enabled(dev_priv, 1954 encoder->power_domain); 1955 if (!wakeref) 1956 return; 1957 1958 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1959 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1960 goto out; 1961 1962 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 1963 tmp = intel_de_read(dev_priv, 1964 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1965 1966 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1967 default: 1968 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 1969 fallthrough; 1970 case TRANS_DDI_EDP_INPUT_A_ON: 1971 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1972 *pipe_mask = BIT(PIPE_A); 1973 break; 1974 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1975 *pipe_mask = BIT(PIPE_B); 1976 break; 1977 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1978 *pipe_mask = BIT(PIPE_C); 1979 break; 1980 } 1981 1982 goto out; 1983 } 1984 1985 mst_pipe_mask = 0; 1986 for_each_pipe(dev_priv, p) { 1987 enum transcoder cpu_transcoder = (enum transcoder)p; 1988 unsigned int port_mask, ddi_select; 1989 intel_wakeref_t trans_wakeref; 1990 1991 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 1992 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 1993 if (!trans_wakeref) 1994 continue; 1995 1996 if (INTEL_GEN(dev_priv) >= 12) { 1997 port_mask = TGL_TRANS_DDI_PORT_MASK; 1998 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 1999 } else { 2000 port_mask = TRANS_DDI_PORT_MASK; 2001 ddi_select = TRANS_DDI_SELECT_PORT(port); 2002 } 2003 2004 tmp = intel_de_read(dev_priv, 2005 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2006 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 2007 trans_wakeref); 2008 2009 if ((tmp & port_mask) != ddi_select) 2010 continue; 2011 2012 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 2013 TRANS_DDI_MODE_SELECT_DP_MST) 2014 mst_pipe_mask |= BIT(p); 2015 2016 *pipe_mask |= BIT(p); 2017 } 2018 2019 if (!*pipe_mask) 2020 drm_dbg_kms(&dev_priv->drm, 2021 "No pipe for [ENCODER:%d:%s] found\n", 2022 encoder->base.base.id, encoder->base.name); 2023 2024 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 2025 drm_dbg_kms(&dev_priv->drm, 2026 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 2027 encoder->base.base.id, encoder->base.name, 2028 *pipe_mask); 2029 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 2030 } 2031 2032 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 2033 drm_dbg_kms(&dev_priv->drm, 2034 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 2035 encoder->base.base.id, encoder->base.name, 2036 *pipe_mask, mst_pipe_mask); 2037 else 2038 *is_dp_mst = mst_pipe_mask; 2039 2040out: 2041 if (*pipe_mask && IS_GEN9_LP(dev_priv)) { 2042 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 2043 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 2044 BXT_PHY_LANE_POWERDOWN_ACK | 2045 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 2046 drm_err(&dev_priv->drm, 2047 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 2048 encoder->base.base.id, encoder->base.name, tmp); 2049 } 2050 2051 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 2052} 2053 2054bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 2055 enum pipe *pipe) 2056{ 2057 u8 pipe_mask; 2058 bool is_mst; 2059 2060 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2061 2062 if (is_mst || !pipe_mask) 2063 return false; 2064 2065 *pipe = ffs(pipe_mask) - 1; 2066 2067 return true; 2068} 2069 2070static enum intel_display_power_domain 2071intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 2072{ 2073 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 2074 * DC states enabled at the same time, while for driver initiated AUX 2075 * transfers we need the same AUX IOs to be powered but with DC states 2076 * disabled. Accordingly use the AUX power domain here which leaves DC 2077 * states enabled. 2078 * However, for non-A AUX ports the corresponding non-EDP transcoders 2079 * would have already enabled power well 2 and DC_OFF. This means we can 2080 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 2081 * specific AUX_IO reference without powering up any extra wells. 2082 * Note that PSR is enabled only on Port A even though this function 2083 * returns the correct domain for other ports too. 2084 */ 2085 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 2086 intel_aux_power_domain(dig_port); 2087} 2088 2089static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 2090 struct intel_crtc_state *crtc_state) 2091{ 2092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2093 struct intel_digital_port *dig_port; 2094 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2095 2096 /* 2097 * TODO: Add support for MST encoders. Atm, the following should never 2098 * happen since fake-MST encoders don't set their get_power_domains() 2099 * hook. 2100 */ 2101 if (drm_WARN_ON(&dev_priv->drm, 2102 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 2103 return; 2104 2105 dig_port = enc_to_dig_port(encoder); 2106 2107 if (!intel_phy_is_tc(dev_priv, phy) || 2108 dig_port->tc_mode != TC_PORT_TBT_ALT) 2109 intel_display_power_get(dev_priv, 2110 dig_port->ddi_io_power_domain); 2111 2112 /* 2113 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 2114 * ports. 2115 */ 2116 if (intel_crtc_has_dp_encoder(crtc_state) || 2117 intel_phy_is_tc(dev_priv, phy)) 2118 intel_display_power_get(dev_priv, 2119 intel_ddi_main_link_aux_domain(dig_port)); 2120 2121 /* 2122 * VDSC power is needed when DSC is enabled 2123 */ 2124 if (crtc_state->dsc.compression_enable) 2125 intel_display_power_get(dev_priv, 2126 intel_dsc_power_domain(crtc_state)); 2127} 2128 2129void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 2130 const struct intel_crtc_state *crtc_state) 2131{ 2132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2134 enum port port = encoder->port; 2135 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2136 2137 if (cpu_transcoder != TRANSCODER_EDP) { 2138 if (INTEL_GEN(dev_priv) >= 12) 2139 intel_de_write(dev_priv, 2140 TRANS_CLK_SEL(cpu_transcoder), 2141 TGL_TRANS_CLK_SEL_PORT(port)); 2142 else 2143 intel_de_write(dev_priv, 2144 TRANS_CLK_SEL(cpu_transcoder), 2145 TRANS_CLK_SEL_PORT(port)); 2146 } 2147} 2148 2149void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 2150{ 2151 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2152 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2153 2154 if (cpu_transcoder != TRANSCODER_EDP) { 2155 if (INTEL_GEN(dev_priv) >= 12) 2156 intel_de_write(dev_priv, 2157 TRANS_CLK_SEL(cpu_transcoder), 2158 TGL_TRANS_CLK_SEL_DISABLED); 2159 else 2160 intel_de_write(dev_priv, 2161 TRANS_CLK_SEL(cpu_transcoder), 2162 TRANS_CLK_SEL_DISABLED); 2163 } 2164} 2165 2166static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 2167 enum port port, u8 iboost) 2168{ 2169 u32 tmp; 2170 2171 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 2172 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 2173 if (iboost) 2174 tmp |= iboost << BALANCE_LEG_SHIFT(port); 2175 else 2176 tmp |= BALANCE_LEG_DISABLE(port); 2177 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 2178} 2179 2180static void skl_ddi_set_iboost(struct intel_encoder *encoder, 2181 int level, enum intel_output_type type) 2182{ 2183 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2185 u8 iboost; 2186 2187 if (type == INTEL_OUTPUT_HDMI) 2188 iboost = intel_bios_hdmi_boost_level(encoder); 2189 else 2190 iboost = intel_bios_dp_boost_level(encoder); 2191 2192 if (iboost == 0) { 2193 const struct ddi_buf_trans *ddi_translations; 2194 int n_entries; 2195 2196 if (type == INTEL_OUTPUT_HDMI) 2197 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); 2198 else if (type == INTEL_OUTPUT_EDP) 2199 ddi_translations = intel_ddi_get_buf_trans_edp(encoder, 2200 &n_entries); 2201 else 2202 ddi_translations = intel_ddi_get_buf_trans_dp(encoder, 2203 &n_entries); 2204 2205 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2206 return; 2207 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2208 level = n_entries - 1; 2209 2210 iboost = ddi_translations[level].i_boost; 2211 } 2212 2213 /* Make sure that the requested I_boost is valid */ 2214 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2215 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 2216 return; 2217 } 2218 2219 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 2220 2221 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 2222 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 2223} 2224 2225static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 2226 int level, enum intel_output_type type) 2227{ 2228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2229 const struct bxt_ddi_buf_trans *ddi_translations; 2230 enum port port = encoder->port; 2231 int n_entries; 2232 2233 if (type == INTEL_OUTPUT_HDMI) 2234 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); 2235 else if (type == INTEL_OUTPUT_EDP) 2236 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); 2237 else 2238 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); 2239 2240 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2241 return; 2242 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2243 level = n_entries - 1; 2244 2245 bxt_ddi_phy_set_signal_level(dev_priv, port, 2246 ddi_translations[level].margin, 2247 ddi_translations[level].scale, 2248 ddi_translations[level].enable, 2249 ddi_translations[level].deemphasis); 2250} 2251 2252static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) 2253{ 2254 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2256 enum port port = encoder->port; 2257 enum phy phy = intel_port_to_phy(dev_priv, port); 2258 int n_entries; 2259 2260 if (INTEL_GEN(dev_priv) >= 12) { 2261 if (intel_phy_is_combo(dev_priv, phy)) 2262 tgl_get_combo_buf_trans(encoder, encoder->type, 2263 intel_dp->link_rate, &n_entries); 2264 else 2265 tgl_get_dkl_buf_trans(encoder, encoder->type, 2266 intel_dp->link_rate, &n_entries); 2267 } else if (INTEL_GEN(dev_priv) == 11) { 2268 if (IS_ELKHARTLAKE(dev_priv)) 2269 ehl_get_combo_buf_trans(encoder, encoder->type, 2270 intel_dp->link_rate, &n_entries); 2271 else if (intel_phy_is_combo(dev_priv, phy)) 2272 icl_get_combo_buf_trans(encoder, encoder->type, 2273 intel_dp->link_rate, &n_entries); 2274 else 2275 icl_get_mg_buf_trans(encoder, encoder->type, 2276 intel_dp->link_rate, &n_entries); 2277 } else if (IS_CANNONLAKE(dev_priv)) { 2278 if (encoder->type == INTEL_OUTPUT_EDP) 2279 cnl_get_buf_trans_edp(encoder, &n_entries); 2280 else 2281 cnl_get_buf_trans_dp(encoder, &n_entries); 2282 } else if (IS_GEN9_LP(dev_priv)) { 2283 if (encoder->type == INTEL_OUTPUT_EDP) 2284 bxt_get_buf_trans_edp(encoder, &n_entries); 2285 else 2286 bxt_get_buf_trans_dp(encoder, &n_entries); 2287 } else { 2288 if (encoder->type == INTEL_OUTPUT_EDP) 2289 intel_ddi_get_buf_trans_edp(encoder, &n_entries); 2290 else 2291 intel_ddi_get_buf_trans_dp(encoder, &n_entries); 2292 } 2293 2294 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 2295 n_entries = 1; 2296 if (drm_WARN_ON(&dev_priv->drm, 2297 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 2298 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 2299 2300 return index_to_dp_signal_levels[n_entries - 1] & 2301 DP_TRAIN_VOLTAGE_SWING_MASK; 2302} 2303 2304/* 2305 * We assume that the full set of pre-emphasis values can be 2306 * used on all DDI platforms. Should that change we need to 2307 * rethink this code. 2308 */ 2309static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 2310{ 2311 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2312} 2313 2314static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 2315 int level, enum intel_output_type type) 2316{ 2317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2318 const struct cnl_ddi_buf_trans *ddi_translations; 2319 enum port port = encoder->port; 2320 int n_entries, ln; 2321 u32 val; 2322 2323 if (type == INTEL_OUTPUT_HDMI) 2324 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); 2325 else if (type == INTEL_OUTPUT_EDP) 2326 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); 2327 else 2328 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); 2329 2330 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 2331 return; 2332 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 2333 level = n_entries - 1; 2334 2335 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 2336 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2337 val &= ~SCALING_MODE_SEL_MASK; 2338 val |= SCALING_MODE_SEL(2); 2339 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2340 2341 /* Program PORT_TX_DW2 */ 2342 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 2343 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2344 RCOMP_SCALAR_MASK); 2345 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2346 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2347 /* Rcomp scalar is fixed as 0x98 for every table entry */ 2348 val |= RCOMP_SCALAR(0x98); 2349 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 2350 2351 /* Program PORT_TX_DW4 */ 2352 /* We cannot write to GRP. It would overrite individual loadgen */ 2353 for (ln = 0; ln < 4; ln++) { 2354 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2355 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2356 CURSOR_COEFF_MASK); 2357 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2358 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2359 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2360 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2361 } 2362 2363 /* Program PORT_TX_DW5 */ 2364 /* All DW5 values are fixed for every table entry */ 2365 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2366 val &= ~RTERM_SELECT_MASK; 2367 val |= RTERM_SELECT(6); 2368 val |= TAP3_DISABLE; 2369 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2370 2371 /* Program PORT_TX_DW7 */ 2372 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 2373 val &= ~N_SCALAR_MASK; 2374 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2375 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 2376} 2377 2378static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 2379 int level, enum intel_output_type type) 2380{ 2381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2382 enum port port = encoder->port; 2383 int width, rate, ln; 2384 u32 val; 2385 2386 if (type == INTEL_OUTPUT_HDMI) { 2387 width = 4; 2388 rate = 0; /* Rate is always < than 6GHz for HDMI */ 2389 } else { 2390 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2391 2392 width = intel_dp->lane_count; 2393 rate = intel_dp->link_rate; 2394 } 2395 2396 /* 2397 * 1. If port type is eDP or DP, 2398 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2399 * else clear to 0b. 2400 */ 2401 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 2402 if (type != INTEL_OUTPUT_HDMI) 2403 val |= COMMON_KEEPER_EN; 2404 else 2405 val &= ~COMMON_KEEPER_EN; 2406 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 2407 2408 /* 2. Program loadgen select */ 2409 /* 2410 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2411 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2412 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2413 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2414 */ 2415 for (ln = 0; ln <= 3; ln++) { 2416 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 2417 val &= ~LOADGEN_SELECT; 2418 2419 if ((rate <= 600000 && width == 4 && ln >= 1) || 2420 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2421 val |= LOADGEN_SELECT; 2422 } 2423 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 2424 } 2425 2426 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2427 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 2428 val |= SUS_CLOCK_CONFIG; 2429 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 2430 2431 /* 4. Clear training enable to change swing values */ 2432 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2433 val &= ~TX_TRAINING_EN; 2434 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2435 2436 /* 5. Program swing and de-emphasis */ 2437 cnl_ddi_vswing_program(encoder, level, type); 2438 2439 /* 6. Set training enable to trigger update */ 2440 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 2441 val |= TX_TRAINING_EN; 2442 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 2443} 2444 2445static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 2446 u32 level, int type, int rate) 2447{ 2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2449 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2450 const struct cnl_ddi_buf_trans *ddi_translations = NULL; 2451 u32 n_entries, val; 2452 int ln; 2453 2454 if (INTEL_GEN(dev_priv) >= 12) 2455 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate, 2456 &n_entries); 2457 else if (IS_ELKHARTLAKE(dev_priv)) 2458 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate, 2459 &n_entries); 2460 else 2461 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate, 2462 &n_entries); 2463 if (!ddi_translations) 2464 return; 2465 2466 if (level >= n_entries) { 2467 drm_dbg_kms(&dev_priv->drm, 2468 "DDI translation not found for level %d. Using %d instead.", 2469 level, n_entries - 1); 2470 level = n_entries - 1; 2471 } 2472 2473 if (type == INTEL_OUTPUT_EDP) { 2474 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2475 2476 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 2477 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 2478 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 2479 intel_dp->hobl_active ? val : 0); 2480 } 2481 2482 /* Set PORT_TX_DW5 */ 2483 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2484 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 2485 TAP2_DISABLE | TAP3_DISABLE); 2486 val |= SCALING_MODE_SEL(0x2); 2487 val |= RTERM_SELECT(0x6); 2488 val |= TAP3_DISABLE; 2489 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2490 2491 /* Program PORT_TX_DW2 */ 2492 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 2493 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 2494 RCOMP_SCALAR_MASK); 2495 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); 2496 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); 2497 /* Program Rcomp scalar for every table entry */ 2498 val |= RCOMP_SCALAR(0x98); 2499 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 2500 2501 /* Program PORT_TX_DW4 */ 2502 /* We cannot write to GRP. It would overwrite individual loadgen. */ 2503 for (ln = 0; ln <= 3; ln++) { 2504 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2505 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 2506 CURSOR_COEFF_MASK); 2507 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); 2508 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); 2509 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); 2510 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2511 } 2512 2513 /* Program PORT_TX_DW7 */ 2514 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 2515 val &= ~N_SCALAR_MASK; 2516 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); 2517 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 2518} 2519 2520static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2521 u32 level, 2522 enum intel_output_type type) 2523{ 2524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2525 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2526 int width = 0; 2527 int rate = 0; 2528 u32 val; 2529 int ln = 0; 2530 2531 if (type == INTEL_OUTPUT_HDMI) { 2532 width = 4; 2533 /* Rate is always < than 6GHz for HDMI */ 2534 } else { 2535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2536 2537 width = intel_dp->lane_count; 2538 rate = intel_dp->link_rate; 2539 } 2540 2541 /* 2542 * 1. If port type is eDP or DP, 2543 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 2544 * else clear to 0b. 2545 */ 2546 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 2547 if (type == INTEL_OUTPUT_HDMI) 2548 val &= ~COMMON_KEEPER_EN; 2549 else 2550 val |= COMMON_KEEPER_EN; 2551 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 2552 2553 /* 2. Program loadgen select */ 2554 /* 2555 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 2556 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 2557 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 2558 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 2559 */ 2560 for (ln = 0; ln <= 3; ln++) { 2561 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 2562 val &= ~LOADGEN_SELECT; 2563 2564 if ((rate <= 600000 && width == 4 && ln >= 1) || 2565 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 2566 val |= LOADGEN_SELECT; 2567 } 2568 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 2569 } 2570 2571 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 2572 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 2573 val |= SUS_CLOCK_CONFIG; 2574 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 2575 2576 /* 4. Clear training enable to change swing values */ 2577 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2578 val &= ~TX_TRAINING_EN; 2579 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2580 2581 /* 5. Program swing and de-emphasis */ 2582 icl_ddi_combo_vswing_program(encoder, level, type, rate); 2583 2584 /* 6. Set training enable to trigger update */ 2585 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 2586 val |= TX_TRAINING_EN; 2587 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 2588} 2589 2590static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 2591 int link_clock, u32 level, 2592 enum intel_output_type type) 2593{ 2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2595 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2596 const struct icl_mg_phy_ddi_buf_trans *ddi_translations; 2597 u32 n_entries, val; 2598 int ln, rate = 0; 2599 2600 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 2601 return; 2602 2603 if (type != INTEL_OUTPUT_HDMI) { 2604 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2605 2606 rate = intel_dp->link_rate; 2607 } 2608 2609 ddi_translations = icl_get_mg_buf_trans(encoder, type, rate, 2610 &n_entries); 2611 if (level >= n_entries) { 2612 drm_dbg_kms(&dev_priv->drm, 2613 "DDI translation not found for level %d. Using %d instead.", 2614 level, n_entries - 1); 2615 level = n_entries - 1; 2616 } 2617 2618 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 2619 for (ln = 0; ln < 2; ln++) { 2620 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 2621 val &= ~CRI_USE_FS32; 2622 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 2623 2624 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 2625 val &= ~CRI_USE_FS32; 2626 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 2627 } 2628 2629 /* Program MG_TX_SWINGCTRL with values from vswing table */ 2630 for (ln = 0; ln < 2; ln++) { 2631 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 2632 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2633 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2634 ddi_translations[level].cri_txdeemph_override_17_12); 2635 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 2636 2637 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 2638 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 2639 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 2640 ddi_translations[level].cri_txdeemph_override_17_12); 2641 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 2642 } 2643 2644 /* Program MG_TX_DRVCTRL with values from vswing table */ 2645 for (ln = 0; ln < 2; ln++) { 2646 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 2647 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2648 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2649 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2650 ddi_translations[level].cri_txdeemph_override_5_0) | 2651 CRI_TXDEEMPH_OVERRIDE_11_6( 2652 ddi_translations[level].cri_txdeemph_override_11_6) | 2653 CRI_TXDEEMPH_OVERRIDE_EN; 2654 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 2655 2656 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 2657 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 2658 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 2659 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 2660 ddi_translations[level].cri_txdeemph_override_5_0) | 2661 CRI_TXDEEMPH_OVERRIDE_11_6( 2662 ddi_translations[level].cri_txdeemph_override_11_6) | 2663 CRI_TXDEEMPH_OVERRIDE_EN; 2664 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 2665 2666 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 2667 } 2668 2669 /* 2670 * Program MG_CLKHUB<LN, port being used> with value from frequency table 2671 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 2672 * values from table for which TX1 and TX2 enabled. 2673 */ 2674 for (ln = 0; ln < 2; ln++) { 2675 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 2676 if (link_clock < 300000) 2677 val |= CFG_LOW_RATE_LKREN_EN; 2678 else 2679 val &= ~CFG_LOW_RATE_LKREN_EN; 2680 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 2681 } 2682 2683 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 2684 for (ln = 0; ln < 2; ln++) { 2685 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 2686 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2687 if (link_clock <= 500000) { 2688 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2689 } else { 2690 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2691 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2692 } 2693 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 2694 2695 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 2696 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 2697 if (link_clock <= 500000) { 2698 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 2699 } else { 2700 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 2701 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 2702 } 2703 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 2704 } 2705 2706 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 2707 for (ln = 0; ln < 2; ln++) { 2708 val = intel_de_read(dev_priv, 2709 MG_TX1_PISO_READLOAD(ln, tc_port)); 2710 val |= CRI_CALCINIT; 2711 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 2712 val); 2713 2714 val = intel_de_read(dev_priv, 2715 MG_TX2_PISO_READLOAD(ln, tc_port)); 2716 val |= CRI_CALCINIT; 2717 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 2718 val); 2719 } 2720} 2721 2722static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 2723 int link_clock, 2724 u32 level, 2725 enum intel_output_type type) 2726{ 2727 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2728 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2729 2730 if (intel_phy_is_combo(dev_priv, phy)) 2731 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2732 else 2733 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level, 2734 type); 2735} 2736 2737static void 2738tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, 2739 u32 level, enum intel_output_type type) 2740{ 2741 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2742 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 2743 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations; 2744 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val; 2745 int rate = 0; 2746 2747 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 2748 return; 2749 2750 if (type != INTEL_OUTPUT_HDMI) { 2751 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2752 2753 rate = intel_dp->link_rate; 2754 } 2755 2756 ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate, 2757 &n_entries); 2758 2759 if (level >= n_entries) 2760 level = n_entries - 1; 2761 2762 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 2763 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 2764 DKL_TX_VSWING_CONTROL_MASK); 2765 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control); 2766 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control); 2767 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); 2768 2769 for (ln = 0; ln < 2; ln++) { 2770 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2771 HIP_INDEX_VAL(tc_port, ln)); 2772 2773 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 2774 2775 /* All the registers are RMW */ 2776 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 2777 val &= ~dpcnt_mask; 2778 val |= dpcnt_val; 2779 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 2780 2781 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 2782 val &= ~dpcnt_mask; 2783 val |= dpcnt_val; 2784 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 2785 2786 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 2787 val &= ~DKL_TX_DP20BITMODE; 2788 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 2789 } 2790} 2791 2792static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 2793 int link_clock, 2794 u32 level, 2795 enum intel_output_type type) 2796{ 2797 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2798 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2799 2800 if (intel_phy_is_combo(dev_priv, phy)) 2801 icl_combo_phy_ddi_vswing_sequence(encoder, level, type); 2802 else 2803 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type); 2804} 2805 2806static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels) 2807{ 2808 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2809 int i; 2810 2811 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 2812 if (index_to_dp_signal_levels[i] == signal_levels) 2813 return i; 2814 } 2815 2816 drm_WARN(&i915->drm, 1, 2817 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2818 signal_levels); 2819 2820 return 0; 2821} 2822 2823static u32 intel_ddi_dp_level(struct intel_dp *intel_dp) 2824{ 2825 u8 train_set = intel_dp->train_set[0]; 2826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2827 DP_TRAIN_PRE_EMPHASIS_MASK); 2828 2829 return translate_signal_level(intel_dp, signal_levels); 2830} 2831 2832static void 2833tgl_set_signal_levels(struct intel_dp *intel_dp) 2834{ 2835 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2836 int level = intel_ddi_dp_level(intel_dp); 2837 2838 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2839 level, encoder->type); 2840} 2841 2842static void 2843icl_set_signal_levels(struct intel_dp *intel_dp) 2844{ 2845 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2846 int level = intel_ddi_dp_level(intel_dp); 2847 2848 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate, 2849 level, encoder->type); 2850} 2851 2852static void 2853cnl_set_signal_levels(struct intel_dp *intel_dp) 2854{ 2855 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2856 int level = intel_ddi_dp_level(intel_dp); 2857 2858 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 2859} 2860 2861static void 2862bxt_set_signal_levels(struct intel_dp *intel_dp) 2863{ 2864 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2865 int level = intel_ddi_dp_level(intel_dp); 2866 2867 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 2868} 2869 2870static void 2871hsw_set_signal_levels(struct intel_dp *intel_dp) 2872{ 2873 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 2874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2875 int level = intel_ddi_dp_level(intel_dp); 2876 enum port port = encoder->port; 2877 u32 signal_levels; 2878 2879 signal_levels = DDI_BUF_TRANS_SELECT(level); 2880 2881 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 2882 signal_levels); 2883 2884 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 2885 intel_dp->DP |= signal_levels; 2886 2887 if (IS_GEN9_BC(dev_priv)) 2888 skl_ddi_set_iboost(encoder, level, encoder->type); 2889 2890 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 2891 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 2892} 2893 2894static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv, 2895 enum phy phy) 2896{ 2897 if (IS_ROCKETLAKE(dev_priv)) { 2898 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2899 } else if (intel_phy_is_combo(dev_priv, phy)) { 2900 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 2901 } else if (intel_phy_is_tc(dev_priv, phy)) { 2902 enum tc_port tc_port = intel_port_to_tc(dev_priv, 2903 (enum port)phy); 2904 2905 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port); 2906 } 2907 2908 return 0; 2909} 2910 2911static void icl_map_plls_to_ports(struct intel_encoder *encoder, 2912 const struct intel_crtc_state *crtc_state) 2913{ 2914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2915 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2916 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2917 u32 val; 2918 2919 mutex_lock(&dev_priv->dpll.lock); 2920 2921 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2922 drm_WARN_ON(&dev_priv->drm, 2923 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); 2924 2925 if (intel_phy_is_combo(dev_priv, phy)) { 2926 u32 mask, sel; 2927 2928 if (IS_ROCKETLAKE(dev_priv)) { 2929 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2930 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2931 } else { 2932 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 2933 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 2934 } 2935 2936 /* 2937 * Even though this register references DDIs, note that we 2938 * want to pass the PHY rather than the port (DDI). For 2939 * ICL, port=phy in all cases so it doesn't matter, but for 2940 * EHL the bspec notes the following: 2941 * 2942 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA 2943 * Clock Select chooses the PLL for both DDIA and DDID and 2944 * drives port A in all cases." 2945 */ 2946 val &= ~mask; 2947 val |= sel; 2948 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2949 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 2950 } 2951 2952 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2953 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2954 2955 mutex_unlock(&dev_priv->dpll.lock); 2956} 2957 2958static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) 2959{ 2960 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2961 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2962 u32 val; 2963 2964 mutex_lock(&dev_priv->dpll.lock); 2965 2966 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2967 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2968 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 2969 2970 mutex_unlock(&dev_priv->dpll.lock); 2971} 2972 2973static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, 2974 u32 port_mask, bool ddi_clk_needed) 2975{ 2976 enum port port; 2977 u32 val; 2978 2979 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 2980 for_each_port_masked(port, port_mask) { 2981 enum phy phy = intel_port_to_phy(dev_priv, port); 2982 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, 2983 phy); 2984 2985 if (ddi_clk_needed == !ddi_clk_off) 2986 continue; 2987 2988 /* 2989 * Punt on the case now where clock is gated, but it would 2990 * be needed by the port. Something else is really broken then. 2991 */ 2992 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) 2993 continue; 2994 2995 drm_notice(&dev_priv->drm, 2996 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2997 phy_name(phy)); 2998 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); 2999 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 3000 } 3001} 3002 3003void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 3004{ 3005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3006 u32 port_mask; 3007 bool ddi_clk_needed; 3008 3009 /* 3010 * In case of DP MST, we sanitize the primary encoder only, not the 3011 * virtual ones. 3012 */ 3013 if (encoder->type == INTEL_OUTPUT_DP_MST) 3014 return; 3015 3016 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 3017 u8 pipe_mask; 3018 bool is_mst; 3019 3020 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 3021 /* 3022 * In the unlikely case that BIOS enables DP in MST mode, just 3023 * warn since our MST HW readout is incomplete. 3024 */ 3025 if (drm_WARN_ON(&dev_priv->drm, is_mst)) 3026 return; 3027 } 3028 3029 port_mask = BIT(encoder->port); 3030 ddi_clk_needed = encoder->base.crtc; 3031 3032 if (encoder->type == INTEL_OUTPUT_DSI) { 3033 struct intel_encoder *other_encoder; 3034 3035 port_mask = intel_dsi_encoder_ports(encoder); 3036 /* 3037 * Sanity check that we haven't incorrectly registered another 3038 * encoder using any of the ports of this DSI encoder. 3039 */ 3040 for_each_intel_encoder(&dev_priv->drm, other_encoder) { 3041 if (other_encoder == encoder) 3042 continue; 3043 3044 if (drm_WARN_ON(&dev_priv->drm, 3045 port_mask & BIT(other_encoder->port))) 3046 return; 3047 } 3048 /* 3049 * For DSI we keep the ddi clocks gated 3050 * except during enable/disable sequence. 3051 */ 3052 ddi_clk_needed = false; 3053 } 3054 3055 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed); 3056} 3057 3058static void intel_ddi_clk_select(struct intel_encoder *encoder, 3059 const struct intel_crtc_state *crtc_state) 3060{ 3061 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3062 enum port port = encoder->port; 3063 enum phy phy = intel_port_to_phy(dev_priv, port); 3064 u32 val; 3065 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 3066 3067 if (drm_WARN_ON(&dev_priv->drm, !pll)) 3068 return; 3069 3070 mutex_lock(&dev_priv->dpll.lock); 3071 3072 if (INTEL_GEN(dev_priv) >= 11) { 3073 if (!intel_phy_is_combo(dev_priv, phy)) 3074 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3075 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 3076 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) 3077 /* 3078 * MG does not exist but the programming is required 3079 * to ungate DDIC and DDID 3080 */ 3081 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3082 DDI_CLK_SEL_MG); 3083 } else if (IS_CANNONLAKE(dev_priv)) { 3084 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ 3085 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3086 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); 3087 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); 3088 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3089 3090 /* 3091 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. 3092 * This step and the step before must be done with separate 3093 * register writes. 3094 */ 3095 val = intel_de_read(dev_priv, DPCLKA_CFGCR0); 3096 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); 3097 intel_de_write(dev_priv, DPCLKA_CFGCR0, val); 3098 } else if (IS_GEN9_BC(dev_priv)) { 3099 /* DDI -> PLL mapping */ 3100 val = intel_de_read(dev_priv, DPLL_CTRL2); 3101 3102 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 3103 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 3104 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 3105 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 3106 3107 intel_de_write(dev_priv, DPLL_CTRL2, val); 3108 3109 } else if (INTEL_GEN(dev_priv) < 9) { 3110 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3111 hsw_pll_to_ddi_pll_sel(pll)); 3112 } 3113 3114 mutex_unlock(&dev_priv->dpll.lock); 3115} 3116 3117static void intel_ddi_clk_disable(struct intel_encoder *encoder) 3118{ 3119 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3120 enum port port = encoder->port; 3121 enum phy phy = intel_port_to_phy(dev_priv, port); 3122 3123 if (INTEL_GEN(dev_priv) >= 11) { 3124 if (!intel_phy_is_combo(dev_priv, phy) || 3125 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) 3126 intel_de_write(dev_priv, DDI_CLK_SEL(port), 3127 DDI_CLK_SEL_NONE); 3128 } else if (IS_CANNONLAKE(dev_priv)) { 3129 intel_de_write(dev_priv, DPCLKA_CFGCR0, 3130 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 3131 } else if (IS_GEN9_BC(dev_priv)) { 3132 intel_de_write(dev_priv, DPLL_CTRL2, 3133 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); 3134 } else if (INTEL_GEN(dev_priv) < 9) { 3135 intel_de_write(dev_priv, PORT_CLK_SEL(port), 3136 PORT_CLK_SEL_NONE); 3137 } 3138} 3139 3140static void 3141icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 3142 const struct intel_crtc_state *crtc_state) 3143{ 3144 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 3145 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 3146 u32 ln0, ln1, pin_assignment; 3147 u8 width; 3148 3149 if (dig_port->tc_mode == TC_PORT_TBT_ALT) 3150 return; 3151 3152 if (INTEL_GEN(dev_priv) >= 12) { 3153 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3154 HIP_INDEX_VAL(tc_port, 0x0)); 3155 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3156 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3157 HIP_INDEX_VAL(tc_port, 0x1)); 3158 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 3159 } else { 3160 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 3161 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 3162 } 3163 3164 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3165 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 3166 3167 /* DPPATC */ 3168 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 3169 width = crtc_state->lane_count; 3170 3171 switch (pin_assignment) { 3172 case 0x0: 3173 drm_WARN_ON(&dev_priv->drm, 3174 dig_port->tc_mode != TC_PORT_LEGACY); 3175 if (width == 1) { 3176 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3177 } else { 3178 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3179 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3180 } 3181 break; 3182 case 0x1: 3183 if (width == 4) { 3184 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3185 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3186 } 3187 break; 3188 case 0x2: 3189 if (width == 2) { 3190 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3191 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3192 } 3193 break; 3194 case 0x3: 3195 case 0x5: 3196 if (width == 1) { 3197 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3198 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3199 } else { 3200 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3201 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3202 } 3203 break; 3204 case 0x4: 3205 case 0x6: 3206 if (width == 1) { 3207 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 3208 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 3209 } else { 3210 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 3211 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 3212 } 3213 break; 3214 default: 3215 MISSING_CASE(pin_assignment); 3216 } 3217 3218 if (INTEL_GEN(dev_priv) >= 12) { 3219 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3220 HIP_INDEX_VAL(tc_port, 0x0)); 3221 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 3222 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 3223 HIP_INDEX_VAL(tc_port, 0x1)); 3224 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 3225 } else { 3226 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 3227 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 3228 } 3229} 3230 3231static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 3232 const struct intel_crtc_state *crtc_state) 3233{ 3234 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3235 3236 if (!crtc_state->fec_enable) 3237 return; 3238 3239 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 3240 drm_dbg_kms(&i915->drm, 3241 "Failed to set FEC_READY in the sink\n"); 3242} 3243 3244static void intel_ddi_enable_fec(struct intel_encoder *encoder, 3245 const struct intel_crtc_state *crtc_state) 3246{ 3247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3248 struct intel_dp *intel_dp; 3249 u32 val; 3250 3251 if (!crtc_state->fec_enable) 3252 return; 3253 3254 intel_dp = enc_to_intel_dp(encoder); 3255 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3256 val |= DP_TP_CTL_FEC_ENABLE; 3257 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3258 3259 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 3260 DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) 3261 drm_err(&dev_priv->drm, 3262 "Timed out waiting for FEC Enable Status\n"); 3263} 3264 3265static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 3266 const struct intel_crtc_state *crtc_state) 3267{ 3268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3269 struct intel_dp *intel_dp; 3270 u32 val; 3271 3272 if (!crtc_state->fec_enable) 3273 return; 3274 3275 intel_dp = enc_to_intel_dp(encoder); 3276 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3277 val &= ~DP_TP_CTL_FEC_ENABLE; 3278 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3279 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3280} 3281 3282static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 3283 const struct intel_crtc_state *crtc_state) 3284{ 3285 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3286 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3287 enum phy phy = intel_port_to_phy(i915, encoder->port); 3288 3289 if (intel_phy_is_combo(i915, phy)) { 3290 bool lane_reversal = 3291 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 3292 3293 intel_combo_phy_power_up_lanes(i915, phy, false, 3294 crtc_state->lane_count, 3295 lane_reversal); 3296 } 3297} 3298 3299static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 3300 struct intel_encoder *encoder, 3301 const struct intel_crtc_state *crtc_state, 3302 const struct drm_connector_state *conn_state) 3303{ 3304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3306 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3307 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3308 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3309 int level = intel_ddi_dp_level(intel_dp); 3310 enum transcoder transcoder = crtc_state->cpu_transcoder; 3311 3312 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3313 crtc_state->lane_count, is_mst); 3314 3315 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 3316 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 3317 3318 /* 3319 * 1. Enable Power Wells 3320 * 3321 * This was handled at the beginning of intel_atomic_commit_tail(), 3322 * before we called down into this function. 3323 */ 3324 3325 /* 2. Enable Panel Power if PPS is required */ 3326 intel_edp_panel_on(intel_dp); 3327 3328 /* 3329 * 3. For non-TBT Type-C ports, set FIA lane count 3330 * (DFLEXDPSP.DPX4TXLATC) 3331 * 3332 * This was done before tgl_ddi_pre_enable_dp by 3333 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 3334 */ 3335 3336 /* 3337 * 4. Enable the port PLL. 3338 * 3339 * The PLL enabling itself was already done before this function by 3340 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 3341 * configure the PLL to port mapping here. 3342 */ 3343 intel_ddi_clk_select(encoder, crtc_state); 3344 3345 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 3346 if (!intel_phy_is_tc(dev_priv, phy) || 3347 dig_port->tc_mode != TC_PORT_TBT_ALT) 3348 intel_display_power_get(dev_priv, 3349 dig_port->ddi_io_power_domain); 3350 3351 /* 6. Program DP_MODE */ 3352 icl_program_mg_dp_mode(dig_port, crtc_state); 3353 3354 /* 3355 * 7. The rest of the below are substeps under the bspec's "Enable and 3356 * Train Display Port" step. Note that steps that are specific to 3357 * MST will be handled by intel_mst_pre_enable_dp() before/after it 3358 * calls into this function. Also intel_mst_pre_enable_dp() only calls 3359 * us when active_mst_links==0, so any steps designated for "single 3360 * stream or multi-stream master transcoder" can just be performed 3361 * unconditionally here. 3362 */ 3363 3364 /* 3365 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 3366 * Transcoder. 3367 */ 3368 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3369 3370 /* 3371 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 3372 * Transport Select 3373 */ 3374 intel_ddi_config_transcoder_func(encoder, crtc_state); 3375 3376 /* 3377 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 3378 * selected 3379 * 3380 * This will be handled by the intel_dp_start_link_train() farther 3381 * down this function. 3382 */ 3383 3384 /* 7.e Configure voltage swing and related IO settings */ 3385 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level, 3386 encoder->type); 3387 3388 /* 3389 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 3390 * the used lanes of the DDI. 3391 */ 3392 intel_ddi_power_up_lanes(encoder, crtc_state); 3393 3394 /* 3395 * 7.g Configure and enable DDI_BUF_CTL 3396 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 3397 * after 500 us. 3398 * 3399 * We only configure what the register value will be here. Actual 3400 * enabling happens during link training farther down. 3401 */ 3402 intel_ddi_init_dp_buf_reg(encoder); 3403 3404 if (!is_mst) 3405 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3406 3407 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 3408 /* 3409 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 3410 * in the FEC_CONFIGURATION register to 1 before initiating link 3411 * training 3412 */ 3413 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3414 3415 /* 3416 * 7.i Follow DisplayPort specification training sequence (see notes for 3417 * failure handling) 3418 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 3419 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 3420 * (timeout after 800 us) 3421 */ 3422 intel_dp_start_link_train(intel_dp); 3423 3424 /* 7.k Set DP_TP_CTL link training to Normal */ 3425 if (!is_trans_port_sync_mode(crtc_state)) 3426 intel_dp_stop_link_train(intel_dp); 3427 3428 /* 7.l Configure and enable FEC if needed */ 3429 intel_ddi_enable_fec(encoder, crtc_state); 3430 intel_dsc_enable(encoder, crtc_state); 3431} 3432 3433static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 3434 struct intel_encoder *encoder, 3435 const struct intel_crtc_state *crtc_state, 3436 const struct drm_connector_state *conn_state) 3437{ 3438 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3440 enum port port = encoder->port; 3441 enum phy phy = intel_port_to_phy(dev_priv, port); 3442 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3443 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 3444 int level = intel_ddi_dp_level(intel_dp); 3445 3446 if (INTEL_GEN(dev_priv) < 11) 3447 drm_WARN_ON(&dev_priv->drm, 3448 is_mst && (port == PORT_A || port == PORT_E)); 3449 else 3450 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 3451 3452 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, 3453 crtc_state->lane_count, is_mst); 3454 3455 intel_edp_panel_on(intel_dp); 3456 3457 intel_ddi_clk_select(encoder, crtc_state); 3458 3459 if (!intel_phy_is_tc(dev_priv, phy) || 3460 dig_port->tc_mode != TC_PORT_TBT_ALT) 3461 intel_display_power_get(dev_priv, 3462 dig_port->ddi_io_power_domain); 3463 3464 icl_program_mg_dp_mode(dig_port, crtc_state); 3465 3466 if (INTEL_GEN(dev_priv) >= 11) 3467 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3468 level, encoder->type); 3469 else if (IS_CANNONLAKE(dev_priv)) 3470 cnl_ddi_vswing_sequence(encoder, level, encoder->type); 3471 else if (IS_GEN9_LP(dev_priv)) 3472 bxt_ddi_vswing_sequence(encoder, level, encoder->type); 3473 else 3474 intel_prepare_dp_ddi_buffers(encoder, crtc_state); 3475 3476 intel_ddi_power_up_lanes(encoder, crtc_state); 3477 3478 intel_ddi_init_dp_buf_reg(encoder); 3479 if (!is_mst) 3480 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 3481 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 3482 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 3483 true); 3484 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 3485 intel_dp_start_link_train(intel_dp); 3486 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) && 3487 !is_trans_port_sync_mode(crtc_state)) 3488 intel_dp_stop_link_train(intel_dp); 3489 3490 intel_ddi_enable_fec(encoder, crtc_state); 3491 3492 if (!is_mst) 3493 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3494 3495 intel_dsc_enable(encoder, crtc_state); 3496} 3497 3498static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 3499 struct intel_encoder *encoder, 3500 const struct intel_crtc_state *crtc_state, 3501 const struct drm_connector_state *conn_state) 3502{ 3503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3504 3505 if (INTEL_GEN(dev_priv) >= 12) 3506 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3507 else 3508 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 3509 3510 /* MST will call a setting of MSA after an allocating of Virtual Channel 3511 * from MST encoder pre_enable callback. 3512 */ 3513 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3514 intel_ddi_set_dp_msa(crtc_state, conn_state); 3515 3516 intel_dp_set_m_n(crtc_state, M1_N1); 3517 } 3518} 3519 3520static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 3521 struct intel_encoder *encoder, 3522 const struct intel_crtc_state *crtc_state, 3523 const struct drm_connector_state *conn_state) 3524{ 3525 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3526 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3528 int level = intel_ddi_hdmi_level(encoder); 3529 3530 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3531 intel_ddi_clk_select(encoder, crtc_state); 3532 3533 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); 3534 3535 icl_program_mg_dp_mode(dig_port, crtc_state); 3536 3537 if (INTEL_GEN(dev_priv) >= 12) 3538 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3539 level, INTEL_OUTPUT_HDMI); 3540 else if (INTEL_GEN(dev_priv) == 11) 3541 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock, 3542 level, INTEL_OUTPUT_HDMI); 3543 else if (IS_CANNONLAKE(dev_priv)) 3544 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3545 else if (IS_GEN9_LP(dev_priv)) 3546 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); 3547 else 3548 intel_prepare_hdmi_ddi_buffers(encoder, level); 3549 3550 if (IS_GEN9_BC(dev_priv)) 3551 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); 3552 3553 intel_ddi_enable_pipe_clock(encoder, crtc_state); 3554 3555 dig_port->set_infoframes(encoder, 3556 crtc_state->has_infoframe, 3557 crtc_state, conn_state); 3558} 3559 3560static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3561 struct intel_encoder *encoder, 3562 const struct intel_crtc_state *crtc_state, 3563 const struct drm_connector_state *conn_state) 3564{ 3565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3567 enum pipe pipe = crtc->pipe; 3568 3569 /* 3570 * When called from DP MST code: 3571 * - conn_state will be NULL 3572 * - encoder will be the main encoder (ie. mst->primary) 3573 * - the main connector associated with this port 3574 * won't be active or linked to a crtc 3575 * - crtc_state will be the state of the first stream to 3576 * be activated on this port, and it may not be the same 3577 * stream that will be deactivated last, but each stream 3578 * should have a state that is identical when it comes to 3579 * the DP link parameteres 3580 */ 3581 3582 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 3583 3584 if (INTEL_GEN(dev_priv) >= 11) 3585 icl_map_plls_to_ports(encoder, crtc_state); 3586 3587 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 3588 3589 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3590 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3591 conn_state); 3592 } else { 3593 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3594 3595 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3596 conn_state); 3597 3598 /* FIXME precompute everything properly */ 3599 /* FIXME how do we turn infoframes off again? */ 3600 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3601 dig_port->set_infoframes(encoder, 3602 crtc_state->has_infoframe, 3603 crtc_state, conn_state); 3604 } 3605} 3606 3607static void intel_disable_ddi_buf(struct intel_encoder *encoder, 3608 const struct intel_crtc_state *crtc_state) 3609{ 3610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3611 enum port port = encoder->port; 3612 bool wait = false; 3613 u32 val; 3614 3615 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3616 if (val & DDI_BUF_CTL_ENABLE) { 3617 val &= ~DDI_BUF_CTL_ENABLE; 3618 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 3619 wait = true; 3620 } 3621 3622 if (intel_crtc_has_dp_encoder(crtc_state)) { 3623 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3624 3625 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 3626 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3627 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 3628 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 3629 } 3630 3631 /* Disable FEC in DP Sink */ 3632 intel_ddi_disable_fec_state(encoder, crtc_state); 3633 3634 if (wait) 3635 intel_wait_ddi_buf_idle(dev_priv, port); 3636} 3637 3638static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3639 struct intel_encoder *encoder, 3640 const struct intel_crtc_state *old_crtc_state, 3641 const struct drm_connector_state *old_conn_state) 3642{ 3643 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3644 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3645 struct intel_dp *intel_dp = &dig_port->dp; 3646 bool is_mst = intel_crtc_has_type(old_crtc_state, 3647 INTEL_OUTPUT_DP_MST); 3648 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3649 3650 if (!is_mst) 3651 intel_dp_set_infoframes(encoder, false, 3652 old_crtc_state, old_conn_state); 3653 3654 /* 3655 * Power down sink before disabling the port, otherwise we end 3656 * up getting interrupts from the sink on detecting link loss. 3657 */ 3658 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3659 3660 if (INTEL_GEN(dev_priv) >= 12) { 3661 if (is_mst) { 3662 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3663 u32 val; 3664 3665 val = intel_de_read(dev_priv, 3666 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3667 val &= ~(TGL_TRANS_DDI_PORT_MASK | 3668 TRANS_DDI_MODE_SELECT_MASK); 3669 intel_de_write(dev_priv, 3670 TRANS_DDI_FUNC_CTL(cpu_transcoder), 3671 val); 3672 } 3673 } else { 3674 if (!is_mst) 3675 intel_ddi_disable_pipe_clock(old_crtc_state); 3676 } 3677 3678 intel_disable_ddi_buf(encoder, old_crtc_state); 3679 3680 /* 3681 * From TGL spec: "If single stream or multi-stream master transcoder: 3682 * Configure Transcoder Clock select to direct no clock to the 3683 * transcoder" 3684 */ 3685 if (INTEL_GEN(dev_priv) >= 12) 3686 intel_ddi_disable_pipe_clock(old_crtc_state); 3687 3688 intel_edp_panel_vdd_on(intel_dp); 3689 intel_edp_panel_off(intel_dp); 3690 3691 if (!intel_phy_is_tc(dev_priv, phy) || 3692 dig_port->tc_mode != TC_PORT_TBT_ALT) 3693 intel_display_power_put_unchecked(dev_priv, 3694 dig_port->ddi_io_power_domain); 3695 3696 intel_ddi_clk_disable(encoder); 3697} 3698 3699static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3700 struct intel_encoder *encoder, 3701 const struct intel_crtc_state *old_crtc_state, 3702 const struct drm_connector_state *old_conn_state) 3703{ 3704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3705 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3706 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3707 3708 dig_port->set_infoframes(encoder, false, 3709 old_crtc_state, old_conn_state); 3710 3711 intel_ddi_disable_pipe_clock(old_crtc_state); 3712 3713 intel_disable_ddi_buf(encoder, old_crtc_state); 3714 3715 intel_display_power_put_unchecked(dev_priv, 3716 dig_port->ddi_io_power_domain); 3717 3718 intel_ddi_clk_disable(encoder); 3719 3720 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3721} 3722 3723static void intel_ddi_post_disable(struct intel_atomic_state *state, 3724 struct intel_encoder *encoder, 3725 const struct intel_crtc_state *old_crtc_state, 3726 const struct drm_connector_state *old_conn_state) 3727{ 3728 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3729 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3730 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3731 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3732 3733 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 3734 intel_crtc_vblank_off(old_crtc_state); 3735 3736 intel_disable_pipe(old_crtc_state); 3737 3738 intel_ddi_disable_transcoder_func(old_crtc_state); 3739 3740 intel_dsc_disable(old_crtc_state); 3741 3742 if (INTEL_GEN(dev_priv) >= 9) 3743 skl_scaler_disable(old_crtc_state); 3744 else 3745 ilk_pfit_disable(old_crtc_state); 3746 } 3747 3748 /* 3749 * When called from DP MST code: 3750 * - old_conn_state will be NULL 3751 * - encoder will be the main encoder (ie. mst->primary) 3752 * - the main connector associated with this port 3753 * won't be active or linked to a crtc 3754 * - old_crtc_state will be the state of the last stream to 3755 * be deactivated on this port, and it may not be the same 3756 * stream that was activated last, but each stream 3757 * should have a state that is identical when it comes to 3758 * the DP link parameteres 3759 */ 3760 3761 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3762 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3763 old_conn_state); 3764 else 3765 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3766 old_conn_state); 3767 3768 if (INTEL_GEN(dev_priv) >= 11) 3769 icl_unmap_plls_to_ports(encoder); 3770 3771 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 3772 intel_display_power_put_unchecked(dev_priv, 3773 intel_ddi_main_link_aux_domain(dig_port)); 3774 3775 if (is_tc_port) 3776 intel_tc_port_put_link(dig_port); 3777} 3778 3779void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 3780 struct intel_encoder *encoder, 3781 const struct intel_crtc_state *old_crtc_state, 3782 const struct drm_connector_state *old_conn_state) 3783{ 3784 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3785 u32 val; 3786 3787 /* 3788 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 3789 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 3790 * step 13 is the correct place for it. Step 18 is where it was 3791 * originally before the BUN. 3792 */ 3793 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3794 val &= ~FDI_RX_ENABLE; 3795 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3796 3797 intel_disable_ddi_buf(encoder, old_crtc_state); 3798 intel_ddi_clk_disable(encoder); 3799 3800 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 3801 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3802 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3803 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 3804 3805 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3806 val &= ~FDI_PCDCLK; 3807 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3808 3809 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 3810 val &= ~FDI_RX_PLL_ENABLE; 3811 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3812} 3813 3814static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3815 struct intel_encoder *encoder, 3816 const struct intel_crtc_state *crtc_state) 3817{ 3818 const struct drm_connector_state *conn_state; 3819 struct drm_connector *conn; 3820 int i; 3821 3822 if (!crtc_state->sync_mode_slaves_mask) 3823 return; 3824 3825 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3826 struct intel_encoder *slave_encoder = 3827 to_intel_encoder(conn_state->best_encoder); 3828 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3829 const struct intel_crtc_state *slave_crtc_state; 3830 3831 if (!slave_crtc) 3832 continue; 3833 3834 slave_crtc_state = 3835 intel_atomic_get_new_crtc_state(state, slave_crtc); 3836 3837 if (slave_crtc_state->master_transcoder != 3838 crtc_state->cpu_transcoder) 3839 continue; 3840 3841 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder)); 3842 } 3843 3844 usleep_range(200, 400); 3845 3846 intel_dp_stop_link_train(enc_to_intel_dp(encoder)); 3847} 3848 3849static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3850 struct intel_encoder *encoder, 3851 const struct intel_crtc_state *crtc_state, 3852 const struct drm_connector_state *conn_state) 3853{ 3854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3855 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3856 enum port port = encoder->port; 3857 3858 if (port == PORT_A && INTEL_GEN(dev_priv) < 9) 3859 intel_dp_stop_link_train(intel_dp); 3860 3861 intel_edp_backlight_on(crtc_state, conn_state); 3862 intel_psr_enable(intel_dp, crtc_state, conn_state); 3863 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3864 intel_edp_drrs_enable(intel_dp, crtc_state); 3865 3866 if (crtc_state->has_audio) 3867 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3868 3869 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3870} 3871 3872static i915_reg_t 3873gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3874 enum port port) 3875{ 3876 static const enum transcoder trans[] = { 3877 [PORT_A] = TRANSCODER_EDP, 3878 [PORT_B] = TRANSCODER_A, 3879 [PORT_C] = TRANSCODER_B, 3880 [PORT_D] = TRANSCODER_C, 3881 [PORT_E] = TRANSCODER_A, 3882 }; 3883 3884 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); 3885 3886 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3887 port = PORT_A; 3888 3889 return CHICKEN_TRANS(trans[port]); 3890} 3891 3892static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3893 struct intel_encoder *encoder, 3894 const struct intel_crtc_state *crtc_state, 3895 const struct drm_connector_state *conn_state) 3896{ 3897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3898 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3899 struct drm_connector *connector = conn_state->connector; 3900 enum port port = encoder->port; 3901 3902 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3903 crtc_state->hdmi_high_tmds_clock_ratio, 3904 crtc_state->hdmi_scrambling)) 3905 drm_dbg_kms(&dev_priv->drm, 3906 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3907 connector->base.id, connector->name); 3908 3909 /* Display WA #1143: skl,kbl,cfl */ 3910 if (IS_GEN9_BC(dev_priv)) { 3911 /* 3912 * For some reason these chicken bits have been 3913 * stuffed into a transcoder register, event though 3914 * the bits affect a specific DDI port rather than 3915 * a specific transcoder. 3916 */ 3917 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3918 u32 val; 3919 3920 val = intel_de_read(dev_priv, reg); 3921 3922 if (port == PORT_E) 3923 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3924 DDIE_TRAINING_OVERRIDE_VALUE; 3925 else 3926 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3927 DDI_TRAINING_OVERRIDE_VALUE; 3928 3929 intel_de_write(dev_priv, reg, val); 3930 intel_de_posting_read(dev_priv, reg); 3931 3932 udelay(1); 3933 3934 if (port == PORT_E) 3935 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3936 DDIE_TRAINING_OVERRIDE_VALUE); 3937 else 3938 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3939 DDI_TRAINING_OVERRIDE_VALUE); 3940 3941 intel_de_write(dev_priv, reg, val); 3942 } 3943 3944 intel_ddi_power_up_lanes(encoder, crtc_state); 3945 3946 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3947 * are ignored so nothing special needs to be done besides 3948 * enabling the port. 3949 */ 3950 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3951 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3952 3953 if (crtc_state->has_audio) 3954 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3955} 3956 3957static void intel_enable_ddi(struct intel_atomic_state *state, 3958 struct intel_encoder *encoder, 3959 const struct intel_crtc_state *crtc_state, 3960 const struct drm_connector_state *conn_state) 3961{ 3962 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3963 3964 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3965 3966 intel_enable_pipe(crtc_state); 3967 3968 intel_crtc_vblank_on(crtc_state); 3969 3970 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3971 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3972 else 3973 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3974 3975 /* Enable hdcp if it's desired */ 3976 if (conn_state->content_protection == 3977 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3978 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3979 crtc_state->cpu_transcoder, 3980 (u8)conn_state->hdcp_content_type); 3981} 3982 3983static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3984 struct intel_encoder *encoder, 3985 const struct intel_crtc_state *old_crtc_state, 3986 const struct drm_connector_state *old_conn_state) 3987{ 3988 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3989 3990 intel_dp->link_trained = false; 3991 3992 if (old_crtc_state->has_audio) 3993 intel_audio_codec_disable(encoder, 3994 old_crtc_state, old_conn_state); 3995 3996 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3997 intel_psr_disable(intel_dp, old_crtc_state); 3998 intel_edp_backlight_off(old_conn_state); 3999 /* Disable the decompression in DP Sink */ 4000 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 4001 false); 4002} 4003 4004static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 4005 struct intel_encoder *encoder, 4006 const struct intel_crtc_state *old_crtc_state, 4007 const struct drm_connector_state *old_conn_state) 4008{ 4009 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4010 struct drm_connector *connector = old_conn_state->connector; 4011 4012 if (old_crtc_state->has_audio) 4013 intel_audio_codec_disable(encoder, 4014 old_crtc_state, old_conn_state); 4015 4016 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 4017 false, false)) 4018 drm_dbg_kms(&i915->drm, 4019 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 4020 connector->base.id, connector->name); 4021} 4022 4023static void intel_disable_ddi(struct intel_atomic_state *state, 4024 struct intel_encoder *encoder, 4025 const struct intel_crtc_state *old_crtc_state, 4026 const struct drm_connector_state *old_conn_state) 4027{ 4028 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 4029 4030 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 4031 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 4032 old_conn_state); 4033 else 4034 intel_disable_ddi_dp(state, encoder, old_crtc_state, 4035 old_conn_state); 4036} 4037 4038static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 4039 struct intel_encoder *encoder, 4040 const struct intel_crtc_state *crtc_state, 4041 const struct drm_connector_state *conn_state) 4042{ 4043 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4044 4045 intel_ddi_set_dp_msa(crtc_state, conn_state); 4046 4047 intel_psr_update(intel_dp, crtc_state, conn_state); 4048 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 4049 intel_edp_drrs_update(intel_dp, crtc_state); 4050 4051 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 4052} 4053 4054void intel_ddi_update_pipe(struct intel_atomic_state *state, 4055 struct intel_encoder *encoder, 4056 const struct intel_crtc_state *crtc_state, 4057 const struct drm_connector_state *conn_state) 4058{ 4059 4060 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 4061 !intel_encoder_is_mst(encoder)) 4062 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 4063 conn_state); 4064 4065 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 4066} 4067 4068static void 4069intel_ddi_update_prepare(struct intel_atomic_state *state, 4070 struct intel_encoder *encoder, 4071 struct intel_crtc *crtc) 4072{ 4073 struct intel_crtc_state *crtc_state = 4074 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 4075 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 4076 4077 drm_WARN_ON(state->base.dev, crtc && crtc->active); 4078 4079 intel_tc_port_get_link(enc_to_dig_port(encoder), 4080 required_lanes); 4081 if (crtc_state && crtc_state->hw.active) 4082 intel_update_active_dpll(state, crtc, encoder); 4083} 4084 4085static void 4086intel_ddi_update_complete(struct intel_atomic_state *state, 4087 struct intel_encoder *encoder, 4088 struct intel_crtc *crtc) 4089{ 4090 intel_tc_port_put_link(enc_to_dig_port(encoder)); 4091} 4092 4093static void 4094intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 4095 struct intel_encoder *encoder, 4096 const struct intel_crtc_state *crtc_state, 4097 const struct drm_connector_state *conn_state) 4098{ 4099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4100 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4101 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 4102 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 4103 4104 if (is_tc_port) 4105 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 4106 4107 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) 4108 intel_display_power_get(dev_priv, 4109 intel_ddi_main_link_aux_domain(dig_port)); 4110 4111 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 4112 /* 4113 * Program the lane count for static/dynamic connections on 4114 * Type-C ports. Skip this step for TBT. 4115 */ 4116 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 4117 else if (IS_GEN9_LP(dev_priv)) 4118 bxt_ddi_phy_set_lane_optim_mask(encoder, 4119 crtc_state->lane_lat_optim_mask); 4120} 4121 4122static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) 4123{ 4124 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4125 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4126 enum port port = dig_port->base.port; 4127 u32 dp_tp_ctl, ddi_buf_ctl; 4128 bool wait = false; 4129 4130 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4131 4132 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 4133 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 4134 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 4135 intel_de_write(dev_priv, DDI_BUF_CTL(port), 4136 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 4137 wait = true; 4138 } 4139 4140 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 4141 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 4142 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4143 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4144 4145 if (wait) 4146 intel_wait_ddi_buf_idle(dev_priv, port); 4147 } 4148 4149 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 4150 if (intel_dp->link_mst) 4151 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 4152 else { 4153 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 4154 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 4155 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4156 } 4157 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); 4158 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4159 4160 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 4161 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 4162 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 4163 4164 intel_wait_ddi_buf_active(dev_priv, port); 4165} 4166 4167static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 4168 u8 dp_train_pat) 4169{ 4170 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4171 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 4172 u32 temp; 4173 4174 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4175 4176 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4177 switch (dp_train_pat & train_pat_mask) { 4178 case DP_TRAINING_PATTERN_DISABLE: 4179 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 4180 break; 4181 case DP_TRAINING_PATTERN_1: 4182 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 4183 break; 4184 case DP_TRAINING_PATTERN_2: 4185 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 4186 break; 4187 case DP_TRAINING_PATTERN_3: 4188 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 4189 break; 4190 case DP_TRAINING_PATTERN_4: 4191 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 4192 break; 4193 } 4194 4195 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); 4196} 4197 4198static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp) 4199{ 4200 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 4201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4202 enum port port = encoder->port; 4203 u32 val; 4204 4205 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); 4206 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 4207 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 4208 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); 4209 4210 /* 4211 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 4212 * reason we need to set idle transmission mode is to work around a HW 4213 * issue where we enable the pipe while not in idle link-training mode. 4214 * In this case there is requirement to wait for a minimum number of 4215 * idle patterns to be sent. 4216 */ 4217 if (port == PORT_A && INTEL_GEN(dev_priv) < 12) 4218 return; 4219 4220 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, 4221 DP_TP_STATUS_IDLE_DONE, 1)) 4222 drm_err(&dev_priv->drm, 4223 "Timed out waiting for DP idle patterns\n"); 4224} 4225 4226static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 4227 enum transcoder cpu_transcoder) 4228{ 4229 if (cpu_transcoder == TRANSCODER_EDP) 4230 return false; 4231 4232 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 4233 return false; 4234 4235 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 4236 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 4237} 4238 4239void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 4240 struct intel_crtc_state *crtc_state) 4241{ 4242 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) 4243 crtc_state->min_voltage_level = 2; 4244 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) 4245 crtc_state->min_voltage_level = 3; 4246 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) 4247 crtc_state->min_voltage_level = 1; 4248 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 4249 crtc_state->min_voltage_level = 2; 4250} 4251 4252static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 4253 enum transcoder cpu_transcoder) 4254{ 4255 u32 master_select; 4256 4257 if (INTEL_GEN(dev_priv) >= 11) { 4258 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 4259 4260 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 4261 return INVALID_TRANSCODER; 4262 4263 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 4264 } else { 4265 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4266 4267 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 4268 return INVALID_TRANSCODER; 4269 4270 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 4271 } 4272 4273 if (master_select == 0) 4274 return TRANSCODER_EDP; 4275 else 4276 return master_select - 1; 4277} 4278 4279static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 4280{ 4281 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 4282 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 4283 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 4284 enum transcoder cpu_transcoder; 4285 4286 crtc_state->master_transcoder = 4287 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 4288 4289 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 4290 enum intel_display_power_domain power_domain; 4291 intel_wakeref_t trans_wakeref; 4292 4293 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 4294 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 4295 power_domain); 4296 4297 if (!trans_wakeref) 4298 continue; 4299 4300 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 4301 crtc_state->cpu_transcoder) 4302 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 4303 4304 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 4305 } 4306 4307 drm_WARN_ON(&dev_priv->drm, 4308 crtc_state->master_transcoder != INVALID_TRANSCODER && 4309 crtc_state->sync_mode_slaves_mask); 4310} 4311 4312void intel_ddi_get_config(struct intel_encoder *encoder, 4313 struct intel_crtc_state *pipe_config) 4314{ 4315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4316 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 4317 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4318 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4319 u32 temp, flags = 0; 4320 4321 /* XXX: DSI transcoder paranoia */ 4322 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 4323 return; 4324 4325 intel_dsc_get_config(encoder, pipe_config); 4326 4327 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 4328 if (temp & TRANS_DDI_PHSYNC) 4329 flags |= DRM_MODE_FLAG_PHSYNC; 4330 else 4331 flags |= DRM_MODE_FLAG_NHSYNC; 4332 if (temp & TRANS_DDI_PVSYNC) 4333 flags |= DRM_MODE_FLAG_PVSYNC; 4334 else 4335 flags |= DRM_MODE_FLAG_NVSYNC; 4336 4337 pipe_config->hw.adjusted_mode.flags |= flags; 4338 4339 switch (temp & TRANS_DDI_BPC_MASK) { 4340 case TRANS_DDI_BPC_6: 4341 pipe_config->pipe_bpp = 18; 4342 break; 4343 case TRANS_DDI_BPC_8: 4344 pipe_config->pipe_bpp = 24; 4345 break; 4346 case TRANS_DDI_BPC_10: 4347 pipe_config->pipe_bpp = 30; 4348 break; 4349 case TRANS_DDI_BPC_12: 4350 pipe_config->pipe_bpp = 36; 4351 break; 4352 default: 4353 break; 4354 } 4355 4356 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4357 case TRANS_DDI_MODE_SELECT_HDMI: 4358 pipe_config->has_hdmi_sink = true; 4359 4360 pipe_config->infoframes.enable |= 4361 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4362 4363 if (pipe_config->infoframes.enable) 4364 pipe_config->has_infoframe = true; 4365 4366 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4367 pipe_config->hdmi_scrambling = true; 4368 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4369 pipe_config->hdmi_high_tmds_clock_ratio = true; 4370 fallthrough; 4371 case TRANS_DDI_MODE_SELECT_DVI: 4372 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4373 pipe_config->lane_count = 4; 4374 break; 4375 case TRANS_DDI_MODE_SELECT_FDI: 4376 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4377 break; 4378 case TRANS_DDI_MODE_SELECT_DP_SST: 4379 if (encoder->type == INTEL_OUTPUT_EDP) 4380 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4381 else 4382 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4383 pipe_config->lane_count = 4384 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4385 intel_dp_get_m_n(intel_crtc, pipe_config); 4386 4387 if (INTEL_GEN(dev_priv) >= 11) { 4388 i915_reg_t dp_tp_ctl; 4389 4390 if (IS_GEN(dev_priv, 11)) 4391 dp_tp_ctl = DP_TP_CTL(encoder->port); 4392 else 4393 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); 4394 4395 pipe_config->fec_enable = 4396 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 4397 4398 drm_dbg_kms(&dev_priv->drm, 4399 "[ENCODER:%d:%s] Fec status: %u\n", 4400 encoder->base.base.id, encoder->base.name, 4401 pipe_config->fec_enable); 4402 } 4403 4404 pipe_config->infoframes.enable |= 4405 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4406 4407 break; 4408 case TRANS_DDI_MODE_SELECT_DP_MST: 4409 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4410 pipe_config->lane_count = 4411 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4412 4413 if (INTEL_GEN(dev_priv) >= 12) 4414 pipe_config->mst_master_transcoder = 4415 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4416 4417 intel_dp_get_m_n(intel_crtc, pipe_config); 4418 4419 pipe_config->infoframes.enable |= 4420 intel_hdmi_infoframes_enabled(encoder, pipe_config); 4421 break; 4422 default: 4423 break; 4424 } 4425 4426 if (INTEL_GEN(dev_priv) >= 12) { 4427 enum transcoder transcoder = 4428 intel_dp_mst_is_slave_trans(pipe_config) ? 4429 pipe_config->mst_master_transcoder : 4430 pipe_config->cpu_transcoder; 4431 4432 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder); 4433 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder); 4434 } 4435 4436 pipe_config->has_audio = 4437 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 4438 4439 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 4440 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 4441 /* 4442 * This is a big fat ugly hack. 4443 * 4444 * Some machines in UEFI boot mode provide us a VBT that has 18 4445 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 4446 * unknown we fail to light up. Yet the same BIOS boots up with 4447 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 4448 * max, not what it tells us to use. 4449 * 4450 * Note: This will still be broken if the eDP panel is not lit 4451 * up by the BIOS, and thus we can't get the mode at module 4452 * load. 4453 */ 4454 drm_dbg_kms(&dev_priv->drm, 4455 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 4456 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 4457 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 4458 } 4459 4460 intel_ddi_clock_get(encoder, pipe_config); 4461 4462 if (IS_GEN9_LP(dev_priv)) 4463 pipe_config->lane_lat_optim_mask = 4464 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 4465 4466 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4467 4468 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4469 4470 intel_read_infoframe(encoder, pipe_config, 4471 HDMI_INFOFRAME_TYPE_AVI, 4472 &pipe_config->infoframes.avi); 4473 intel_read_infoframe(encoder, pipe_config, 4474 HDMI_INFOFRAME_TYPE_SPD, 4475 &pipe_config->infoframes.spd); 4476 intel_read_infoframe(encoder, pipe_config, 4477 HDMI_INFOFRAME_TYPE_VENDOR, 4478 &pipe_config->infoframes.hdmi); 4479 intel_read_infoframe(encoder, pipe_config, 4480 HDMI_INFOFRAME_TYPE_DRM, 4481 &pipe_config->infoframes.drm); 4482 4483 if (INTEL_GEN(dev_priv) >= 8) 4484 bdw_get_trans_port_sync_config(pipe_config); 4485 4486 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4487 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4488} 4489 4490static enum intel_output_type 4491intel_ddi_compute_output_type(struct intel_encoder *encoder, 4492 struct intel_crtc_state *crtc_state, 4493 struct drm_connector_state *conn_state) 4494{ 4495 switch (conn_state->connector->connector_type) { 4496 case DRM_MODE_CONNECTOR_HDMIA: 4497 return INTEL_OUTPUT_HDMI; 4498 case DRM_MODE_CONNECTOR_eDP: 4499 return INTEL_OUTPUT_EDP; 4500 case DRM_MODE_CONNECTOR_DisplayPort: 4501 return INTEL_OUTPUT_DP; 4502 default: 4503 MISSING_CASE(conn_state->connector->connector_type); 4504 return INTEL_OUTPUT_UNUSED; 4505 } 4506} 4507 4508static int intel_ddi_compute_config(struct intel_encoder *encoder, 4509 struct intel_crtc_state *pipe_config, 4510 struct drm_connector_state *conn_state) 4511{ 4512 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4513 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4514 enum port port = encoder->port; 4515 int ret; 4516 4517 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4518 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4519 4520 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4521 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4522 } else { 4523 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4524 } 4525 4526 if (ret) 4527 return ret; 4528 4529 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4530 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4531 pipe_config->pch_pfit.force_thru = 4532 pipe_config->pch_pfit.enabled || 4533 pipe_config->crc_enabled; 4534 4535 if (IS_GEN9_LP(dev_priv)) 4536 pipe_config->lane_lat_optim_mask = 4537 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4538 4539 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 4540 4541 return 0; 4542} 4543 4544static bool mode_equal(const struct drm_display_mode *mode1, 4545 const struct drm_display_mode *mode2) 4546{ 4547 return drm_mode_match(mode1, mode2, 4548 DRM_MODE_MATCH_TIMINGS | 4549 DRM_MODE_MATCH_FLAGS | 4550 DRM_MODE_MATCH_3D_FLAGS) && 4551 mode1->clock == mode2->clock; /* we want an exact match */ 4552} 4553 4554static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4555 const struct intel_link_m_n *m_n_2) 4556{ 4557 return m_n_1->tu == m_n_2->tu && 4558 m_n_1->gmch_m == m_n_2->gmch_m && 4559 m_n_1->gmch_n == m_n_2->gmch_n && 4560 m_n_1->link_m == m_n_2->link_m && 4561 m_n_1->link_n == m_n_2->link_n; 4562} 4563 4564static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4565 const struct intel_crtc_state *crtc_state2) 4566{ 4567 return crtc_state1->hw.active && crtc_state2->hw.active && 4568 crtc_state1->output_types == crtc_state2->output_types && 4569 crtc_state1->output_format == crtc_state2->output_format && 4570 crtc_state1->lane_count == crtc_state2->lane_count && 4571 crtc_state1->port_clock == crtc_state2->port_clock && 4572 mode_equal(&crtc_state1->hw.adjusted_mode, 4573 &crtc_state2->hw.adjusted_mode) && 4574 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4575} 4576 4577static u8 4578intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4579 int tile_group_id) 4580{ 4581 struct drm_connector *connector; 4582 const struct drm_connector_state *conn_state; 4583 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4584 struct intel_atomic_state *state = 4585 to_intel_atomic_state(ref_crtc_state->uapi.state); 4586 u8 transcoders = 0; 4587 int i; 4588 4589 /* 4590 * We don't enable port sync on BDW due to missing w/as and 4591 * due to not having adjusted the modeset sequence appropriately. 4592 */ 4593 if (INTEL_GEN(dev_priv) < 9) 4594 return 0; 4595 4596 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4597 return 0; 4598 4599 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4600 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4601 const struct intel_crtc_state *crtc_state; 4602 4603 if (!crtc) 4604 continue; 4605 4606 if (!connector->has_tile || 4607 connector->tile_group->id != 4608 tile_group_id) 4609 continue; 4610 crtc_state = intel_atomic_get_new_crtc_state(state, 4611 crtc); 4612 if (!crtcs_port_sync_compatible(ref_crtc_state, 4613 crtc_state)) 4614 continue; 4615 transcoders |= BIT(crtc_state->cpu_transcoder); 4616 } 4617 4618 return transcoders; 4619} 4620 4621static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4622 struct intel_crtc_state *crtc_state, 4623 struct drm_connector_state *conn_state) 4624{ 4625 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4626 struct drm_connector *connector = conn_state->connector; 4627 u8 port_sync_transcoders = 0; 4628 4629 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 4630 encoder->base.base.id, encoder->base.name, 4631 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4632 4633 if (connector->has_tile) 4634 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4635 connector->tile_group->id); 4636 4637 /* 4638 * EDP Transcoders cannot be ensalved 4639 * make them a master always when present 4640 */ 4641 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4642 crtc_state->master_transcoder = TRANSCODER_EDP; 4643 else 4644 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4645 4646 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4647 crtc_state->master_transcoder = INVALID_TRANSCODER; 4648 crtc_state->sync_mode_slaves_mask = 4649 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4650 } 4651 4652 return 0; 4653} 4654 4655static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4656{ 4657 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4658 4659 intel_dp_encoder_flush_work(encoder); 4660 4661 drm_encoder_cleanup(encoder); 4662 kfree(dig_port); 4663} 4664 4665static const struct drm_encoder_funcs intel_ddi_funcs = { 4666 .reset = intel_dp_encoder_reset, 4667 .destroy = intel_ddi_encoder_destroy, 4668}; 4669 4670static struct intel_connector * 4671intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4672{ 4673 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4674 struct intel_connector *connector; 4675 enum port port = dig_port->base.port; 4676 4677 connector = intel_connector_alloc(); 4678 if (!connector) 4679 return NULL; 4680 4681 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4682 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4683 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4684 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4685 4686 if (INTEL_GEN(dev_priv) >= 12) 4687 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4688 else if (INTEL_GEN(dev_priv) >= 11) 4689 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4690 else if (IS_CANNONLAKE(dev_priv)) 4691 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4692 else if (IS_GEN9_LP(dev_priv)) 4693 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4694 else 4695 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4696 4697 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4698 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4699 4700 if (INTEL_GEN(dev_priv) < 12) { 4701 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port); 4702 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port); 4703 } 4704 4705 if (!intel_dp_init_connector(dig_port, connector)) { 4706 kfree(connector); 4707 return NULL; 4708 } 4709 4710 return connector; 4711} 4712 4713static int modeset_pipe(struct drm_crtc *crtc, 4714 struct drm_modeset_acquire_ctx *ctx) 4715{ 4716 struct drm_atomic_state *state; 4717 struct drm_crtc_state *crtc_state; 4718 int ret; 4719 4720 state = drm_atomic_state_alloc(crtc->dev); 4721 if (!state) 4722 return -ENOMEM; 4723 4724 state->acquire_ctx = ctx; 4725 4726 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4727 if (IS_ERR(crtc_state)) { 4728 ret = PTR_ERR(crtc_state); 4729 goto out; 4730 } 4731 4732 crtc_state->connectors_changed = true; 4733 4734 ret = drm_atomic_commit(state); 4735out: 4736 drm_atomic_state_put(state); 4737 4738 return ret; 4739} 4740 4741static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4742 struct drm_modeset_acquire_ctx *ctx) 4743{ 4744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4745 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4746 struct intel_connector *connector = hdmi->attached_connector; 4747 struct i2c_adapter *adapter = 4748 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4749 struct drm_connector_state *conn_state; 4750 struct intel_crtc_state *crtc_state; 4751 struct intel_crtc *crtc; 4752 u8 config; 4753 int ret; 4754 4755 if (!connector || connector->base.status != connector_status_connected) 4756 return 0; 4757 4758 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4759 ctx); 4760 if (ret) 4761 return ret; 4762 4763 conn_state = connector->base.state; 4764 4765 crtc = to_intel_crtc(conn_state->crtc); 4766 if (!crtc) 4767 return 0; 4768 4769 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4770 if (ret) 4771 return ret; 4772 4773 crtc_state = to_intel_crtc_state(crtc->base.state); 4774 4775 drm_WARN_ON(&dev_priv->drm, 4776 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4777 4778 if (!crtc_state->hw.active) 4779 return 0; 4780 4781 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4782 !crtc_state->hdmi_scrambling) 4783 return 0; 4784 4785 if (conn_state->commit && 4786 !try_wait_for_completion(&conn_state->commit->hw_done)) 4787 return 0; 4788 4789 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4790 if (ret < 0) { 4791 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4792 ret); 4793 return 0; 4794 } 4795 4796 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4797 crtc_state->hdmi_high_tmds_clock_ratio && 4798 !!(config & SCDC_SCRAMBLING_ENABLE) == 4799 crtc_state->hdmi_scrambling) 4800 return 0; 4801 4802 /* 4803 * HDMI 2.0 says that one should not send scrambled data 4804 * prior to configuring the sink scrambling, and that 4805 * TMDS clock/data transmission should be suspended when 4806 * changing the TMDS clock rate in the sink. So let's 4807 * just do a full modeset here, even though some sinks 4808 * would be perfectly happy if were to just reconfigure 4809 * the SCDC settings on the fly. 4810 */ 4811 return modeset_pipe(&crtc->base, ctx); 4812} 4813 4814static enum intel_hotplug_state 4815intel_ddi_hotplug(struct intel_encoder *encoder, 4816 struct intel_connector *connector) 4817{ 4818 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4819 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4820 enum phy phy = intel_port_to_phy(i915, encoder->port); 4821 bool is_tc = intel_phy_is_tc(i915, phy); 4822 struct drm_modeset_acquire_ctx ctx; 4823 enum intel_hotplug_state state; 4824 int ret; 4825 4826 state = intel_encoder_hotplug(encoder, connector); 4827 4828 drm_modeset_acquire_init(&ctx, 0); 4829 4830 for (;;) { 4831 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4832 ret = intel_hdmi_reset_link(encoder, &ctx); 4833 else 4834 ret = intel_dp_retrain_link(encoder, &ctx); 4835 4836 if (ret == -EDEADLK) { 4837 drm_modeset_backoff(&ctx); 4838 continue; 4839 } 4840 4841 break; 4842 } 4843 4844 drm_modeset_drop_locks(&ctx); 4845 drm_modeset_acquire_fini(&ctx); 4846 drm_WARN(encoder->base.dev, ret, 4847 "Acquiring modeset locks failed with %i\n", ret); 4848 4849 /* 4850 * Unpowered type-c dongles can take some time to boot and be 4851 * responsible, so here giving some time to those dongles to power up 4852 * and then retrying the probe. 4853 * 4854 * On many platforms the HDMI live state signal is known to be 4855 * unreliable, so we can't use it to detect if a sink is connected or 4856 * not. Instead we detect if it's connected based on whether we can 4857 * read the EDID or not. That in turn has a problem during disconnect, 4858 * since the HPD interrupt may be raised before the DDC lines get 4859 * disconnected (due to how the required length of DDC vs. HPD 4860 * connector pins are specified) and so we'll still be able to get a 4861 * valid EDID. To solve this schedule another detection cycle if this 4862 * time around we didn't detect any change in the sink's connection 4863 * status. 4864 * 4865 * Type-c connectors which get their HPD signal deasserted then 4866 * reasserted, without unplugging/replugging the sink from the 4867 * connector, introduce a delay until the AUX channel communication 4868 * becomes functional. Retry the detection for 5 seconds on type-c 4869 * connectors to account for this delay. 4870 */ 4871 if (state == INTEL_HOTPLUG_UNCHANGED && 4872 connector->hotplug_retries < (is_tc ? 5 : 1) && 4873 !dig_port->dp.is_mst) 4874 state = INTEL_HOTPLUG_RETRY; 4875 4876 return state; 4877} 4878 4879static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4880{ 4881 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4882 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4883 4884 return intel_de_read(dev_priv, SDEISR) & bit; 4885} 4886 4887static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4888{ 4889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4890 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4891 4892 return intel_de_read(dev_priv, DEISR) & bit; 4893} 4894 4895static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4896{ 4897 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4898 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4899 4900 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4901} 4902 4903static struct intel_connector * 4904intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4905{ 4906 struct intel_connector *connector; 4907 enum port port = dig_port->base.port; 4908 4909 connector = intel_connector_alloc(); 4910 if (!connector) 4911 return NULL; 4912 4913 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4914 intel_hdmi_init_connector(dig_port, connector); 4915 4916 return connector; 4917} 4918 4919static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4920{ 4921 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4922 4923 if (dig_port->base.port != PORT_A) 4924 return false; 4925 4926 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4927 return false; 4928 4929 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4930 * supported configuration 4931 */ 4932 if (IS_GEN9_LP(dev_priv)) 4933 return true; 4934 4935 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4936 * one who does also have a full A/E split called 4937 * DDI_F what makes DDI_E useless. However for this 4938 * case let's trust VBT info. 4939 */ 4940 if (IS_CANNONLAKE(dev_priv) && 4941 !intel_bios_is_port_present(dev_priv, PORT_E)) 4942 return true; 4943 4944 return false; 4945} 4946 4947static int 4948intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4949{ 4950 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4951 enum port port = dig_port->base.port; 4952 int max_lanes = 4; 4953 4954 if (INTEL_GEN(dev_priv) >= 11) 4955 return max_lanes; 4956 4957 if (port == PORT_A || port == PORT_E) { 4958 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4959 max_lanes = port == PORT_A ? 4 : 0; 4960 else 4961 /* Both A and E share 2 lanes */ 4962 max_lanes = 2; 4963 } 4964 4965 /* 4966 * Some BIOS might fail to set this bit on port A if eDP 4967 * wasn't lit up at boot. Force this bit set when needed 4968 * so we use the proper lane count for our calculations. 4969 */ 4970 if (intel_ddi_a_force_4_lanes(dig_port)) { 4971 drm_dbg_kms(&dev_priv->drm, 4972 "Forcing DDI_A_4_LANES for port A\n"); 4973 dig_port->saved_port_bits |= DDI_A_4_LANES; 4974 max_lanes = 4; 4975 } 4976 4977 return max_lanes; 4978} 4979 4980static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4981{ 4982 return i915->hti_state & HDPORT_ENABLED && 4983 (i915->hti_state & HDPORT_PHY_USED_DP(phy) || 4984 i915->hti_state & HDPORT_PHY_USED_HDMI(phy)); 4985} 4986 4987static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4988 enum port port) 4989{ 4990 if (port >= PORT_D) 4991 return HPD_PORT_TC1 + port - PORT_D; 4992 else 4993 return HPD_PORT_A + port - PORT_A; 4994} 4995 4996static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4997 enum port port) 4998{ 4999 if (HAS_PCH_TGP(dev_priv)) 5000 return tgl_hpd_pin(dev_priv, port); 5001 5002 if (port >= PORT_D) 5003 return HPD_PORT_C + port - PORT_D; 5004 else 5005 return HPD_PORT_A + port - PORT_A; 5006} 5007 5008static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 5009 enum port port) 5010{ 5011 if (port >= PORT_C) 5012 return HPD_PORT_TC1 + port - PORT_C; 5013 else 5014 return HPD_PORT_A + port - PORT_A; 5015} 5016 5017static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 5018 enum port port) 5019{ 5020 if (port == PORT_D) 5021 return HPD_PORT_A; 5022 5023 if (HAS_PCH_MCC(dev_priv)) 5024 return icl_hpd_pin(dev_priv, port); 5025 5026 return HPD_PORT_A + port - PORT_A; 5027} 5028 5029static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 5030 enum port port) 5031{ 5032 if (port == PORT_F) 5033 return HPD_PORT_E; 5034 5035 return HPD_PORT_A + port - PORT_A; 5036} 5037 5038void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 5039{ 5040 struct intel_digital_port *dig_port; 5041 struct intel_encoder *encoder; 5042 bool init_hdmi, init_dp, init_lspcon = false; 5043 enum phy phy = intel_port_to_phy(dev_priv, port); 5044 5045 /* 5046 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5047 * have taken over some of the PHYs and made them unavailable to the 5048 * driver. In that case we should skip initializing the corresponding 5049 * outputs. 5050 */ 5051 if (hti_uses_phy(dev_priv, phy)) { 5052 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 5053 port_name(port), phy_name(phy)); 5054 return; 5055 } 5056 5057 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || 5058 intel_bios_port_supports_hdmi(dev_priv, port); 5059 init_dp = intel_bios_port_supports_dp(dev_priv, port); 5060 5061 if (intel_bios_is_lspcon_present(dev_priv, port)) { 5062 /* 5063 * Lspcon device needs to be driven with DP connector 5064 * with special detection sequence. So make sure DP 5065 * is initialized before lspcon. 5066 */ 5067 init_dp = true; 5068 init_lspcon = true; 5069 init_hdmi = false; 5070 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 5071 port_name(port)); 5072 } 5073 5074 if (!init_dp && !init_hdmi) { 5075 drm_dbg_kms(&dev_priv->drm, 5076 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5077 port_name(port)); 5078 return; 5079 } 5080 5081 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 5082 if (!dig_port) 5083 return; 5084 5085 encoder = &dig_port->base; 5086 5087 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 5088 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); 5089 5090 mutex_init(&dig_port->hdcp_mutex); 5091 dig_port->num_hdcp_streams = 0; 5092 5093 encoder->hotplug = intel_ddi_hotplug; 5094 encoder->compute_output_type = intel_ddi_compute_output_type; 5095 encoder->compute_config = intel_ddi_compute_config; 5096 encoder->compute_config_late = intel_ddi_compute_config_late; 5097 encoder->enable = intel_enable_ddi; 5098 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5099 encoder->pre_enable = intel_ddi_pre_enable; 5100 encoder->disable = intel_disable_ddi; 5101 encoder->post_disable = intel_ddi_post_disable; 5102 encoder->update_pipe = intel_ddi_update_pipe; 5103 encoder->get_hw_state = intel_ddi_get_hw_state; 5104 encoder->get_config = intel_ddi_get_config; 5105 encoder->suspend = intel_dp_encoder_suspend; 5106 encoder->get_power_domains = intel_ddi_get_power_domains; 5107 5108 encoder->type = INTEL_OUTPUT_DDI; 5109 encoder->power_domain = intel_port_to_power_domain(port); 5110 encoder->port = port; 5111 encoder->cloneable = 0; 5112 encoder->pipe_mask = ~0; 5113 5114 if (IS_ROCKETLAKE(dev_priv)) 5115 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5116 else if (INTEL_GEN(dev_priv) >= 12) 5117 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5118 else if (IS_ELKHARTLAKE(dev_priv)) 5119 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5120 else if (IS_GEN(dev_priv, 11)) 5121 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5122 else if (IS_GEN(dev_priv, 10)) 5123 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 5124 else 5125 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5126 5127 if (INTEL_GEN(dev_priv) >= 11) 5128 dig_port->saved_port_bits = 5129 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5130 & DDI_BUF_PORT_REVERSAL; 5131 else 5132 dig_port->saved_port_bits = 5133 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5134 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5135 5136 dig_port->dp.output_reg = INVALID_MMIO_REG; 5137 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5138 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 5139 5140 if (intel_phy_is_tc(dev_priv, phy)) { 5141 bool is_legacy = 5142 !intel_bios_port_supports_typec_usb(dev_priv, port) && 5143 !intel_bios_port_supports_tbt(dev_priv, port); 5144 5145 intel_tc_port_init(dig_port, is_legacy); 5146 5147 encoder->update_prepare = intel_ddi_update_prepare; 5148 encoder->update_complete = intel_ddi_update_complete; 5149 } 5150 5151 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5152 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 5153 port - PORT_A; 5154 5155 if (init_dp) { 5156 if (!intel_ddi_init_dp_connector(dig_port)) 5157 goto err; 5158 5159 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5160 } 5161 5162 /* In theory we don't need the encoder->type check, but leave it just in 5163 * case we have some really bad VBTs... */ 5164 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5165 if (!intel_ddi_init_hdmi_connector(dig_port)) 5166 goto err; 5167 } 5168 5169 if (init_lspcon) { 5170 if (lspcon_init(dig_port)) 5171 /* TODO: handle hdmi info frame part */ 5172 drm_dbg_kms(&dev_priv->drm, 5173 "LSPCON init success on port %c\n", 5174 port_name(port)); 5175 else 5176 /* 5177 * LSPCON init faied, but DP init was success, so 5178 * lets try to drive as DP++ port. 5179 */ 5180 drm_err(&dev_priv->drm, 5181 "LSPCON init failed on port %c\n", 5182 port_name(port)); 5183 } 5184 5185 if (INTEL_GEN(dev_priv) >= 11) { 5186 if (intel_phy_is_tc(dev_priv, phy)) 5187 dig_port->connected = intel_tc_port_connected; 5188 else 5189 dig_port->connected = lpt_digital_port_connected; 5190 } else if (INTEL_GEN(dev_priv) >= 8) { 5191 if (port == PORT_A || IS_GEN9_LP(dev_priv)) 5192 dig_port->connected = bdw_digital_port_connected; 5193 else 5194 dig_port->connected = lpt_digital_port_connected; 5195 } else { 5196 if (port == PORT_A) 5197 dig_port->connected = hsw_digital_port_connected; 5198 else 5199 dig_port->connected = lpt_digital_port_connected; 5200 } 5201 5202 intel_infoframe_init(dig_port); 5203 5204 return; 5205 5206err: 5207 drm_encoder_cleanup(&encoder->base); 5208 kfree(dig_port); 5209} 5210