1/* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23#include <linux/delay.h> 24#include <linux/errno.h> 25#include <linux/i2c.h> 26#include <linux/init.h> 27#include <linux/kernel.h> 28#include <linux/module.h> 29#include <linux/sched.h> 30#include <linux/seq_file.h> 31 32#include <drm/drm_dp_helper.h> 33#include <drm/drm_print.h> 34#include <drm/drm_vblank.h> 35#include <drm/drm_dp_mst_helper.h> 36 37#include "drm_crtc_helper_internal.h" 38 39/** 40 * DOC: dp helpers 41 * 42 * These functions contain some common logic and helpers at various abstraction 43 * levels to deal with Display Port sink devices and related things like DP aux 44 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 45 * blocks, ... 46 */ 47 48/* Helpers for DP link training */ 49static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 50{ 51 return link_status[r - DP_LANE0_1_STATUS]; 52} 53 54static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 55 int lane) 56{ 57 int i = DP_LANE0_1_STATUS + (lane >> 1); 58 int s = (lane & 1) * 4; 59 u8 l = dp_link_status(link_status, i); 60 61 return (l >> s) & 0xf; 62} 63 64bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 65 int lane_count) 66{ 67 u8 lane_align; 68 u8 lane_status; 69 int lane; 70 71 lane_align = dp_link_status(link_status, 72 DP_LANE_ALIGN_STATUS_UPDATED); 73 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 74 return false; 75 for (lane = 0; lane < lane_count; lane++) { 76 lane_status = dp_get_lane_status(link_status, lane); 77 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 78 return false; 79 } 80 return true; 81} 82EXPORT_SYMBOL(drm_dp_channel_eq_ok); 83 84bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 85 int lane_count) 86{ 87 int lane; 88 u8 lane_status; 89 90 for (lane = 0; lane < lane_count; lane++) { 91 lane_status = dp_get_lane_status(link_status, lane); 92 if ((lane_status & DP_LANE_CR_DONE) == 0) 93 return false; 94 } 95 return true; 96} 97EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 98 99u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 100 int lane) 101{ 102 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 103 int s = ((lane & 1) ? 104 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 105 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 106 u8 l = dp_link_status(link_status, i); 107 108 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 109} 110EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 111 112u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 113 int lane) 114{ 115 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 116 int s = ((lane & 1) ? 117 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 118 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 119 u8 l = dp_link_status(link_status, i); 120 121 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 122} 123EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 124 125u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], 126 unsigned int lane) 127{ 128 unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2; 129 u8 value = dp_link_status(link_status, offset); 130 131 return (value >> (lane << 1)) & 0x3; 132} 133EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor); 134 135void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 136{ 137 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 138 DP_TRAINING_AUX_RD_MASK; 139 140 if (rd_interval > 4) 141 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", 142 rd_interval); 143 144 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 145 rd_interval = 100; 146 else 147 rd_interval *= 4 * USEC_PER_MSEC; 148 149 usleep_range(rd_interval, rd_interval * 2); 150} 151EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 152 153void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 154{ 155 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 156 DP_TRAINING_AUX_RD_MASK; 157 158 if (rd_interval > 4) 159 DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", 160 rd_interval); 161 162 if (rd_interval == 0) 163 rd_interval = 400; 164 else 165 rd_interval *= 4 * USEC_PER_MSEC; 166 167 usleep_range(rd_interval, rd_interval * 2); 168} 169EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 170 171u8 drm_dp_link_rate_to_bw_code(int link_rate) 172{ 173 /* Spec says link_bw = link_rate / 0.27Gbps */ 174 return link_rate / 27000; 175} 176EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 177 178int drm_dp_bw_code_to_link_rate(u8 link_bw) 179{ 180 /* Spec says link_rate = link_bw * 0.27Gbps */ 181 return link_bw * 27000; 182} 183EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 184 185#define AUX_RETRY_INTERVAL 500 /* us */ 186 187static inline void 188drm_dp_dump_access(const struct drm_dp_aux *aux, 189 u8 request, uint offset, void *buffer, int ret) 190{ 191 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 192 193 if (ret > 0) 194 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 195 aux->name, offset, arrow, ret, min(ret, 20), buffer); 196 else 197 DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n", 198 aux->name, offset, arrow, ret); 199} 200 201/** 202 * DOC: dp helpers 203 * 204 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 205 * independent access to AUX functionality. Drivers can take advantage of 206 * this by filling in the fields of the drm_dp_aux structure. 207 * 208 * Transactions are described using a hardware-independent drm_dp_aux_msg 209 * structure, which is passed into a driver's .transfer() implementation. 210 * Both native and I2C-over-AUX transactions are supported. 211 */ 212 213static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 214 unsigned int offset, void *buffer, size_t size) 215{ 216 struct drm_dp_aux_msg msg; 217 unsigned int retry, native_reply; 218 int err = 0, ret = 0; 219 220 memset(&msg, 0, sizeof(msg)); 221 msg.address = offset; 222 msg.request = request; 223 msg.buffer = buffer; 224 msg.size = size; 225 226 mutex_lock(&aux->hw_mutex); 227 228 /* 229 * The specification doesn't give any recommendation on how often to 230 * retry native transactions. We used to retry 7 times like for 231 * aux i2c transactions but real world devices this wasn't 232 * sufficient, bump to 32 which makes Dell 4k monitors happier. 233 */ 234 for (retry = 0; retry < 32; retry++) { 235 if (ret != 0 && ret != -ETIMEDOUT) { 236 usleep_range(AUX_RETRY_INTERVAL, 237 AUX_RETRY_INTERVAL + 100); 238 } 239 240 ret = aux->transfer(aux, &msg); 241 if (ret >= 0) { 242 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 243 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 244 if (ret == size) 245 goto unlock; 246 247 ret = -EPROTO; 248 } else 249 ret = -EIO; 250 } 251 252 /* 253 * We want the error we return to be the error we received on 254 * the first transaction, since we may get a different error the 255 * next time we retry 256 */ 257 if (!err) 258 err = ret; 259 } 260 261 DRM_DEBUG_KMS("%s: Too many retries, giving up. First error: %d\n", 262 aux->name, err); 263 ret = err; 264 265unlock: 266 mutex_unlock(&aux->hw_mutex); 267 return ret; 268} 269 270/** 271 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 272 * @aux: DisplayPort AUX channel (SST or MST) 273 * @offset: address of the (first) register to read 274 * @buffer: buffer to store the register values 275 * @size: number of bytes in @buffer 276 * 277 * Returns the number of bytes transferred on success, or a negative error 278 * code on failure. -EIO is returned if the request was NAKed by the sink or 279 * if the retry count was exceeded. If not all bytes were transferred, this 280 * function returns -EPROTO. Errors from the underlying AUX channel transfer 281 * function, with the exception of -EBUSY (which causes the transaction to 282 * be retried), are propagated to the caller. 283 */ 284ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 285 void *buffer, size_t size) 286{ 287 int ret; 288 289 /* 290 * HP ZR24w corrupts the first DPCD access after entering power save 291 * mode. Eg. on a read, the entire buffer will be filled with the same 292 * byte. Do a throw away read to avoid corrupting anything we care 293 * about. Afterwards things will work correctly until the monitor 294 * gets woken up and subsequently re-enters power save mode. 295 * 296 * The user pressing any button on the monitor is enough to wake it 297 * up, so there is no particularly good place to do the workaround. 298 * We just have to do it before any DPCD access and hope that the 299 * monitor doesn't power down exactly after the throw away read. 300 */ 301 if (!aux->is_remote) { 302 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, 303 buffer, 1); 304 if (ret != 1) 305 goto out; 306 } 307 308 if (aux->is_remote) 309 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 310 else 311 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 312 buffer, size); 313 314out: 315 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 316 return ret; 317} 318EXPORT_SYMBOL(drm_dp_dpcd_read); 319 320/** 321 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 322 * @aux: DisplayPort AUX channel (SST or MST) 323 * @offset: address of the (first) register to write 324 * @buffer: buffer containing the values to write 325 * @size: number of bytes in @buffer 326 * 327 * Returns the number of bytes transferred on success, or a negative error 328 * code on failure. -EIO is returned if the request was NAKed by the sink or 329 * if the retry count was exceeded. If not all bytes were transferred, this 330 * function returns -EPROTO. Errors from the underlying AUX channel transfer 331 * function, with the exception of -EBUSY (which causes the transaction to 332 * be retried), are propagated to the caller. 333 */ 334ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 335 void *buffer, size_t size) 336{ 337 int ret; 338 339 if (aux->is_remote) 340 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 341 else 342 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 343 buffer, size); 344 345 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 346 return ret; 347} 348EXPORT_SYMBOL(drm_dp_dpcd_write); 349 350/** 351 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 352 * @aux: DisplayPort AUX channel 353 * @status: buffer to store the link status in (must be at least 6 bytes) 354 * 355 * Returns the number of bytes transferred on success or a negative error 356 * code on failure. 357 */ 358int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 359 u8 status[DP_LINK_STATUS_SIZE]) 360{ 361 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 362 DP_LINK_STATUS_SIZE); 363} 364EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 365 366static bool is_edid_digital_input_dp(const struct edid *edid) 367{ 368 return edid && edid->revision >= 4 && 369 edid->input & DRM_EDID_INPUT_DIGITAL && 370 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 371} 372 373/** 374 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 375 * @dpcd: DisplayPort configuration data 376 * @port_cap: port capabilities 377 * @type: port type to be checked. Can be: 378 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 379 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 380 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 381 * 382 * Caveat: Only works with DPCD 1.1+ port caps. 383 * 384 * Returns: whether the downstream facing port matches the type. 385 */ 386bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 387 const u8 port_cap[4], u8 type) 388{ 389 return drm_dp_is_branch(dpcd) && 390 dpcd[DP_DPCD_REV] >= 0x11 && 391 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 392} 393EXPORT_SYMBOL(drm_dp_downstream_is_type); 394 395/** 396 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 397 * @dpcd: DisplayPort configuration data 398 * @port_cap: port capabilities 399 * @edid: EDID 400 * 401 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 402 */ 403bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 404 const u8 port_cap[4], 405 const struct edid *edid) 406{ 407 if (dpcd[DP_DPCD_REV] < 0x11) { 408 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 409 case DP_DWN_STRM_PORT_TYPE_TMDS: 410 return true; 411 default: 412 return false; 413 } 414 } 415 416 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 417 case DP_DS_PORT_TYPE_DP_DUALMODE: 418 if (is_edid_digital_input_dp(edid)) 419 return false; 420 fallthrough; 421 case DP_DS_PORT_TYPE_DVI: 422 case DP_DS_PORT_TYPE_HDMI: 423 return true; 424 default: 425 return false; 426 } 427} 428EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 429 430/** 431 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 432 * @aux: DisplayPort AUX channel 433 * @real_edid_checksum: real edid checksum for the last block 434 * 435 * Returns: 436 * True on success 437 */ 438bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 439 u8 real_edid_checksum) 440{ 441 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 442 443 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 444 &auto_test_req, 1) < 1) { 445 DRM_ERROR("%s: DPCD failed read at register 0x%x\n", 446 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 447 return false; 448 } 449 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 450 451 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 452 DRM_ERROR("%s: DPCD failed read at register 0x%x\n", 453 aux->name, DP_TEST_REQUEST); 454 return false; 455 } 456 link_edid_read &= DP_TEST_LINK_EDID_READ; 457 458 if (!auto_test_req || !link_edid_read) { 459 DRM_DEBUG_KMS("%s: Source DUT does not support TEST_EDID_READ\n", 460 aux->name); 461 return false; 462 } 463 464 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 465 &auto_test_req, 1) < 1) { 466 DRM_ERROR("%s: DPCD failed write at register 0x%x\n", 467 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 468 return false; 469 } 470 471 /* send back checksum for the last edid extension block data */ 472 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 473 &real_edid_checksum, 1) < 1) { 474 DRM_ERROR("%s: DPCD failed write at register 0x%x\n", 475 aux->name, DP_TEST_EDID_CHECKSUM); 476 return false; 477 } 478 479 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 480 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 481 DRM_ERROR("%s: DPCD failed write at register 0x%x\n", 482 aux->name, DP_TEST_RESPONSE); 483 return false; 484 } 485 486 return true; 487} 488EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 489 490static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 491{ 492 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 493 494 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 495 port_count = 4; 496 497 return port_count; 498} 499 500static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 501 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 502{ 503 u8 dpcd_ext[6]; 504 int ret; 505 506 /* 507 * Prior to DP1.3 the bit represented by 508 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 509 * If it is set DP_DPCD_REV at 0000h could be at a value less than 510 * the true capability of the panel. The only way to check is to 511 * then compare 0000h and 2200h. 512 */ 513 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 514 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 515 return 0; 516 517 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 518 sizeof(dpcd_ext)); 519 if (ret < 0) 520 return ret; 521 if (ret != sizeof(dpcd_ext)) 522 return -EIO; 523 524 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 525 DRM_DEBUG_KMS("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 526 aux->name, dpcd[DP_DPCD_REV], 527 dpcd_ext[DP_DPCD_REV]); 528 return 0; 529 } 530 531 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 532 return 0; 533 534 DRM_DEBUG_KMS("%s: Base DPCD: %*ph\n", 535 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 536 537 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 538 539 return 0; 540} 541 542/** 543 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 544 * available 545 * @aux: DisplayPort AUX channel 546 * @dpcd: Buffer to store the resulting DPCD in 547 * 548 * Attempts to read the base DPCD caps for @aux. Additionally, this function 549 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 550 * present. 551 * 552 * Returns: %0 if the DPCD was read successfully, negative error code 553 * otherwise. 554 */ 555int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 556 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 557{ 558 int ret; 559 560 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 561 if (ret < 0) 562 return ret; 563 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 564 return -EIO; 565 566 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 567 if (ret < 0) 568 return ret; 569 570 DRM_DEBUG_KMS("%s: DPCD: %*ph\n", 571 aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 572 573 return ret; 574} 575EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 576 577/** 578 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 579 * @aux: DisplayPort AUX channel 580 * @dpcd: A cached copy of the port's DPCD 581 * @downstream_ports: buffer to store the downstream port info in 582 * 583 * See also: 584 * drm_dp_downstream_max_clock() 585 * drm_dp_downstream_max_bpc() 586 * 587 * Returns: 0 if either the downstream port info was read successfully or 588 * there was no downstream info to read, or a negative error code otherwise. 589 */ 590int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 591 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 592 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 593{ 594 int ret; 595 u8 len; 596 597 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 598 599 /* No downstream info to read */ 600 if (!drm_dp_is_branch(dpcd) || 601 dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || 602 !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 603 return 0; 604 605 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 606 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 607 * some branches do it we need to handle it regardless. 608 */ 609 len = drm_dp_downstream_port_count(dpcd); 610 if (!len) 611 return 0; 612 613 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 614 len *= 4; 615 616 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 617 if (ret < 0) 618 return ret; 619 if (ret != len) 620 return -EIO; 621 622 DRM_DEBUG_KMS("%s: DPCD DFP: %*ph\n", 623 aux->name, len, downstream_ports); 624 625 return 0; 626} 627EXPORT_SYMBOL(drm_dp_read_downstream_info); 628 629/** 630 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 631 * @dpcd: DisplayPort configuration data 632 * @port_cap: port capabilities 633 * 634 * Returns: Downstream facing port max dot clock in kHz on success, 635 * or 0 if max clock not defined 636 */ 637int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 638 const u8 port_cap[4]) 639{ 640 if (!drm_dp_is_branch(dpcd)) 641 return 0; 642 643 if (dpcd[DP_DPCD_REV] < 0x11) 644 return 0; 645 646 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 647 case DP_DS_PORT_TYPE_VGA: 648 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 649 return 0; 650 return port_cap[1] * 8000; 651 default: 652 return 0; 653 } 654} 655EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 656 657/** 658 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 659 * @dpcd: DisplayPort configuration data 660 * @port_cap: port capabilities 661 * @edid: EDID 662 * 663 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 664 * or 0 if max TMDS clock not defined 665 */ 666int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 667 const u8 port_cap[4], 668 const struct edid *edid) 669{ 670 if (!drm_dp_is_branch(dpcd)) 671 return 0; 672 673 if (dpcd[DP_DPCD_REV] < 0x11) { 674 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 675 case DP_DWN_STRM_PORT_TYPE_TMDS: 676 return 165000; 677 default: 678 return 0; 679 } 680 } 681 682 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 683 case DP_DS_PORT_TYPE_DP_DUALMODE: 684 if (is_edid_digital_input_dp(edid)) 685 return 0; 686 /* 687 * It's left up to the driver to check the 688 * DP dual mode adapter's max TMDS clock. 689 * 690 * Unfortunatley it looks like branch devices 691 * may not fordward that the DP dual mode i2c 692 * access so we just usually get i2c nak :( 693 */ 694 fallthrough; 695 case DP_DS_PORT_TYPE_HDMI: 696 /* 697 * We should perhaps assume 165 MHz when detailed cap 698 * info is not available. But looks like many typical 699 * branch devices fall into that category and so we'd 700 * probably end up with users complaining that they can't 701 * get high resolution modes with their favorite dongle. 702 * 703 * So let's limit to 300 MHz instead since DPCD 1.4 704 * HDMI 2.0 DFPs are required to have the detailed cap 705 * info. So it's more likely we're dealing with a HDMI 1.4 706 * compatible* device here. 707 */ 708 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 709 return 300000; 710 return port_cap[1] * 2500; 711 case DP_DS_PORT_TYPE_DVI: 712 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 713 return 165000; 714 /* FIXME what to do about DVI dual link? */ 715 return port_cap[1] * 2500; 716 default: 717 return 0; 718 } 719} 720EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 721 722/** 723 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 724 * @dpcd: DisplayPort configuration data 725 * @port_cap: port capabilities 726 * @edid: EDID 727 * 728 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 729 * or 0 if max TMDS clock not defined 730 */ 731int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 732 const u8 port_cap[4], 733 const struct edid *edid) 734{ 735 if (!drm_dp_is_branch(dpcd)) 736 return 0; 737 738 if (dpcd[DP_DPCD_REV] < 0x11) { 739 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 740 case DP_DWN_STRM_PORT_TYPE_TMDS: 741 return 25000; 742 default: 743 return 0; 744 } 745 } 746 747 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 748 case DP_DS_PORT_TYPE_DP_DUALMODE: 749 if (is_edid_digital_input_dp(edid)) 750 return 0; 751 fallthrough; 752 case DP_DS_PORT_TYPE_DVI: 753 case DP_DS_PORT_TYPE_HDMI: 754 /* 755 * Unclear whether the protocol converter could 756 * utilize pixel replication. Assume it won't. 757 */ 758 return 25000; 759 default: 760 return 0; 761 } 762} 763EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 764 765/** 766 * drm_dp_downstream_max_bpc() - extract downstream facing port max 767 * bits per component 768 * @dpcd: DisplayPort configuration data 769 * @port_cap: downstream facing port capabilities 770 * @edid: EDID 771 * 772 * Returns: Max bpc on success or 0 if max bpc not defined 773 */ 774int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 775 const u8 port_cap[4], 776 const struct edid *edid) 777{ 778 if (!drm_dp_is_branch(dpcd)) 779 return 0; 780 781 if (dpcd[DP_DPCD_REV] < 0x11) { 782 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 783 case DP_DWN_STRM_PORT_TYPE_DP: 784 return 0; 785 default: 786 return 8; 787 } 788 } 789 790 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 791 case DP_DS_PORT_TYPE_DP: 792 return 0; 793 case DP_DS_PORT_TYPE_DP_DUALMODE: 794 if (is_edid_digital_input_dp(edid)) 795 return 0; 796 fallthrough; 797 case DP_DS_PORT_TYPE_HDMI: 798 case DP_DS_PORT_TYPE_DVI: 799 case DP_DS_PORT_TYPE_VGA: 800 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 801 return 8; 802 803 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 804 case DP_DS_8BPC: 805 return 8; 806 case DP_DS_10BPC: 807 return 10; 808 case DP_DS_12BPC: 809 return 12; 810 case DP_DS_16BPC: 811 return 16; 812 default: 813 return 8; 814 } 815 break; 816 default: 817 return 8; 818 } 819} 820EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 821 822/** 823 * drm_dp_downstream_420_passthrough() - determine downstream facing port 824 * YCbCr 4:2:0 pass-through capability 825 * @dpcd: DisplayPort configuration data 826 * @port_cap: downstream facing port capabilities 827 * 828 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 829 */ 830bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 831 const u8 port_cap[4]) 832{ 833 if (!drm_dp_is_branch(dpcd)) 834 return false; 835 836 if (dpcd[DP_DPCD_REV] < 0x13) 837 return false; 838 839 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 840 case DP_DS_PORT_TYPE_DP: 841 return true; 842 case DP_DS_PORT_TYPE_HDMI: 843 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 844 return false; 845 846 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 847 default: 848 return false; 849 } 850} 851EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 852 853/** 854 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 855 * YCbCr 4:4:4->4:2:0 conversion capability 856 * @dpcd: DisplayPort configuration data 857 * @port_cap: downstream facing port capabilities 858 * 859 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 860 */ 861bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 862 const u8 port_cap[4]) 863{ 864 if (!drm_dp_is_branch(dpcd)) 865 return false; 866 867 if (dpcd[DP_DPCD_REV] < 0x13) 868 return false; 869 870 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 871 case DP_DS_PORT_TYPE_HDMI: 872 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 873 return false; 874 875 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 876 default: 877 return false; 878 } 879} 880EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 881 882/** 883 * drm_dp_downstream_mode() - return a mode for downstream facing port 884 * @dev: DRM device 885 * @dpcd: DisplayPort configuration data 886 * @port_cap: port capabilities 887 * 888 * Provides a suitable mode for downstream facing ports without EDID. 889 * 890 * Returns: A new drm_display_mode on success or NULL on failure 891 */ 892struct drm_display_mode * 893drm_dp_downstream_mode(struct drm_device *dev, 894 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 895 const u8 port_cap[4]) 896 897{ 898 u8 vic; 899 900 if (!drm_dp_is_branch(dpcd)) 901 return NULL; 902 903 if (dpcd[DP_DPCD_REV] < 0x11) 904 return NULL; 905 906 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 907 case DP_DS_PORT_TYPE_NON_EDID: 908 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 909 case DP_DS_NON_EDID_720x480i_60: 910 vic = 6; 911 break; 912 case DP_DS_NON_EDID_720x480i_50: 913 vic = 21; 914 break; 915 case DP_DS_NON_EDID_1920x1080i_60: 916 vic = 5; 917 break; 918 case DP_DS_NON_EDID_1920x1080i_50: 919 vic = 20; 920 break; 921 case DP_DS_NON_EDID_1280x720_60: 922 vic = 4; 923 break; 924 case DP_DS_NON_EDID_1280x720_50: 925 vic = 19; 926 break; 927 default: 928 return NULL; 929 } 930 return drm_display_mode_from_cea_vic(dev, vic); 931 default: 932 return NULL; 933 } 934} 935EXPORT_SYMBOL(drm_dp_downstream_mode); 936 937/** 938 * drm_dp_downstream_id() - identify branch device 939 * @aux: DisplayPort AUX channel 940 * @id: DisplayPort branch device id 941 * 942 * Returns branch device id on success or NULL on failure 943 */ 944int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 945{ 946 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 947} 948EXPORT_SYMBOL(drm_dp_downstream_id); 949 950/** 951 * drm_dp_downstream_debug() - debug DP branch devices 952 * @m: pointer for debugfs file 953 * @dpcd: DisplayPort configuration data 954 * @port_cap: port capabilities 955 * @edid: EDID 956 * @aux: DisplayPort AUX channel 957 * 958 */ 959void drm_dp_downstream_debug(struct seq_file *m, 960 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 961 const u8 port_cap[4], 962 const struct edid *edid, 963 struct drm_dp_aux *aux) 964{ 965 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 966 DP_DETAILED_CAP_INFO_AVAILABLE; 967 int clk; 968 int bpc; 969 char id[7]; 970 int len; 971 uint8_t rev[2]; 972 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 973 bool branch_device = drm_dp_is_branch(dpcd); 974 975 seq_printf(m, "\tDP branch device present: %s\n", 976 branch_device ? "yes" : "no"); 977 978 if (!branch_device) 979 return; 980 981 switch (type) { 982 case DP_DS_PORT_TYPE_DP: 983 seq_puts(m, "\t\tType: DisplayPort\n"); 984 break; 985 case DP_DS_PORT_TYPE_VGA: 986 seq_puts(m, "\t\tType: VGA\n"); 987 break; 988 case DP_DS_PORT_TYPE_DVI: 989 seq_puts(m, "\t\tType: DVI\n"); 990 break; 991 case DP_DS_PORT_TYPE_HDMI: 992 seq_puts(m, "\t\tType: HDMI\n"); 993 break; 994 case DP_DS_PORT_TYPE_NON_EDID: 995 seq_puts(m, "\t\tType: others without EDID support\n"); 996 break; 997 case DP_DS_PORT_TYPE_DP_DUALMODE: 998 seq_puts(m, "\t\tType: DP++\n"); 999 break; 1000 case DP_DS_PORT_TYPE_WIRELESS: 1001 seq_puts(m, "\t\tType: Wireless\n"); 1002 break; 1003 default: 1004 seq_puts(m, "\t\tType: N/A\n"); 1005 } 1006 1007 memset(id, 0, sizeof(id)); 1008 drm_dp_downstream_id(aux, id); 1009 seq_printf(m, "\t\tID: %s\n", id); 1010 1011 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1012 if (len > 0) 1013 seq_printf(m, "\t\tHW: %d.%d\n", 1014 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1015 1016 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1017 if (len > 0) 1018 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1019 1020 if (detailed_cap_info) { 1021 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1022 if (clk > 0) 1023 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1024 1025 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid); 1026 if (clk > 0) 1027 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1028 1029 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid); 1030 if (clk > 0) 1031 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1032 1033 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); 1034 1035 if (bpc > 0) 1036 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1037 } 1038} 1039EXPORT_SYMBOL(drm_dp_downstream_debug); 1040 1041/** 1042 * drm_dp_subconnector_type() - get DP branch device type 1043 * @dpcd: DisplayPort configuration data 1044 * @port_cap: port capabilities 1045 */ 1046enum drm_mode_subconnector 1047drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1048 const u8 port_cap[4]) 1049{ 1050 int type; 1051 if (!drm_dp_is_branch(dpcd)) 1052 return DRM_MODE_SUBCONNECTOR_Native; 1053 /* DP 1.0 approach */ 1054 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1055 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1056 DP_DWN_STRM_PORT_TYPE_MASK; 1057 1058 switch (type) { 1059 case DP_DWN_STRM_PORT_TYPE_TMDS: 1060 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1061 return DRM_MODE_SUBCONNECTOR_DVID; 1062 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1063 /* Can be VGA or DVI-A, VGA is more popular */ 1064 return DRM_MODE_SUBCONNECTOR_VGA; 1065 case DP_DWN_STRM_PORT_TYPE_DP: 1066 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1067 case DP_DWN_STRM_PORT_TYPE_OTHER: 1068 default: 1069 return DRM_MODE_SUBCONNECTOR_Unknown; 1070 } 1071 } 1072 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1073 1074 switch (type) { 1075 case DP_DS_PORT_TYPE_DP: 1076 case DP_DS_PORT_TYPE_DP_DUALMODE: 1077 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1078 case DP_DS_PORT_TYPE_VGA: 1079 return DRM_MODE_SUBCONNECTOR_VGA; 1080 case DP_DS_PORT_TYPE_DVI: 1081 return DRM_MODE_SUBCONNECTOR_DVID; 1082 case DP_DS_PORT_TYPE_HDMI: 1083 return DRM_MODE_SUBCONNECTOR_HDMIA; 1084 case DP_DS_PORT_TYPE_WIRELESS: 1085 return DRM_MODE_SUBCONNECTOR_Wireless; 1086 case DP_DS_PORT_TYPE_NON_EDID: 1087 default: 1088 return DRM_MODE_SUBCONNECTOR_Unknown; 1089 } 1090} 1091EXPORT_SYMBOL(drm_dp_subconnector_type); 1092 1093/** 1094 * drm_mode_set_dp_subconnector_property - set subconnector for DP connector 1095 * @connector: connector to set property on 1096 * @status: connector status 1097 * @dpcd: DisplayPort configuration data 1098 * @port_cap: port capabilities 1099 * 1100 * Called by a driver on every detect event. 1101 */ 1102void drm_dp_set_subconnector_property(struct drm_connector *connector, 1103 enum drm_connector_status status, 1104 const u8 *dpcd, 1105 const u8 port_cap[4]) 1106{ 1107 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1108 1109 if (status == connector_status_connected) 1110 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1111 drm_object_property_set_value(&connector->base, 1112 connector->dev->mode_config.dp_subconnector_property, 1113 subconnector); 1114} 1115EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1116 1117/** 1118 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1119 * count 1120 * @connector: The DRM connector to check 1121 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1122 * @desc: A cached copy of the connector's DP descriptor 1123 * 1124 * See also: drm_dp_read_sink_count() 1125 * 1126 * Returns: %True if the (e)DP connector has a valid sink count that should 1127 * be probed, %false otherwise. 1128 */ 1129bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1130 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1131 const struct drm_dp_desc *desc) 1132{ 1133 /* Some eDP panels don't set a valid value for the sink count */ 1134 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1135 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1136 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1137 !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT); 1138} 1139EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1140 1141/** 1142 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1143 * @aux: The DP AUX channel to use 1144 * 1145 * See also: drm_dp_read_sink_count_cap() 1146 * 1147 * Returns: The current sink count reported by @aux, or a negative error code 1148 * otherwise. 1149 */ 1150int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1151{ 1152 u8 count; 1153 int ret; 1154 1155 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1156 if (ret < 0) 1157 return ret; 1158 if (ret != 1) 1159 return -EIO; 1160 1161 return DP_GET_SINK_COUNT(count); 1162} 1163EXPORT_SYMBOL(drm_dp_read_sink_count); 1164 1165/* 1166 * I2C-over-AUX implementation 1167 */ 1168 1169static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1170{ 1171 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1172 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1173 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1174 I2C_FUNC_10BIT_ADDR; 1175} 1176 1177static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1178{ 1179 /* 1180 * In case of i2c defer or short i2c ack reply to a write, 1181 * we need to switch to WRITE_STATUS_UPDATE to drain the 1182 * rest of the message 1183 */ 1184 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1185 msg->request &= DP_AUX_I2C_MOT; 1186 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1187 } 1188} 1189 1190#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1191#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1192#define AUX_STOP_LEN 4 1193#define AUX_CMD_LEN 4 1194#define AUX_ADDRESS_LEN 20 1195#define AUX_REPLY_PAD_LEN 4 1196#define AUX_LENGTH_LEN 8 1197 1198/* 1199 * Calculate the duration of the AUX request/reply in usec. Gives the 1200 * "best" case estimate, ie. successful while as short as possible. 1201 */ 1202static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1203{ 1204 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1205 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1206 1207 if ((msg->request & DP_AUX_I2C_READ) == 0) 1208 len += msg->size * 8; 1209 1210 return len; 1211} 1212 1213static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1214{ 1215 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1216 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1217 1218 /* 1219 * For read we expect what was asked. For writes there will 1220 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1221 */ 1222 if (msg->request & DP_AUX_I2C_READ) 1223 len += msg->size * 8; 1224 1225 return len; 1226} 1227 1228#define I2C_START_LEN 1 1229#define I2C_STOP_LEN 1 1230#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1231#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1232 1233/* 1234 * Calculate the length of the i2c transfer in usec, assuming 1235 * the i2c bus speed is as specified. Gives the the "worst" 1236 * case estimate, ie. successful while as long as possible. 1237 * Doesn't account the the "MOT" bit, and instead assumes each 1238 * message includes a START, ADDRESS and STOP. Neither does it 1239 * account for additional random variables such as clock stretching. 1240 */ 1241static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1242 int i2c_speed_khz) 1243{ 1244 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1245 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1246 msg->size * I2C_DATA_LEN + 1247 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1248} 1249 1250/* 1251 * Deterine how many retries should be attempted to successfully transfer 1252 * the specified message, based on the estimated durations of the 1253 * i2c and AUX transfers. 1254 */ 1255static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1256 int i2c_speed_khz) 1257{ 1258 int aux_time_us = drm_dp_aux_req_duration(msg) + 1259 drm_dp_aux_reply_duration(msg); 1260 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1261 1262 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1263} 1264 1265/* 1266 * FIXME currently assumes 10 kHz as some real world devices seem 1267 * to require it. We should query/set the speed via DPCD if supported. 1268 */ 1269static int dp_aux_i2c_speed_khz __read_mostly = 10; 1270module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1271MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1272 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1273 1274/* 1275 * Transfer a single I2C-over-AUX message and handle various error conditions, 1276 * retrying the transaction as appropriate. It is assumed that the 1277 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1278 * reply field. 1279 * 1280 * Returns bytes transferred on success, or a negative error code on failure. 1281 */ 1282static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1283{ 1284 unsigned int retry, defer_i2c; 1285 int ret; 1286 /* 1287 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1288 * is required to retry at least seven times upon receiving AUX_DEFER 1289 * before giving up the AUX transaction. 1290 * 1291 * We also try to account for the i2c bus speed. 1292 */ 1293 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1294 1295 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1296 ret = aux->transfer(aux, msg); 1297 if (ret < 0) { 1298 if (ret == -EBUSY) 1299 continue; 1300 1301 /* 1302 * While timeouts can be errors, they're usually normal 1303 * behavior (for instance, when a driver tries to 1304 * communicate with a non-existant DisplayPort device). 1305 * Avoid spamming the kernel log with timeout errors. 1306 */ 1307 if (ret == -ETIMEDOUT) 1308 DRM_DEBUG_KMS_RATELIMITED("%s: transaction timed out\n", 1309 aux->name); 1310 else 1311 DRM_DEBUG_KMS("%s: transaction failed: %d\n", 1312 aux->name, ret); 1313 return ret; 1314 } 1315 1316 1317 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1318 case DP_AUX_NATIVE_REPLY_ACK: 1319 /* 1320 * For I2C-over-AUX transactions this isn't enough, we 1321 * need to check for the I2C ACK reply. 1322 */ 1323 break; 1324 1325 case DP_AUX_NATIVE_REPLY_NACK: 1326 DRM_DEBUG_KMS("%s: native nack (result=%d, size=%zu)\n", 1327 aux->name, ret, msg->size); 1328 return -EREMOTEIO; 1329 1330 case DP_AUX_NATIVE_REPLY_DEFER: 1331 DRM_DEBUG_KMS("%s: native defer\n", aux->name); 1332 /* 1333 * We could check for I2C bit rate capabilities and if 1334 * available adjust this interval. We could also be 1335 * more careful with DP-to-legacy adapters where a 1336 * long legacy cable may force very low I2C bit rates. 1337 * 1338 * For now just defer for long enough to hopefully be 1339 * safe for all use-cases. 1340 */ 1341 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1342 continue; 1343 1344 default: 1345 DRM_ERROR("%s: invalid native reply %#04x\n", 1346 aux->name, msg->reply); 1347 return -EREMOTEIO; 1348 } 1349 1350 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1351 case DP_AUX_I2C_REPLY_ACK: 1352 /* 1353 * Both native ACK and I2C ACK replies received. We 1354 * can assume the transfer was successful. 1355 */ 1356 if (ret != msg->size) 1357 drm_dp_i2c_msg_write_status_update(msg); 1358 return ret; 1359 1360 case DP_AUX_I2C_REPLY_NACK: 1361 DRM_DEBUG_KMS("%s: I2C nack (result=%d, size=%zu)\n", 1362 aux->name, ret, msg->size); 1363 aux->i2c_nack_count++; 1364 return -EREMOTEIO; 1365 1366 case DP_AUX_I2C_REPLY_DEFER: 1367 DRM_DEBUG_KMS("%s: I2C defer\n", aux->name); 1368 /* DP Compliance Test 4.2.2.5 Requirement: 1369 * Must have at least 7 retries for I2C defers on the 1370 * transaction to pass this test 1371 */ 1372 aux->i2c_defer_count++; 1373 if (defer_i2c < 7) 1374 defer_i2c++; 1375 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1376 drm_dp_i2c_msg_write_status_update(msg); 1377 1378 continue; 1379 1380 default: 1381 DRM_ERROR("%s: invalid I2C reply %#04x\n", 1382 aux->name, msg->reply); 1383 return -EREMOTEIO; 1384 } 1385 } 1386 1387 DRM_DEBUG_KMS("%s: Too many retries, giving up\n", aux->name); 1388 return -EREMOTEIO; 1389} 1390 1391static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1392 const struct i2c_msg *i2c_msg) 1393{ 1394 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1395 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1396 if (!(i2c_msg->flags & I2C_M_STOP)) 1397 msg->request |= DP_AUX_I2C_MOT; 1398} 1399 1400/* 1401 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1402 * 1403 * Returns an error code on failure, or a recommended transfer size on success. 1404 */ 1405static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1406{ 1407 int err, ret = orig_msg->size; 1408 struct drm_dp_aux_msg msg = *orig_msg; 1409 1410 while (msg.size > 0) { 1411 err = drm_dp_i2c_do_msg(aux, &msg); 1412 if (err <= 0) 1413 return err == 0 ? -EPROTO : err; 1414 1415 if (err < msg.size && err < ret) { 1416 DRM_DEBUG_KMS("%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1417 aux->name, msg.size, err); 1418 ret = err; 1419 } 1420 1421 msg.size -= err; 1422 msg.buffer += err; 1423 } 1424 1425 return ret; 1426} 1427 1428/* 1429 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 1430 * packets to be as large as possible. If not, the I2C transactions never 1431 * succeed. Hence the default is maximum. 1432 */ 1433static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 1434module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 1435MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 1436 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 1437 1438static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 1439 int num) 1440{ 1441 struct drm_dp_aux *aux = adapter->algo_data; 1442 unsigned int i, j; 1443 unsigned transfer_size; 1444 struct drm_dp_aux_msg msg; 1445 int err = 0; 1446 1447 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 1448 1449 memset(&msg, 0, sizeof(msg)); 1450 1451 for (i = 0; i < num; i++) { 1452 msg.address = msgs[i].addr; 1453 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1454 /* Send a bare address packet to start the transaction. 1455 * Zero sized messages specify an address only (bare 1456 * address) transaction. 1457 */ 1458 msg.buffer = NULL; 1459 msg.size = 0; 1460 err = drm_dp_i2c_do_msg(aux, &msg); 1461 1462 /* 1463 * Reset msg.request in case in case it got 1464 * changed into a WRITE_STATUS_UPDATE. 1465 */ 1466 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1467 1468 if (err < 0) 1469 break; 1470 /* We want each transaction to be as large as possible, but 1471 * we'll go to smaller sizes if the hardware gives us a 1472 * short reply. 1473 */ 1474 transfer_size = dp_aux_i2c_transfer_size; 1475 for (j = 0; j < msgs[i].len; j += msg.size) { 1476 msg.buffer = msgs[i].buf + j; 1477 msg.size = min(transfer_size, msgs[i].len - j); 1478 1479 err = drm_dp_i2c_drain_msg(aux, &msg); 1480 1481 /* 1482 * Reset msg.request in case in case it got 1483 * changed into a WRITE_STATUS_UPDATE. 1484 */ 1485 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 1486 1487 if (err < 0) 1488 break; 1489 transfer_size = err; 1490 } 1491 if (err < 0) 1492 break; 1493 } 1494 if (err >= 0) 1495 err = num; 1496 /* Send a bare address packet to close out the transaction. 1497 * Zero sized messages specify an address only (bare 1498 * address) transaction. 1499 */ 1500 msg.request &= ~DP_AUX_I2C_MOT; 1501 msg.buffer = NULL; 1502 msg.size = 0; 1503 (void)drm_dp_i2c_do_msg(aux, &msg); 1504 1505 return err; 1506} 1507 1508static const struct i2c_algorithm drm_dp_i2c_algo = { 1509 .functionality = drm_dp_i2c_functionality, 1510 .master_xfer = drm_dp_i2c_xfer, 1511}; 1512 1513static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 1514{ 1515 return container_of(i2c, struct drm_dp_aux, ddc); 1516} 1517 1518static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 1519{ 1520 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 1521} 1522 1523static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 1524{ 1525 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 1526} 1527 1528static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 1529{ 1530 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 1531} 1532 1533static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 1534 .lock_bus = lock_bus, 1535 .trylock_bus = trylock_bus, 1536 .unlock_bus = unlock_bus, 1537}; 1538 1539static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 1540{ 1541 u8 buf, count; 1542 int ret; 1543 1544 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1545 if (ret < 0) 1546 return ret; 1547 1548 WARN_ON(!(buf & DP_TEST_SINK_START)); 1549 1550 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 1551 if (ret < 0) 1552 return ret; 1553 1554 count = buf & DP_TEST_COUNT_MASK; 1555 if (count == aux->crc_count) 1556 return -EAGAIN; /* No CRC yet */ 1557 1558 aux->crc_count = count; 1559 1560 /* 1561 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 1562 * per component (RGB or CrYCb). 1563 */ 1564 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 1565 if (ret < 0) 1566 return ret; 1567 1568 return 0; 1569} 1570 1571static void drm_dp_aux_crc_work(struct work_struct *work) 1572{ 1573 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 1574 crc_work); 1575 struct drm_crtc *crtc; 1576 u8 crc_bytes[6]; 1577 uint32_t crcs[3]; 1578 int ret; 1579 1580 if (WARN_ON(!aux->crtc)) 1581 return; 1582 1583 crtc = aux->crtc; 1584 while (crtc->crc.opened) { 1585 drm_crtc_wait_one_vblank(crtc); 1586 if (!crtc->crc.opened) 1587 break; 1588 1589 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1590 if (ret == -EAGAIN) { 1591 usleep_range(1000, 2000); 1592 ret = drm_dp_aux_get_crc(aux, crc_bytes); 1593 } 1594 1595 if (ret == -EAGAIN) { 1596 DRM_DEBUG_KMS("%s: Get CRC failed after retrying: %d\n", 1597 aux->name, ret); 1598 continue; 1599 } else if (ret) { 1600 DRM_DEBUG_KMS("%s: Failed to get a CRC: %d\n", 1601 aux->name, ret); 1602 continue; 1603 } 1604 1605 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 1606 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 1607 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 1608 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 1609 } 1610} 1611 1612/** 1613 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 1614 * @aux: DisplayPort AUX channel 1615 * 1616 * Used for remote aux channel in general. Merely initialize the crc work 1617 * struct. 1618 */ 1619void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 1620{ 1621 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1622} 1623EXPORT_SYMBOL(drm_dp_remote_aux_init); 1624 1625/** 1626 * drm_dp_aux_init() - minimally initialise an aux channel 1627 * @aux: DisplayPort AUX channel 1628 * 1629 * If you need to use the drm_dp_aux's i2c adapter prior to registering it 1630 * with the outside world, call drm_dp_aux_init() first. You must still 1631 * call drm_dp_aux_register() once the connector has been registered to 1632 * allow userspace access to the auxiliary DP channel. 1633 */ 1634void drm_dp_aux_init(struct drm_dp_aux *aux) 1635{ 1636 mutex_init(&aux->hw_mutex); 1637 mutex_init(&aux->cec.lock); 1638 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 1639 1640 aux->ddc.algo = &drm_dp_i2c_algo; 1641 aux->ddc.algo_data = aux; 1642 aux->ddc.retries = 3; 1643 1644 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 1645} 1646EXPORT_SYMBOL(drm_dp_aux_init); 1647 1648/** 1649 * drm_dp_aux_register() - initialise and register aux channel 1650 * @aux: DisplayPort AUX channel 1651 * 1652 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. 1653 * This should only be called when the underlying &struct drm_connector is 1654 * initialiazed already. Therefore the best place to call this is from 1655 * &drm_connector_funcs.late_register. Not that drivers which don't follow this 1656 * will Oops when CONFIG_DRM_DP_AUX_CHARDEV is enabled. 1657 * 1658 * Drivers which need to use the aux channel before that point (e.g. at driver 1659 * load time, before drm_dev_register() has been called) need to call 1660 * drm_dp_aux_init(). 1661 * 1662 * Returns 0 on success or a negative error code on failure. 1663 */ 1664int drm_dp_aux_register(struct drm_dp_aux *aux) 1665{ 1666 int ret; 1667 1668 if (!aux->ddc.algo) 1669 drm_dp_aux_init(aux); 1670 1671 aux->ddc.class = I2C_CLASS_DDC; 1672 aux->ddc.owner = THIS_MODULE; 1673 aux->ddc.dev.parent = aux->dev; 1674 1675 strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 1676 sizeof(aux->ddc.name)); 1677 1678 ret = drm_dp_aux_register_devnode(aux); 1679 if (ret) 1680 return ret; 1681 1682 ret = i2c_add_adapter(&aux->ddc); 1683 if (ret) { 1684 drm_dp_aux_unregister_devnode(aux); 1685 return ret; 1686 } 1687 1688 return 0; 1689} 1690EXPORT_SYMBOL(drm_dp_aux_register); 1691 1692/** 1693 * drm_dp_aux_unregister() - unregister an AUX adapter 1694 * @aux: DisplayPort AUX channel 1695 */ 1696void drm_dp_aux_unregister(struct drm_dp_aux *aux) 1697{ 1698 drm_dp_aux_unregister_devnode(aux); 1699 i2c_del_adapter(&aux->ddc); 1700} 1701EXPORT_SYMBOL(drm_dp_aux_unregister); 1702 1703#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 1704 1705/** 1706 * drm_dp_psr_setup_time() - PSR setup in time usec 1707 * @psr_cap: PSR capabilities from DPCD 1708 * 1709 * Returns: 1710 * PSR setup time for the panel in microseconds, negative 1711 * error code on failure. 1712 */ 1713int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 1714{ 1715 static const u16 psr_setup_time_us[] = { 1716 PSR_SETUP_TIME(330), 1717 PSR_SETUP_TIME(275), 1718 PSR_SETUP_TIME(220), 1719 PSR_SETUP_TIME(165), 1720 PSR_SETUP_TIME(110), 1721 PSR_SETUP_TIME(55), 1722 PSR_SETUP_TIME(0), 1723 }; 1724 int i; 1725 1726 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 1727 if (i >= ARRAY_SIZE(psr_setup_time_us)) 1728 return -EINVAL; 1729 1730 return psr_setup_time_us[i]; 1731} 1732EXPORT_SYMBOL(drm_dp_psr_setup_time); 1733 1734#undef PSR_SETUP_TIME 1735 1736/** 1737 * drm_dp_start_crc() - start capture of frame CRCs 1738 * @aux: DisplayPort AUX channel 1739 * @crtc: CRTC displaying the frames whose CRCs are to be captured 1740 * 1741 * Returns 0 on success or a negative error code on failure. 1742 */ 1743int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 1744{ 1745 u8 buf; 1746 int ret; 1747 1748 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1749 if (ret < 0) 1750 return ret; 1751 1752 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 1753 if (ret < 0) 1754 return ret; 1755 1756 aux->crc_count = 0; 1757 aux->crtc = crtc; 1758 schedule_work(&aux->crc_work); 1759 1760 return 0; 1761} 1762EXPORT_SYMBOL(drm_dp_start_crc); 1763 1764/** 1765 * drm_dp_stop_crc() - stop capture of frame CRCs 1766 * @aux: DisplayPort AUX channel 1767 * 1768 * Returns 0 on success or a negative error code on failure. 1769 */ 1770int drm_dp_stop_crc(struct drm_dp_aux *aux) 1771{ 1772 u8 buf; 1773 int ret; 1774 1775 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 1776 if (ret < 0) 1777 return ret; 1778 1779 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 1780 if (ret < 0) 1781 return ret; 1782 1783 flush_work(&aux->crc_work); 1784 aux->crtc = NULL; 1785 1786 return 0; 1787} 1788EXPORT_SYMBOL(drm_dp_stop_crc); 1789 1790struct dpcd_quirk { 1791 u8 oui[3]; 1792 u8 device_id[6]; 1793 bool is_branch; 1794 u32 quirks; 1795}; 1796 1797#define OUI(first, second, third) { (first), (second), (third) } 1798#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 1799 { (first), (second), (third), (fourth), (fifth), (sixth) } 1800 1801#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 1802 1803static const struct dpcd_quirk dpcd_quirk_list[] = { 1804 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 1805 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 1806 /* LG LP140WF6-SPM1 eDP panel */ 1807 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 1808 /* Apple panels need some additional handling to support PSR */ 1809 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 1810 /* CH7511 seems to leave SINK_COUNT zeroed */ 1811 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 1812 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 1813 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 1814 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 1815 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 1816}; 1817 1818#undef OUI 1819 1820/* 1821 * Get a bit mask of DPCD quirks for the sink/branch device identified by 1822 * ident. The quirk data is shared but it's up to the drivers to act on the 1823 * data. 1824 * 1825 * For now, only the OUI (first three bytes) is used, but this may be extended 1826 * to device identification string and hardware/firmware revisions later. 1827 */ 1828static u32 1829drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 1830{ 1831 const struct dpcd_quirk *quirk; 1832 u32 quirks = 0; 1833 int i; 1834 u8 any_device[] = DEVICE_ID_ANY; 1835 1836 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 1837 quirk = &dpcd_quirk_list[i]; 1838 1839 if (quirk->is_branch != is_branch) 1840 continue; 1841 1842 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 1843 continue; 1844 1845 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 1846 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 1847 continue; 1848 1849 quirks |= quirk->quirks; 1850 } 1851 1852 return quirks; 1853} 1854 1855#undef DEVICE_ID_ANY 1856#undef DEVICE_ID 1857 1858struct edid_quirk { 1859 u8 mfg_id[2]; 1860 u8 prod_id[2]; 1861 u32 quirks; 1862}; 1863 1864#define MFG(first, second) { (first), (second) } 1865#define PROD_ID(first, second) { (first), (second) } 1866 1867/* 1868 * Some devices have unreliable OUIDs where they don't set the device ID 1869 * correctly, and as a result we need to use the EDID for finding additional 1870 * DP quirks in such cases. 1871 */ 1872static const struct edid_quirk edid_quirk_list[] = { 1873 /* Optional 4K AMOLED panel in the ThinkPad X1 Extreme 2nd Generation 1874 * only supports DPCD backlight controls 1875 */ 1876 { MFG(0x4c, 0x83), PROD_ID(0x41, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1877 /* 1878 * Some Dell CML 2020 systems have panels support both AUX and PWM 1879 * backlight control, and some only support AUX backlight control. All 1880 * said panels start up in AUX mode by default, and we don't have any 1881 * support for disabling HDR mode on these panels which would be 1882 * required to switch to PWM backlight control mode (plus, I'm not 1883 * even sure we want PWM backlight controls over DPCD backlight 1884 * controls anyway...). Until we have a better way of detecting these, 1885 * force DPCD backlight mode on all of them. 1886 */ 1887 { MFG(0x06, 0xaf), PROD_ID(0x9b, 0x32), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1888 { MFG(0x06, 0xaf), PROD_ID(0xeb, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1889 { MFG(0x4d, 0x10), PROD_ID(0xc7, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1890 { MFG(0x4d, 0x10), PROD_ID(0xe6, 0x14), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1891 { MFG(0x4c, 0x83), PROD_ID(0x47, 0x41), BIT(DP_QUIRK_FORCE_DPCD_BACKLIGHT) }, 1892}; 1893 1894#undef MFG 1895#undef PROD_ID 1896 1897/** 1898 * drm_dp_get_edid_quirks() - Check the EDID of a DP device to find additional 1899 * DP-specific quirks 1900 * @edid: The EDID to check 1901 * 1902 * While OUIDs are meant to be used to recognize a DisplayPort device, a lot 1903 * of manufacturers don't seem to like following standards and neglect to fill 1904 * the dev-ID in, making it impossible to only use OUIDs for determining 1905 * quirks in some cases. This function can be used to check the EDID and look 1906 * up any additional DP quirks. The bits returned by this function correspond 1907 * to the quirk bits in &drm_dp_quirk. 1908 * 1909 * Returns: a bitmask of quirks, if any. The driver can check this using 1910 * drm_dp_has_quirk(). 1911 */ 1912u32 drm_dp_get_edid_quirks(const struct edid *edid) 1913{ 1914 const struct edid_quirk *quirk; 1915 u32 quirks = 0; 1916 int i; 1917 1918 if (!edid) 1919 return 0; 1920 1921 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1922 quirk = &edid_quirk_list[i]; 1923 if (memcmp(quirk->mfg_id, edid->mfg_id, 1924 sizeof(edid->mfg_id)) == 0 && 1925 memcmp(quirk->prod_id, edid->prod_code, 1926 sizeof(edid->prod_code)) == 0) 1927 quirks |= quirk->quirks; 1928 } 1929 1930 DRM_DEBUG_KMS("DP sink: EDID mfg %*phD prod-ID %*phD quirks: 0x%04x\n", 1931 (int)sizeof(edid->mfg_id), edid->mfg_id, 1932 (int)sizeof(edid->prod_code), edid->prod_code, quirks); 1933 1934 return quirks; 1935} 1936EXPORT_SYMBOL(drm_dp_get_edid_quirks); 1937 1938/** 1939 * drm_dp_read_desc - read sink/branch descriptor from DPCD 1940 * @aux: DisplayPort AUX channel 1941 * @desc: Device descriptor to fill from DPCD 1942 * @is_branch: true for branch devices, false for sink devices 1943 * 1944 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 1945 * identification. 1946 * 1947 * Returns 0 on success or a negative error code on failure. 1948 */ 1949int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 1950 bool is_branch) 1951{ 1952 struct drm_dp_dpcd_ident *ident = &desc->ident; 1953 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 1954 int ret, dev_id_len; 1955 1956 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 1957 if (ret < 0) 1958 return ret; 1959 1960 desc->quirks = drm_dp_get_quirks(ident, is_branch); 1961 1962 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); 1963 1964 DRM_DEBUG_KMS("%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 1965 aux->name, is_branch ? "branch" : "sink", 1966 (int)sizeof(ident->oui), ident->oui, 1967 dev_id_len, ident->device_id, 1968 ident->hw_rev >> 4, ident->hw_rev & 0xf, 1969 ident->sw_major_rev, ident->sw_minor_rev, 1970 desc->quirks); 1971 1972 return 0; 1973} 1974EXPORT_SYMBOL(drm_dp_read_desc); 1975 1976/** 1977 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 1978 * supported by the DSC sink. 1979 * @dsc_dpcd: DSC capabilities from DPCD 1980 * @is_edp: true if its eDP, false for DP 1981 * 1982 * Read the slice capabilities DPCD register from DSC sink to get 1983 * the maximum slice count supported. This is used to populate 1984 * the DSC parameters in the &struct drm_dsc_config by the driver. 1985 * Driver creates an infoframe using these parameters to populate 1986 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 1987 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 1988 * 1989 * Returns: 1990 * Maximum slice count supported by DSC sink or 0 its invalid 1991 */ 1992u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 1993 bool is_edp) 1994{ 1995 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 1996 1997 if (is_edp) { 1998 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 1999 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2000 return 4; 2001 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2002 return 2; 2003 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2004 return 1; 2005 } else { 2006 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2007 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2008 2009 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2010 return 24; 2011 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2012 return 20; 2013 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2014 return 16; 2015 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2016 return 12; 2017 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2018 return 10; 2019 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2020 return 8; 2021 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2022 return 6; 2023 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2024 return 4; 2025 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2026 return 2; 2027 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2028 return 1; 2029 } 2030 2031 return 0; 2032} 2033EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2034 2035/** 2036 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2037 * @dsc_dpcd: DSC capabilities from DPCD 2038 * 2039 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2040 * number of bits of precision within the decoder line buffer supported by 2041 * the DSC sink. This is used to populate the DSC parameters in the 2042 * &struct drm_dsc_config by the driver. 2043 * Driver creates an infoframe using these parameters to populate 2044 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2045 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2046 * 2047 * Returns: 2048 * Line buffer depth supported by DSC panel or 0 its invalid 2049 */ 2050u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2051{ 2052 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2053 2054 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2055 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2056 return 9; 2057 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2058 return 10; 2059 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2060 return 11; 2061 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2062 return 12; 2063 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2064 return 13; 2065 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2066 return 14; 2067 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2068 return 15; 2069 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2070 return 16; 2071 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2072 return 8; 2073 } 2074 2075 return 0; 2076} 2077EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2078 2079/** 2080 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2081 * values supported by the DSC sink. 2082 * @dsc_dpcd: DSC capabilities from DPCD 2083 * @dsc_bpc: An array to be filled by this helper with supported 2084 * input bpcs. 2085 * 2086 * Read the DSC DPCD from the sink device to parse the supported bits per 2087 * component values. This is used to populate the DSC parameters 2088 * in the &struct drm_dsc_config by the driver. 2089 * Driver creates an infoframe using these parameters to populate 2090 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2091 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2092 * 2093 * Returns: 2094 * Number of input BPC values parsed from the DPCD 2095 */ 2096int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2097 u8 dsc_bpc[3]) 2098{ 2099 int num_bpc = 0; 2100 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2101 2102 if (color_depth & DP_DSC_12_BPC) 2103 dsc_bpc[num_bpc++] = 12; 2104 if (color_depth & DP_DSC_10_BPC) 2105 dsc_bpc[num_bpc++] = 10; 2106 if (color_depth & DP_DSC_8_BPC) 2107 dsc_bpc[num_bpc++] = 8; 2108 2109 return num_bpc; 2110} 2111EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2112 2113/** 2114 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2115 * @aux: DisplayPort AUX channel 2116 * @data: DP phy compliance test parameters. 2117 * 2118 * Returns 0 on success or a negative error code on failure. 2119 */ 2120int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2121 struct drm_dp_phy_test_params *data) 2122{ 2123 int err; 2124 u8 rate, lanes; 2125 2126 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2127 if (err < 0) 2128 return err; 2129 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2130 2131 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2132 if (err < 0) 2133 return err; 2134 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2135 2136 if (lanes & DP_ENHANCED_FRAME_CAP) 2137 data->enhanced_frame_cap = true; 2138 2139 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2140 if (err < 0) 2141 return err; 2142 2143 switch (data->phy_pattern) { 2144 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2145 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2146 &data->custom80, sizeof(data->custom80)); 2147 if (err < 0) 2148 return err; 2149 2150 break; 2151 case DP_PHY_TEST_PATTERN_CP2520: 2152 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2153 &data->hbr2_reset, 2154 sizeof(data->hbr2_reset)); 2155 if (err < 0) 2156 return err; 2157 } 2158 2159 return 0; 2160} 2161EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2162 2163/** 2164 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2165 * @aux: DisplayPort AUX channel 2166 * @data: DP phy compliance test parameters. 2167 * @dp_rev: DP revision to use for compliance testing 2168 * 2169 * Returns 0 on success or a negative error code on failure. 2170 */ 2171int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2172 struct drm_dp_phy_test_params *data, u8 dp_rev) 2173{ 2174 int err, i; 2175 u8 test_pattern; 2176 2177 test_pattern = data->phy_pattern; 2178 if (dp_rev < 0x12) { 2179 test_pattern = (test_pattern << 2) & 2180 DP_LINK_QUAL_PATTERN_11_MASK; 2181 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2182 test_pattern); 2183 if (err < 0) 2184 return err; 2185 } else { 2186 for (i = 0; i < data->num_lanes; i++) { 2187 err = drm_dp_dpcd_writeb(aux, 2188 DP_LINK_QUAL_LANE0_SET + i, 2189 test_pattern); 2190 if (err < 0) 2191 return err; 2192 } 2193 } 2194 2195 return 0; 2196} 2197EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2198 2199static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2200{ 2201 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2202 return "Invalid"; 2203 2204 switch (pixelformat) { 2205 case DP_PIXELFORMAT_RGB: 2206 return "RGB"; 2207 case DP_PIXELFORMAT_YUV444: 2208 return "YUV444"; 2209 case DP_PIXELFORMAT_YUV422: 2210 return "YUV422"; 2211 case DP_PIXELFORMAT_YUV420: 2212 return "YUV420"; 2213 case DP_PIXELFORMAT_Y_ONLY: 2214 return "Y_ONLY"; 2215 case DP_PIXELFORMAT_RAW: 2216 return "RAW"; 2217 default: 2218 return "Reserved"; 2219 } 2220} 2221 2222static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2223 enum dp_colorimetry colorimetry) 2224{ 2225 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2226 return "Invalid"; 2227 2228 switch (colorimetry) { 2229 case DP_COLORIMETRY_DEFAULT: 2230 switch (pixelformat) { 2231 case DP_PIXELFORMAT_RGB: 2232 return "sRGB"; 2233 case DP_PIXELFORMAT_YUV444: 2234 case DP_PIXELFORMAT_YUV422: 2235 case DP_PIXELFORMAT_YUV420: 2236 return "BT.601"; 2237 case DP_PIXELFORMAT_Y_ONLY: 2238 return "DICOM PS3.14"; 2239 case DP_PIXELFORMAT_RAW: 2240 return "Custom Color Profile"; 2241 default: 2242 return "Reserved"; 2243 } 2244 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2245 switch (pixelformat) { 2246 case DP_PIXELFORMAT_RGB: 2247 return "Wide Fixed"; 2248 case DP_PIXELFORMAT_YUV444: 2249 case DP_PIXELFORMAT_YUV422: 2250 case DP_PIXELFORMAT_YUV420: 2251 return "BT.709"; 2252 default: 2253 return "Reserved"; 2254 } 2255 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 2256 switch (pixelformat) { 2257 case DP_PIXELFORMAT_RGB: 2258 return "Wide Float"; 2259 case DP_PIXELFORMAT_YUV444: 2260 case DP_PIXELFORMAT_YUV422: 2261 case DP_PIXELFORMAT_YUV420: 2262 return "xvYCC 601"; 2263 default: 2264 return "Reserved"; 2265 } 2266 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 2267 switch (pixelformat) { 2268 case DP_PIXELFORMAT_RGB: 2269 return "OpRGB"; 2270 case DP_PIXELFORMAT_YUV444: 2271 case DP_PIXELFORMAT_YUV422: 2272 case DP_PIXELFORMAT_YUV420: 2273 return "xvYCC 709"; 2274 default: 2275 return "Reserved"; 2276 } 2277 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 2278 switch (pixelformat) { 2279 case DP_PIXELFORMAT_RGB: 2280 return "DCI-P3"; 2281 case DP_PIXELFORMAT_YUV444: 2282 case DP_PIXELFORMAT_YUV422: 2283 case DP_PIXELFORMAT_YUV420: 2284 return "sYCC 601"; 2285 default: 2286 return "Reserved"; 2287 } 2288 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 2289 switch (pixelformat) { 2290 case DP_PIXELFORMAT_RGB: 2291 return "Custom Profile"; 2292 case DP_PIXELFORMAT_YUV444: 2293 case DP_PIXELFORMAT_YUV422: 2294 case DP_PIXELFORMAT_YUV420: 2295 return "OpYCC 601"; 2296 default: 2297 return "Reserved"; 2298 } 2299 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 2300 switch (pixelformat) { 2301 case DP_PIXELFORMAT_RGB: 2302 return "BT.2020 RGB"; 2303 case DP_PIXELFORMAT_YUV444: 2304 case DP_PIXELFORMAT_YUV422: 2305 case DP_PIXELFORMAT_YUV420: 2306 return "BT.2020 CYCC"; 2307 default: 2308 return "Reserved"; 2309 } 2310 case DP_COLORIMETRY_BT2020_YCC: 2311 switch (pixelformat) { 2312 case DP_PIXELFORMAT_YUV444: 2313 case DP_PIXELFORMAT_YUV422: 2314 case DP_PIXELFORMAT_YUV420: 2315 return "BT.2020 YCC"; 2316 default: 2317 return "Reserved"; 2318 } 2319 default: 2320 return "Invalid"; 2321 } 2322} 2323 2324static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 2325{ 2326 switch (dynamic_range) { 2327 case DP_DYNAMIC_RANGE_VESA: 2328 return "VESA range"; 2329 case DP_DYNAMIC_RANGE_CTA: 2330 return "CTA range"; 2331 default: 2332 return "Invalid"; 2333 } 2334} 2335 2336static const char *dp_content_type_get_name(enum dp_content_type content_type) 2337{ 2338 switch (content_type) { 2339 case DP_CONTENT_TYPE_NOT_DEFINED: 2340 return "Not defined"; 2341 case DP_CONTENT_TYPE_GRAPHICS: 2342 return "Graphics"; 2343 case DP_CONTENT_TYPE_PHOTO: 2344 return "Photo"; 2345 case DP_CONTENT_TYPE_VIDEO: 2346 return "Video"; 2347 case DP_CONTENT_TYPE_GAME: 2348 return "Game"; 2349 default: 2350 return "Reserved"; 2351 } 2352} 2353 2354void drm_dp_vsc_sdp_log(const char *level, struct device *dev, 2355 const struct drm_dp_vsc_sdp *vsc) 2356{ 2357#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__) 2358 DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC", 2359 vsc->revision, vsc->length); 2360 DP_SDP_LOG(" pixelformat: %s\n", 2361 dp_pixelformat_get_name(vsc->pixelformat)); 2362 DP_SDP_LOG(" colorimetry: %s\n", 2363 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 2364 DP_SDP_LOG(" bpc: %u\n", vsc->bpc); 2365 DP_SDP_LOG(" dynamic range: %s\n", 2366 dp_dynamic_range_get_name(vsc->dynamic_range)); 2367 DP_SDP_LOG(" content type: %s\n", 2368 dp_content_type_get_name(vsc->content_type)); 2369#undef DP_SDP_LOG 2370} 2371EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 2372