1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * NWL MIPI DSI host driver 4 * 5 * Copyright (C) 2017 NXP 6 * Copyright (C) 2019 Purism SPC 7 */ 8#ifndef __NWL_DSI_H__ 9#define __NWL_DSI_H__ 10 11/* DSI HOST registers */ 12#define NWL_DSI_CFG_NUM_LANES 0x0 13#define NWL_DSI_CFG_NONCONTINUOUS_CLK 0x4 14#define NWL_DSI_CFG_T_PRE 0x8 15#define NWL_DSI_CFG_T_POST 0xc 16#define NWL_DSI_CFG_TX_GAP 0x10 17#define NWL_DSI_CFG_AUTOINSERT_EOTP 0x14 18#define NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 19#define NWL_DSI_CFG_HTX_TO_COUNT 0x1c 20#define NWL_DSI_CFG_LRX_H_TO_COUNT 0x20 21#define NWL_DSI_CFG_BTA_H_TO_COUNT 0x24 22#define NWL_DSI_CFG_TWAKEUP 0x28 23#define NWL_DSI_CFG_STATUS_OUT 0x2c 24#define NWL_DSI_RX_ERROR_STATUS 0x30 25 26/* DSI DPI registers */ 27#define NWL_DSI_PIXEL_PAYLOAD_SIZE 0x200 28#define NWL_DSI_PIXEL_FIFO_SEND_LEVEL 0x204 29#define NWL_DSI_INTERFACE_COLOR_CODING 0x208 30#define NWL_DSI_PIXEL_FORMAT 0x20c 31#define NWL_DSI_VSYNC_POLARITY 0x210 32#define NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW 0 33#define NWL_DSI_VSYNC_POLARITY_ACTIVE_HIGH BIT(1) 34 35#define NWL_DSI_HSYNC_POLARITY 0x214 36#define NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW 0 37#define NWL_DSI_HSYNC_POLARITY_ACTIVE_HIGH BIT(1) 38 39#define NWL_DSI_VIDEO_MODE 0x218 40#define NWL_DSI_HFP 0x21c 41#define NWL_DSI_HBP 0x220 42#define NWL_DSI_HSA 0x224 43#define NWL_DSI_ENABLE_MULT_PKTS 0x228 44#define NWL_DSI_VBP 0x22c 45#define NWL_DSI_VFP 0x230 46#define NWL_DSI_BLLP_MODE 0x234 47#define NWL_DSI_USE_NULL_PKT_BLLP 0x238 48#define NWL_DSI_VACTIVE 0x23c 49#define NWL_DSI_VC 0x240 50 51/* DSI APB PKT control */ 52#define NWL_DSI_TX_PAYLOAD 0x280 53#define NWL_DSI_PKT_CONTROL 0x284 54#define NWL_DSI_SEND_PACKET 0x288 55#define NWL_DSI_PKT_STATUS 0x28c 56#define NWL_DSI_PKT_FIFO_WR_LEVEL 0x290 57#define NWL_DSI_PKT_FIFO_RD_LEVEL 0x294 58#define NWL_DSI_RX_PAYLOAD 0x298 59#define NWL_DSI_RX_PKT_HEADER 0x29c 60 61/* DSI IRQ handling */ 62#define NWL_DSI_IRQ_STATUS 0x2a0 63#define NWL_DSI_SM_NOT_IDLE BIT(0) 64#define NWL_DSI_TX_PKT_DONE BIT(1) 65#define NWL_DSI_DPHY_DIRECTION BIT(2) 66#define NWL_DSI_TX_FIFO_OVFLW BIT(3) 67#define NWL_DSI_TX_FIFO_UDFLW BIT(4) 68#define NWL_DSI_RX_FIFO_OVFLW BIT(5) 69#define NWL_DSI_RX_FIFO_UDFLW BIT(6) 70#define NWL_DSI_RX_PKT_HDR_RCVD BIT(7) 71#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD BIT(8) 72#define NWL_DSI_BTA_TIMEOUT BIT(29) 73#define NWL_DSI_LP_RX_TIMEOUT BIT(30) 74#define NWL_DSI_HS_TX_TIMEOUT BIT(31) 75 76#define NWL_DSI_IRQ_STATUS2 0x2a4 77#define NWL_DSI_SINGLE_BIT_ECC_ERR BIT(0) 78#define NWL_DSI_MULTI_BIT_ECC_ERR BIT(1) 79#define NWL_DSI_CRC_ERR BIT(2) 80 81#define NWL_DSI_IRQ_MASK 0x2a8 82#define NWL_DSI_SM_NOT_IDLE_MASK BIT(0) 83#define NWL_DSI_TX_PKT_DONE_MASK BIT(1) 84#define NWL_DSI_DPHY_DIRECTION_MASK BIT(2) 85#define NWL_DSI_TX_FIFO_OVFLW_MASK BIT(3) 86#define NWL_DSI_TX_FIFO_UDFLW_MASK BIT(4) 87#define NWL_DSI_RX_FIFO_OVFLW_MASK BIT(5) 88#define NWL_DSI_RX_FIFO_UDFLW_MASK BIT(6) 89#define NWL_DSI_RX_PKT_HDR_RCVD_MASK BIT(7) 90#define NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD_MASK BIT(8) 91#define NWL_DSI_BTA_TIMEOUT_MASK BIT(29) 92#define NWL_DSI_LP_RX_TIMEOUT_MASK BIT(30) 93#define NWL_DSI_HS_TX_TIMEOUT_MASK BIT(31) 94 95#define NWL_DSI_IRQ_MASK2 0x2ac 96#define NWL_DSI_SINGLE_BIT_ECC_ERR_MASK BIT(0) 97#define NWL_DSI_MULTI_BIT_ECC_ERR_MASK BIT(1) 98#define NWL_DSI_CRC_ERR_MASK BIT(2) 99 100/* 101 * PKT_CONTROL format: 102 * [15: 0] - word count 103 * [17:16] - virtual channel 104 * [23:18] - data type 105 * [24] - LP or HS select (0 - LP, 1 - HS) 106 * [25] - perform BTA after packet is sent 107 * [26] - perform BTA only, no packet tx 108 */ 109#define NWL_DSI_WC(x) FIELD_PREP(GENMASK(15, 0), (x)) 110#define NWL_DSI_TX_VC(x) FIELD_PREP(GENMASK(17, 16), (x)) 111#define NWL_DSI_TX_DT(x) FIELD_PREP(GENMASK(23, 18), (x)) 112#define NWL_DSI_HS_SEL(x) FIELD_PREP(GENMASK(24, 24), (x)) 113#define NWL_DSI_BTA_TX(x) FIELD_PREP(GENMASK(25, 25), (x)) 114#define NWL_DSI_BTA_NO_TX(x) FIELD_PREP(GENMASK(26, 26), (x)) 115 116/* 117 * RX_PKT_HEADER format: 118 * [15: 0] - word count 119 * [21:16] - data type 120 * [23:22] - virtual channel 121 */ 122#define NWL_DSI_RX_DT(x) FIELD_GET(GENMASK(21, 16), (x)) 123#define NWL_DSI_RX_VC(x) FIELD_GET(GENMASK(23, 22), (x)) 124 125/* DSI Video mode */ 126#define NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES 0 127#define NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS BIT(0) 128#define NWL_DSI_VM_BURST_MODE BIT(1) 129 130/* * DPI color coding */ 131#define NWL_DSI_DPI_16_BIT_565_PACKED 0 132#define NWL_DSI_DPI_16_BIT_565_ALIGNED 1 133#define NWL_DSI_DPI_16_BIT_565_SHIFTED 2 134#define NWL_DSI_DPI_18_BIT_PACKED 3 135#define NWL_DSI_DPI_18_BIT_ALIGNED 4 136#define NWL_DSI_DPI_24_BIT 5 137 138/* * DPI Pixel format */ 139#define NWL_DSI_PIXEL_FORMAT_16 0 140#define NWL_DSI_PIXEL_FORMAT_18 BIT(0) 141#define NWL_DSI_PIXEL_FORMAT_18L BIT(1) 142#define NWL_DSI_PIXEL_FORMAT_24 (BIT(0) | BIT(1)) 143 144#endif /* __NWL_DSI_H__ */ 145