18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ciconfig DRM_CDNS_MHDP8546 38c2ecf20Sopenharmony_ci tristate "Cadence DPI/DP bridge" 48c2ecf20Sopenharmony_ci select DRM_KMS_HELPER 58c2ecf20Sopenharmony_ci select DRM_PANEL_BRIDGE 68c2ecf20Sopenharmony_ci depends on OF 78c2ecf20Sopenharmony_ci help 88c2ecf20Sopenharmony_ci Support Cadence DPI to DP bridge. This is an internal 98c2ecf20Sopenharmony_ci bridge and is meant to be directly embedded in a SoC. 108c2ecf20Sopenharmony_ci It takes a DPI stream as input and outputs it encoded 118c2ecf20Sopenharmony_ci in DP format. 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ciif DRM_CDNS_MHDP8546 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ciconfig DRM_CDNS_MHDP8546_J721E 168c2ecf20Sopenharmony_ci depends on ARCH_K3 || COMPILE_TEST 178c2ecf20Sopenharmony_ci bool "J721E Cadence DPI/DP wrapper support" 188c2ecf20Sopenharmony_ci default y 198c2ecf20Sopenharmony_ci help 208c2ecf20Sopenharmony_ci Support J721E Cadence DPI/DP wrapper. This is a wrapper 218c2ecf20Sopenharmony_ci which adds support for J721E related platform ops. It 228c2ecf20Sopenharmony_ci initializes the J721E Display Port and sets up the 238c2ecf20Sopenharmony_ci clock and data muxes. 248c2ecf20Sopenharmony_ciendif 25