1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/pci.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_drv.h>
34#include <drm/drm_gem.h>
35#include <drm/drm_gem_vram_helper.h>
36#include <drm/drm_managed.h>
37
38#include "ast_drv.h"
39
40void ast_set_index_reg_mask(struct ast_private *ast,
41			    uint32_t base, uint8_t index,
42			    uint8_t mask, uint8_t val)
43{
44	u8 tmp;
45	ast_io_write8(ast, base, index);
46	tmp = (ast_io_read8(ast, base + 1) & mask) | val;
47	ast_set_index_reg(ast, base, index, tmp);
48}
49
50uint8_t ast_get_index_reg(struct ast_private *ast,
51			  uint32_t base, uint8_t index)
52{
53	uint8_t ret;
54	ast_io_write8(ast, base, index);
55	ret = ast_io_read8(ast, base + 1);
56	return ret;
57}
58
59uint8_t ast_get_index_reg_mask(struct ast_private *ast,
60			       uint32_t base, uint8_t index, uint8_t mask)
61{
62	uint8_t ret;
63	ast_io_write8(ast, base, index);
64	ret = ast_io_read8(ast, base + 1) & mask;
65	return ret;
66}
67
68static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
69{
70	struct device_node *np = dev->pdev->dev.of_node;
71	struct ast_private *ast = to_ast_private(dev);
72	uint32_t data, jregd0, jregd1;
73
74	/* Defaults */
75	ast->config_mode = ast_use_defaults;
76	*scu_rev = 0xffffffff;
77
78	/* Check if we have device-tree properties */
79	if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
80					scu_rev)) {
81		/* We do, disable P2A access */
82		ast->config_mode = ast_use_dt;
83		drm_info(dev, "Using device-tree for configuration\n");
84		return;
85	}
86
87	/* Not all families have a P2A bridge */
88	if (dev->pdev->device != PCI_CHIP_AST2000)
89		return;
90
91	/*
92	 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
93	 * is disabled. We force using P2A if VGA only mode bit
94	 * is set D[7]
95	 */
96	jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
97	jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
98	if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
99		/* Double check it's actually working */
100		data = ast_read32(ast, 0xf004);
101		if ((data != 0xFFFFFFFF) && (data != 0x00)) {
102			/* P2A works, grab silicon revision */
103			ast->config_mode = ast_use_p2a;
104
105			drm_info(dev, "Using P2A bridge for configuration\n");
106
107			/* Read SCU7c (silicon revision register) */
108			ast_write32(ast, 0xf004, 0x1e6e0000);
109			ast_write32(ast, 0xf000, 0x1);
110			*scu_rev = ast_read32(ast, 0x1207c);
111			return;
112		}
113	}
114
115	/* We have a P2A bridge but it's disabled */
116	drm_info(dev, "P2A bridge disabled, using default configuration\n");
117}
118
119static int ast_detect_chip(struct drm_device *dev, bool *need_post)
120{
121	struct ast_private *ast = to_ast_private(dev);
122	uint32_t jreg, scu_rev;
123
124	/*
125	 * If VGA isn't enabled, we need to enable now or subsequent
126	 * access to the scratch registers will fail. We also inform
127	 * our caller that it needs to POST the chip
128	 * (Assumption: VGA not enabled -> need to POST)
129	 */
130	if (!ast_is_vga_enabled(dev)) {
131		ast_enable_vga(dev);
132		drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
133		*need_post = true;
134	} else
135		*need_post = false;
136
137
138	/* Enable extended register access */
139	ast_open_key(ast);
140	ast_enable_mmio(dev);
141
142	/* Find out whether P2A works or whether to use device-tree */
143	ast_detect_config_mode(dev, &scu_rev);
144
145	/* Identify chipset */
146	if (dev->pdev->revision >= 0x40) {
147		ast->chip = AST2500;
148		drm_info(dev, "AST 2500 detected\n");
149	} else if (dev->pdev->revision >= 0x30) {
150		ast->chip = AST2400;
151		drm_info(dev, "AST 2400 detected\n");
152	} else if (dev->pdev->revision >= 0x20) {
153		ast->chip = AST2300;
154		drm_info(dev, "AST 2300 detected\n");
155	} else if (dev->pdev->revision >= 0x10) {
156		switch (scu_rev & 0x0300) {
157		case 0x0200:
158			ast->chip = AST1100;
159			drm_info(dev, "AST 1100 detected\n");
160			break;
161		case 0x0100:
162			ast->chip = AST2200;
163			drm_info(dev, "AST 2200 detected\n");
164			break;
165		case 0x0000:
166			ast->chip = AST2150;
167			drm_info(dev, "AST 2150 detected\n");
168			break;
169		default:
170			ast->chip = AST2100;
171			drm_info(dev, "AST 2100 detected\n");
172			break;
173		}
174		ast->vga2_clone = false;
175	} else {
176		ast->chip = AST2000;
177		drm_info(dev, "AST 2000 detected\n");
178	}
179
180	/* Check if we support wide screen */
181	switch (ast->chip) {
182	case AST2000:
183		ast->support_wide_screen = false;
184		break;
185	default:
186		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
187		if (!(jreg & 0x80))
188			ast->support_wide_screen = true;
189		else if (jreg & 0x01)
190			ast->support_wide_screen = true;
191		else {
192			ast->support_wide_screen = false;
193			if (ast->chip == AST2300 &&
194			    (scu_rev & 0x300) == 0x0) /* ast1300 */
195				ast->support_wide_screen = true;
196			if (ast->chip == AST2400 &&
197			    (scu_rev & 0x300) == 0x100) /* ast1400 */
198				ast->support_wide_screen = true;
199			if (ast->chip == AST2500 &&
200			    scu_rev == 0x100)           /* ast2510 */
201				ast->support_wide_screen = true;
202		}
203		break;
204	}
205
206	/* Check 3rd Tx option (digital output afaik) */
207	ast->tx_chip_type = AST_TX_NONE;
208
209	/*
210	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
211	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
212	 *
213	 * Don't make that assumption if we the chip wasn't enabled and
214	 * is at power-on reset, otherwise we'll incorrectly "detect" a
215	 * SIL164 when there is none.
216	 */
217	if (!*need_post) {
218		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
219		if (jreg & 0x80)
220			ast->tx_chip_type = AST_TX_SIL164;
221	}
222
223	if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
224		/*
225		 * On AST2300 and 2400, look the configuration set by the SoC in
226		 * the SOC scratch register #1 bits 11:8 (interestingly marked
227		 * as "reserved" in the spec)
228		 */
229		jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
230		switch (jreg) {
231		case 0x04:
232			ast->tx_chip_type = AST_TX_SIL164;
233			break;
234		case 0x08:
235			ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
236			if (ast->dp501_fw_addr) {
237				/* backup firmware */
238				if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
239					drmm_kfree(dev, ast->dp501_fw_addr);
240					ast->dp501_fw_addr = NULL;
241				}
242			}
243			fallthrough;
244		case 0x0c:
245			ast->tx_chip_type = AST_TX_DP501;
246		}
247	}
248
249	/* Print stuff for diagnostic purposes */
250	switch(ast->tx_chip_type) {
251	case AST_TX_SIL164:
252		drm_info(dev, "Using Sil164 TMDS transmitter\n");
253		break;
254	case AST_TX_DP501:
255		drm_info(dev, "Using DP501 DisplayPort transmitter\n");
256		break;
257	default:
258		drm_info(dev, "Analog VGA only\n");
259	}
260	return 0;
261}
262
263static int ast_get_dram_info(struct drm_device *dev)
264{
265	struct device_node *np = dev->pdev->dev.of_node;
266	struct ast_private *ast = to_ast_private(dev);
267	uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
268	uint32_t denum, num, div, ref_pll, dsel;
269
270	switch (ast->config_mode) {
271	case ast_use_dt:
272		/*
273		 * If some properties are missing, use reasonable
274		 * defaults for AST2400
275		 */
276		if (of_property_read_u32(np, "aspeed,mcr-configuration",
277					 &mcr_cfg))
278			mcr_cfg = 0x00000577;
279		if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
280					 &mcr_scu_mpll))
281			mcr_scu_mpll = 0x000050C0;
282		if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
283					 &mcr_scu_strap))
284			mcr_scu_strap = 0;
285		break;
286	case ast_use_p2a:
287		ast_write32(ast, 0xf004, 0x1e6e0000);
288		ast_write32(ast, 0xf000, 0x1);
289		mcr_cfg = ast_read32(ast, 0x10004);
290		mcr_scu_mpll = ast_read32(ast, 0x10120);
291		mcr_scu_strap = ast_read32(ast, 0x10170);
292		break;
293	case ast_use_defaults:
294	default:
295		ast->dram_bus_width = 16;
296		ast->dram_type = AST_DRAM_1Gx16;
297		if (ast->chip == AST2500)
298			ast->mclk = 800;
299		else
300			ast->mclk = 396;
301		return 0;
302	}
303
304	if (mcr_cfg & 0x40)
305		ast->dram_bus_width = 16;
306	else
307		ast->dram_bus_width = 32;
308
309	if (ast->chip == AST2500) {
310		switch (mcr_cfg & 0x03) {
311		case 0:
312			ast->dram_type = AST_DRAM_1Gx16;
313			break;
314		default:
315		case 1:
316			ast->dram_type = AST_DRAM_2Gx16;
317			break;
318		case 2:
319			ast->dram_type = AST_DRAM_4Gx16;
320			break;
321		case 3:
322			ast->dram_type = AST_DRAM_8Gx16;
323			break;
324		}
325	} else if (ast->chip == AST2300 || ast->chip == AST2400) {
326		switch (mcr_cfg & 0x03) {
327		case 0:
328			ast->dram_type = AST_DRAM_512Mx16;
329			break;
330		default:
331		case 1:
332			ast->dram_type = AST_DRAM_1Gx16;
333			break;
334		case 2:
335			ast->dram_type = AST_DRAM_2Gx16;
336			break;
337		case 3:
338			ast->dram_type = AST_DRAM_4Gx16;
339			break;
340		}
341	} else {
342		switch (mcr_cfg & 0x0c) {
343		case 0:
344		case 4:
345			ast->dram_type = AST_DRAM_512Mx16;
346			break;
347		case 8:
348			if (mcr_cfg & 0x40)
349				ast->dram_type = AST_DRAM_1Gx16;
350			else
351				ast->dram_type = AST_DRAM_512Mx32;
352			break;
353		case 0xc:
354			ast->dram_type = AST_DRAM_1Gx32;
355			break;
356		}
357	}
358
359	if (mcr_scu_strap & 0x2000)
360		ref_pll = 14318;
361	else
362		ref_pll = 12000;
363
364	denum = mcr_scu_mpll & 0x1f;
365	num = (mcr_scu_mpll & 0x3fe0) >> 5;
366	dsel = (mcr_scu_mpll & 0xc000) >> 14;
367	switch (dsel) {
368	case 3:
369		div = 0x4;
370		break;
371	case 2:
372	case 1:
373		div = 0x2;
374		break;
375	default:
376		div = 0x1;
377		break;
378	}
379	ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
380	return 0;
381}
382
383/*
384 * Run this function as part of the HW device cleanup; not
385 * when the DRM device gets released.
386 */
387static void ast_device_release(void *data)
388{
389	struct ast_private *ast = data;
390
391	/* enable standard VGA decode */
392	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
393}
394
395struct ast_private *ast_device_create(struct drm_driver *drv,
396				      struct pci_dev *pdev,
397				      unsigned long flags)
398{
399	struct drm_device *dev;
400	struct ast_private *ast;
401	bool need_post;
402	int ret = 0;
403
404	ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
405	if (IS_ERR(ast))
406		return ast;
407	dev = &ast->base;
408
409	dev->pdev = pdev;
410	pci_set_drvdata(pdev, dev);
411
412	ast->regs = pcim_iomap(pdev, 1, 0);
413	if (!ast->regs)
414		return ERR_PTR(-EIO);
415
416	/*
417	 * If we don't have IO space at all, use MMIO now and
418	 * assume the chip has MMIO enabled by default (rev 0x20
419	 * and higher).
420	 */
421	if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
422		drm_info(dev, "platform has no IO space, trying MMIO\n");
423		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
424	}
425
426	/* "map" IO regs if the above hasn't done so already */
427	if (!ast->ioregs) {
428		ast->ioregs = pcim_iomap(pdev, 2, 0);
429		if (!ast->ioregs)
430			return ERR_PTR(-EIO);
431	}
432
433	ast_detect_chip(dev, &need_post);
434
435	ret = ast_get_dram_info(dev);
436	if (ret)
437		return ERR_PTR(ret);
438
439	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
440		 ast->mclk, ast->dram_type, ast->dram_bus_width);
441
442	if (need_post)
443		ast_post_gpu(dev);
444
445	ret = ast_mm_init(ast);
446	if (ret)
447		return ERR_PTR(ret);
448
449	/* map reserved buffer */
450	ast->dp501_fw_buf = NULL;
451	if (dev->vram_mm->vram_size < pci_resource_len(dev->pdev, 0)) {
452		ast->dp501_fw_buf = pci_iomap_range(dev->pdev, 0, dev->vram_mm->vram_size, 0);
453		if (!ast->dp501_fw_buf)
454			drm_info(dev, "failed to map reserved buffer!\n");
455	}
456
457	ret = ast_mode_config_init(ast);
458	if (ret)
459		return ERR_PTR(ret);
460
461	ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
462	if (ret)
463		return ERR_PTR(ret);
464
465	return ast;
466}
467