18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * ARM HDLCD Controller register definition 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci#ifndef __HDLCD_DRV_H__ 78c2ecf20Sopenharmony_ci#define __HDLCD_DRV_H__ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_cistruct hdlcd_drm_private { 108c2ecf20Sopenharmony_ci void __iomem *mmio; 118c2ecf20Sopenharmony_ci struct clk *clk; 128c2ecf20Sopenharmony_ci struct drm_crtc crtc; 138c2ecf20Sopenharmony_ci struct drm_plane *plane; 148c2ecf20Sopenharmony_ci#ifdef CONFIG_DEBUG_FS 158c2ecf20Sopenharmony_ci atomic_t buffer_underrun_count; 168c2ecf20Sopenharmony_ci atomic_t bus_error_count; 178c2ecf20Sopenharmony_ci atomic_t vsync_count; 188c2ecf20Sopenharmony_ci atomic_t dma_end_count; 198c2ecf20Sopenharmony_ci#endif 208c2ecf20Sopenharmony_ci}; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define crtc_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, crtc) 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_cistatic inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, 258c2ecf20Sopenharmony_ci unsigned int reg, u32 value) 268c2ecf20Sopenharmony_ci{ 278c2ecf20Sopenharmony_ci writel(value, hdlcd->mmio + reg); 288c2ecf20Sopenharmony_ci} 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_cistatic inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) 318c2ecf20Sopenharmony_ci{ 328c2ecf20Sopenharmony_ci return readl(hdlcd->mmio + reg); 338c2ecf20Sopenharmony_ci} 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ciint hdlcd_setup_crtc(struct drm_device *dev); 368c2ecf20Sopenharmony_civoid hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd); 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci#endif /* __HDLCD_DRV_H__ */ 39