1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/pci.h> 25 26#include "amdgpu.h" 27#include "amdgpu_ih.h" 28#include "vid.h" 29 30#include "oss/oss_3_0_d.h" 31#include "oss/oss_3_0_sh_mask.h" 32 33#include "bif/bif_5_1_d.h" 34#include "bif/bif_5_1_sh_mask.h" 35 36/* 37 * Interrupts 38 * Starting with r6xx, interrupts are handled via a ring buffer. 39 * Ring buffers are areas of GPU accessible memory that the GPU 40 * writes interrupt vectors into and the host reads vectors out of. 41 * There is a rptr (read pointer) that determines where the 42 * host is currently reading, and a wptr (write pointer) 43 * which determines where the GPU has written. When the 44 * pointers are equal, the ring is idle. When the GPU 45 * writes vectors to the ring buffer, it increments the 46 * wptr. When there is an interrupt, the host then starts 47 * fetching commands and processing them until the pointers are 48 * equal again at which point it updates the rptr. 49 */ 50 51static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); 52 53/** 54 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer 55 * 56 * @adev: amdgpu_device pointer 57 * 58 * Enable the interrupt ring buffer (VI). 59 */ 60static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) 61{ 62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 63 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 67 adev->irq.ih.enabled = true; 68} 69 70/** 71 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer 72 * 73 * @adev: amdgpu_device pointer 74 * 75 * Disable the interrupt ring buffer (VI). 76 */ 77static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) 78{ 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 80 81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 84 /* set rptr, wptr to 0 */ 85 WREG32(mmIH_RB_RPTR, 0); 86 WREG32(mmIH_RB_WPTR, 0); 87 adev->irq.ih.enabled = false; 88 adev->irq.ih.rptr = 0; 89} 90 91/** 92 * tonga_ih_irq_init - init and enable the interrupt ring 93 * 94 * @adev: amdgpu_device pointer 95 * 96 * Allocate a ring buffer for the interrupt controller, 97 * enable the RLC, disable interrupts, enable the IH 98 * ring buffer and enable it (VI). 99 * Called at device load and reume. 100 * Returns 0 for success, errors for failure. 101 */ 102static int tonga_ih_irq_init(struct amdgpu_device *adev) 103{ 104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; 105 struct amdgpu_ih_ring *ih = &adev->irq.ih; 106 int rb_bufsz; 107 108 /* disable irqs */ 109 tonga_ih_disable_interrupts(adev); 110 111 /* setup interrupt control */ 112 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 113 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 114 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 115 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 116 */ 117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 118 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 120 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 121 122 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); 124 125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 128 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 131 132 if (adev->irq.msi_enabled) 133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 134 135 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 136 137 /* set the writeback address whether it's enabled or not */ 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 140 141 /* set rptr, wptr to 0 */ 142 WREG32(mmIH_RB_RPTR, 0); 143 WREG32(mmIH_RB_WPTR, 0); 144 145 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); 146 if (adev->irq.ih.use_doorbell) { 147 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 148 OFFSET, adev->irq.ih.doorbell_index); 149 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 150 ENABLE, 1); 151 } else { 152 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 153 ENABLE, 0); 154 } 155 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 156 157 pci_set_master(adev->pdev); 158 159 /* enable interrupts */ 160 tonga_ih_enable_interrupts(adev); 161 162 return 0; 163} 164 165/** 166 * tonga_ih_irq_disable - disable interrupts 167 * 168 * @adev: amdgpu_device pointer 169 * 170 * Disable interrupts on the hw (VI). 171 */ 172static void tonga_ih_irq_disable(struct amdgpu_device *adev) 173{ 174 tonga_ih_disable_interrupts(adev); 175 176 /* Wait and acknowledge irq */ 177 mdelay(1); 178} 179 180/** 181 * tonga_ih_get_wptr - get the IH ring buffer wptr 182 * 183 * @adev: amdgpu_device pointer 184 * 185 * Get the IH ring buffer wptr from either the register 186 * or the writeback memory buffer (VI). Also check for 187 * ring buffer overflow and deal with it. 188 * Used by cz_irq_process(VI). 189 * Returns the value of the wptr. 190 */ 191static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, 192 struct amdgpu_ih_ring *ih) 193{ 194 u32 wptr, tmp; 195 196 wptr = le32_to_cpu(*ih->wptr_cpu); 197 198 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 199 goto out; 200 201 /* Double check that the overflow wasn't already cleared. */ 202 wptr = RREG32(mmIH_RB_WPTR); 203 204 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 205 goto out; 206 207 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 208 209 /* When a ring buffer overflow happen start parsing interrupt 210 * from the last not overwritten vector (wptr + 16). Hopefully 211 * this should allow us to catchup. 212 */ 213 214 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 215 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 216 ih->rptr = (wptr + 16) & ih->ptr_mask; 217 tmp = RREG32(mmIH_RB_CNTL); 218 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 219 WREG32(mmIH_RB_CNTL, tmp); 220 221out: 222 return (wptr & ih->ptr_mask); 223} 224 225/** 226 * tonga_ih_decode_iv - decode an interrupt vector 227 * 228 * @adev: amdgpu_device pointer 229 * 230 * Decodes the interrupt vector at the current rptr 231 * position and also advance the position. 232 */ 233static void tonga_ih_decode_iv(struct amdgpu_device *adev, 234 struct amdgpu_ih_ring *ih, 235 struct amdgpu_iv_entry *entry) 236{ 237 /* wptr/rptr are in bytes! */ 238 u32 ring_index = ih->rptr >> 2; 239 uint32_t dw[4]; 240 241 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 242 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 243 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 244 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 245 246 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 247 entry->src_id = dw[0] & 0xff; 248 entry->src_data[0] = dw[1] & 0xfffffff; 249 entry->ring_id = dw[2] & 0xff; 250 entry->vmid = (dw[2] >> 8) & 0xff; 251 entry->pasid = (dw[2] >> 16) & 0xffff; 252 253 /* wptr/rptr are in bytes! */ 254 ih->rptr += 16; 255} 256 257/** 258 * tonga_ih_set_rptr - set the IH ring buffer rptr 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Set the IH ring buffer rptr. 263 */ 264static void tonga_ih_set_rptr(struct amdgpu_device *adev, 265 struct amdgpu_ih_ring *ih) 266{ 267 if (ih->use_doorbell) { 268 /* XXX check if swapping is necessary on BE */ 269 *ih->rptr_cpu = ih->rptr; 270 WDOORBELL32(ih->doorbell_index, ih->rptr); 271 } else { 272 WREG32(mmIH_RB_RPTR, ih->rptr); 273 } 274} 275 276static int tonga_ih_early_init(void *handle) 277{ 278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 279 int ret; 280 281 ret = amdgpu_irq_add_domain(adev); 282 if (ret) 283 return ret; 284 285 tonga_ih_set_interrupt_funcs(adev); 286 287 return 0; 288} 289 290static int tonga_ih_sw_init(void *handle) 291{ 292 int r; 293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 294 295 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true); 296 if (r) 297 return r; 298 299 adev->irq.ih.use_doorbell = true; 300 adev->irq.ih.doorbell_index = adev->doorbell_index.ih; 301 302 r = amdgpu_irq_init(adev); 303 304 return r; 305} 306 307static int tonga_ih_sw_fini(void *handle) 308{ 309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 310 311 amdgpu_irq_fini(adev); 312 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 313 amdgpu_irq_remove_domain(adev); 314 315 return 0; 316} 317 318static int tonga_ih_hw_init(void *handle) 319{ 320 int r; 321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 322 323 r = tonga_ih_irq_init(adev); 324 if (r) 325 return r; 326 327 return 0; 328} 329 330static int tonga_ih_hw_fini(void *handle) 331{ 332 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 333 334 tonga_ih_irq_disable(adev); 335 336 return 0; 337} 338 339static int tonga_ih_suspend(void *handle) 340{ 341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 342 343 return tonga_ih_hw_fini(adev); 344} 345 346static int tonga_ih_resume(void *handle) 347{ 348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 349 350 return tonga_ih_hw_init(adev); 351} 352 353static bool tonga_ih_is_idle(void *handle) 354{ 355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 356 u32 tmp = RREG32(mmSRBM_STATUS); 357 358 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 359 return false; 360 361 return true; 362} 363 364static int tonga_ih_wait_for_idle(void *handle) 365{ 366 unsigned i; 367 u32 tmp; 368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 369 370 for (i = 0; i < adev->usec_timeout; i++) { 371 /* read MC_STATUS */ 372 tmp = RREG32(mmSRBM_STATUS); 373 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 374 return 0; 375 udelay(1); 376 } 377 return -ETIMEDOUT; 378} 379 380static bool tonga_ih_check_soft_reset(void *handle) 381{ 382 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 383 u32 srbm_soft_reset = 0; 384 u32 tmp = RREG32(mmSRBM_STATUS); 385 386 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 387 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 388 SOFT_RESET_IH, 1); 389 390 if (srbm_soft_reset) { 391 adev->irq.srbm_soft_reset = srbm_soft_reset; 392 return true; 393 } else { 394 adev->irq.srbm_soft_reset = 0; 395 return false; 396 } 397} 398 399static int tonga_ih_pre_soft_reset(void *handle) 400{ 401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 402 403 if (!adev->irq.srbm_soft_reset) 404 return 0; 405 406 return tonga_ih_hw_fini(adev); 407} 408 409static int tonga_ih_post_soft_reset(void *handle) 410{ 411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 412 413 if (!adev->irq.srbm_soft_reset) 414 return 0; 415 416 return tonga_ih_hw_init(adev); 417} 418 419static int tonga_ih_soft_reset(void *handle) 420{ 421 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 422 u32 srbm_soft_reset; 423 424 if (!adev->irq.srbm_soft_reset) 425 return 0; 426 srbm_soft_reset = adev->irq.srbm_soft_reset; 427 428 if (srbm_soft_reset) { 429 u32 tmp; 430 431 tmp = RREG32(mmSRBM_SOFT_RESET); 432 tmp |= srbm_soft_reset; 433 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 434 WREG32(mmSRBM_SOFT_RESET, tmp); 435 tmp = RREG32(mmSRBM_SOFT_RESET); 436 437 udelay(50); 438 439 tmp &= ~srbm_soft_reset; 440 WREG32(mmSRBM_SOFT_RESET, tmp); 441 tmp = RREG32(mmSRBM_SOFT_RESET); 442 443 /* Wait a little for things to settle down */ 444 udelay(50); 445 } 446 447 return 0; 448} 449 450static int tonga_ih_set_clockgating_state(void *handle, 451 enum amd_clockgating_state state) 452{ 453 return 0; 454} 455 456static int tonga_ih_set_powergating_state(void *handle, 457 enum amd_powergating_state state) 458{ 459 return 0; 460} 461 462static const struct amd_ip_funcs tonga_ih_ip_funcs = { 463 .name = "tonga_ih", 464 .early_init = tonga_ih_early_init, 465 .late_init = NULL, 466 .sw_init = tonga_ih_sw_init, 467 .sw_fini = tonga_ih_sw_fini, 468 .hw_init = tonga_ih_hw_init, 469 .hw_fini = tonga_ih_hw_fini, 470 .suspend = tonga_ih_suspend, 471 .resume = tonga_ih_resume, 472 .is_idle = tonga_ih_is_idle, 473 .wait_for_idle = tonga_ih_wait_for_idle, 474 .check_soft_reset = tonga_ih_check_soft_reset, 475 .pre_soft_reset = tonga_ih_pre_soft_reset, 476 .soft_reset = tonga_ih_soft_reset, 477 .post_soft_reset = tonga_ih_post_soft_reset, 478 .set_clockgating_state = tonga_ih_set_clockgating_state, 479 .set_powergating_state = tonga_ih_set_powergating_state, 480}; 481 482static const struct amdgpu_ih_funcs tonga_ih_funcs = { 483 .get_wptr = tonga_ih_get_wptr, 484 .decode_iv = tonga_ih_decode_iv, 485 .set_rptr = tonga_ih_set_rptr 486}; 487 488static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) 489{ 490 adev->irq.ih_funcs = &tonga_ih_funcs; 491} 492 493const struct amdgpu_ip_block_version tonga_ih_ip_block = 494{ 495 .type = AMD_IP_BLOCK_TYPE_IH, 496 .major = 3, 497 .minor = 0, 498 .rev = 0, 499 .funcs = &tonga_ih_ip_funcs, 500}; 501