1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/pci.h> 25 26#include "amdgpu.h" 27#include "amdgpu_ih.h" 28 29#include "oss/osssys_5_0_0_offset.h" 30#include "oss/osssys_5_0_0_sh_mask.h" 31 32#include "soc15_common.h" 33#include "navi10_ih.h" 34 35#define MAX_REARM_RETRY 10 36 37#define mmIH_CHICKEN_Sienna_Cichlid 0x018d 38#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX 0 39 40static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev); 41 42/** 43 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 44 * 45 * @adev: amdgpu_device pointer 46 * @threshold: threshold to trigger the wptr reporting 47 * @timeout: timeout to trigger the wptr reporting 48 * @enabled: Enable/disable timeout flush mechanism 49 * 50 * threshold input range: 0 ~ 15, default 0, 51 * real_threshold = 2^threshold 52 * timeout input range: 0 ~ 20, default 8, 53 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 54 * 55 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 56 */ 57static void 58force_update_wptr_for_self_int(struct amdgpu_device *adev, 59 u32 threshold, u32 timeout, bool enabled) 60{ 61 u32 ih_cntl, ih_rb_cntl; 62 63 if (adev->asic_type < CHIP_SIENNA_CICHLID) 64 return; 65 66 ih_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_CNTL2); 67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 68 69 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 70 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 71 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 72 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 73 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 74 RB_USED_INT_THRESHOLD, threshold); 75 76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 78 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 79 RB_USED_INT_THRESHOLD, threshold); 80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); 82} 83 84/** 85 * navi10_ih_enable_interrupts - Enable the interrupt ring buffer 86 * 87 * @adev: amdgpu_device pointer 88 * 89 * Enable the interrupt ring buffer (NAVI10). 90 */ 91static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 92{ 93 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 94 95 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 96 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 97 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 98 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 99 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 100 return; 101 } 102 } else { 103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 104 } 105 106 adev->irq.ih.enabled = true; 107 108 if (adev->irq.ih1.ring_size) { 109 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 110 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 111 RB_ENABLE, 1); 112 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 113 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 114 ih_rb_cntl)) { 115 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 116 return; 117 } 118 } else { 119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 120 } 121 adev->irq.ih1.enabled = true; 122 } 123 124 if (adev->irq.ih2.ring_size) { 125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 126 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 127 RB_ENABLE, 1); 128 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 129 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 130 ih_rb_cntl)) { 131 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 132 return; 133 } 134 } else { 135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 136 } 137 adev->irq.ih2.enabled = true; 138 } 139} 140 141/** 142 * navi10_ih_disable_interrupts - Disable the interrupt ring buffer 143 * 144 * @adev: amdgpu_device pointer 145 * 146 * Disable the interrupt ring buffer (NAVI10). 147 */ 148static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 149{ 150 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 151 152 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 153 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 154 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 155 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 156 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 157 return; 158 } 159 } else { 160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 161 } 162 163 /* set rptr, wptr to 0 */ 164 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 166 adev->irq.ih.enabled = false; 167 adev->irq.ih.rptr = 0; 168 169 if (adev->irq.ih1.ring_size) { 170 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 172 RB_ENABLE, 0); 173 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 174 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 175 ih_rb_cntl)) { 176 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 177 return; 178 } 179 } else { 180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 181 } 182 /* set rptr, wptr to 0 */ 183 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 184 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 185 adev->irq.ih1.enabled = false; 186 adev->irq.ih1.rptr = 0; 187 } 188 189 if (adev->irq.ih2.ring_size) { 190 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2, 192 RB_ENABLE, 0); 193 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 194 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 195 ih_rb_cntl)) { 196 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 197 return; 198 } 199 } else { 200 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 201 } 202 /* set rptr, wptr to 0 */ 203 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 204 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 205 adev->irq.ih2.enabled = false; 206 adev->irq.ih2.rptr = 0; 207 } 208 209} 210 211static uint32_t navi10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 212{ 213 int rb_bufsz = order_base_2(ih->ring_size / 4); 214 215 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 216 MC_SPACE, ih->use_bus_addr ? 1 : 4); 217 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 218 WPTR_OVERFLOW_CLEAR, 1); 219 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 220 WPTR_OVERFLOW_ENABLE, 1); 221 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 222 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 223 * value is written to memory 224 */ 225 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 226 WPTR_WRITEBACK_ENABLE, 1); 227 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 228 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 229 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 230 231 return ih_rb_cntl; 232} 233 234static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 235{ 236 u32 ih_doorbell_rtpr = 0; 237 238 if (ih->use_doorbell) { 239 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 240 IH_DOORBELL_RPTR, OFFSET, 241 ih->doorbell_index); 242 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 243 IH_DOORBELL_RPTR, 244 ENABLE, 1); 245 } else { 246 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 247 IH_DOORBELL_RPTR, 248 ENABLE, 0); 249 } 250 return ih_doorbell_rtpr; 251} 252 253static void navi10_ih_reroute_ih(struct amdgpu_device *adev) 254{ 255 uint32_t tmp; 256 257 /* Reroute to IH ring 1 for VMC */ 258 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); 259 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 260 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 261 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 262 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 263 264 /* Reroute IH ring 1 for UMC */ 265 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); 266 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA); 267 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 268 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); 269} 270 271/** 272 * navi10_ih_irq_init - init and enable the interrupt ring 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Allocate a ring buffer for the interrupt controller, 277 * enable the RLC, disable interrupts, enable the IH 278 * ring buffer and enable it (NAVI). 279 * Called at device load and reume. 280 * Returns 0 for success, errors for failure. 281 */ 282static int navi10_ih_irq_init(struct amdgpu_device *adev) 283{ 284 struct amdgpu_ih_ring *ih = &adev->irq.ih; 285 u32 ih_rb_cntl, ih_chicken; 286 u32 tmp; 287 288 /* disable irqs */ 289 navi10_ih_disable_interrupts(adev); 290 291 adev->nbio.funcs->ih_control(adev); 292 293 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 294 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); 295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); 296 297 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 298 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 299 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 300 !!adev->irq.msi_enabled); 301 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 302 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) { 303 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 304 return -ETIMEDOUT; 305 } 306 } else { 307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 308 } 309 if (adev->irq.ih1.ring_size) 310 navi10_ih_reroute_ih(adev); 311 312 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) { 313 if (ih->use_bus_addr) { 314 switch (adev->asic_type) { 315 case CHIP_SIENNA_CICHLID: 316 case CHIP_NAVY_FLOUNDER: 317 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); 318 ih_chicken = REG_SET_FIELD(ih_chicken, 319 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 320 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); 321 break; 322 default: 323 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); 324 ih_chicken = REG_SET_FIELD(ih_chicken, 325 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 326 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); 327 break; 328 } 329 } 330 } 331 332 /* set the writeback address whether it's enabled or not */ 333 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, 334 lower_32_bits(ih->wptr_addr)); 335 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, 336 upper_32_bits(ih->wptr_addr) & 0xFFFF); 337 338 /* set rptr, wptr to 0 */ 339 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 340 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); 341 342 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, 343 navi10_ih_doorbell_rptr(ih)); 344 345 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell, 346 ih->doorbell_index); 347 348 ih = &adev->irq.ih1; 349 if (ih->ring_size) { 350 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); 351 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, 352 (ih->gpu_addr >> 40) & 0xff); 353 354 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); 355 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 356 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 357 WPTR_OVERFLOW_ENABLE, 0); 358 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 359 RB_FULL_DRAIN_ENABLE, 1); 360 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 361 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, 362 ih_rb_cntl)) { 363 DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n"); 364 return -ETIMEDOUT; 365 } 366 } else { 367 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); 368 } 369 /* set rptr, wptr to 0 */ 370 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); 371 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); 372 373 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, 374 navi10_ih_doorbell_rptr(ih)); 375 } 376 377 ih = &adev->irq.ih2; 378 if (ih->ring_size) { 379 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); 380 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, 381 (ih->gpu_addr >> 40) & 0xff); 382 383 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); 384 ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl); 385 386 if (amdgpu_sriov_vf(adev) && adev->asic_type < CHIP_NAVI10) { 387 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, 388 ih_rb_cntl)) { 389 DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n"); 390 return -ETIMEDOUT; 391 } 392 } else { 393 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); 394 } 395 /* set rptr, wptr to 0 */ 396 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); 397 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); 398 399 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, 400 navi10_ih_doorbell_rptr(ih)); 401 } 402 403 404 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL); 405 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 406 CLIENT18_IS_STORM_CLIENT, 1); 407 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); 408 409 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL); 410 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 411 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); 412 413 pci_set_master(adev->pdev); 414 415 /* enable interrupts */ 416 navi10_ih_enable_interrupts(adev); 417 /* enable wptr force update for self int */ 418 force_update_wptr_for_self_int(adev, 0, 8, true); 419 420 return 0; 421} 422 423/** 424 * navi10_ih_irq_disable - disable interrupts 425 * 426 * @adev: amdgpu_device pointer 427 * 428 * Disable interrupts on the hw (NAVI10). 429 */ 430static void navi10_ih_irq_disable(struct amdgpu_device *adev) 431{ 432 force_update_wptr_for_self_int(adev, 0, 8, false); 433 navi10_ih_disable_interrupts(adev); 434 435 /* Wait and acknowledge irq */ 436 mdelay(1); 437} 438 439/** 440 * navi10_ih_get_wptr - get the IH ring buffer wptr 441 * 442 * @adev: amdgpu_device pointer 443 * 444 * Get the IH ring buffer wptr from either the register 445 * or the writeback memory buffer (NAVI10). Also check for 446 * ring buffer overflow and deal with it. 447 * Returns the value of the wptr. 448 */ 449static u32 navi10_ih_get_wptr(struct amdgpu_device *adev, 450 struct amdgpu_ih_ring *ih) 451{ 452 u32 wptr, reg, tmp; 453 454 wptr = le32_to_cpu(*ih->wptr_cpu); 455 456 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 457 goto out; 458 459 if (ih == &adev->irq.ih) 460 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); 461 else if (ih == &adev->irq.ih1) 462 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); 463 else if (ih == &adev->irq.ih2) 464 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); 465 else 466 BUG(); 467 468 wptr = RREG32_NO_KIQ(reg); 469 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 470 goto out; 471 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 472 473 /* When a ring buffer overflow happen start parsing interrupt 474 * from the last not overwritten vector (wptr + 32). Hopefully 475 * this should allow us to catch up. 476 */ 477 tmp = (wptr + 32) & ih->ptr_mask; 478 dev_warn(adev->dev, "IH ring buffer overflow " 479 "(0x%08X, 0x%08X, 0x%08X)\n", 480 wptr, ih->rptr, tmp); 481 ih->rptr = tmp; 482 483 if (ih == &adev->irq.ih) 484 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); 485 else if (ih == &adev->irq.ih1) 486 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); 487 else if (ih == &adev->irq.ih2) 488 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); 489 else 490 BUG(); 491 492 tmp = RREG32_NO_KIQ(reg); 493 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 494 WREG32_NO_KIQ(reg, tmp); 495out: 496 return (wptr & ih->ptr_mask); 497} 498 499/** 500 * navi10_ih_decode_iv - decode an interrupt vector 501 * 502 * @adev: amdgpu_device pointer 503 * 504 * Decodes the interrupt vector at the current rptr 505 * position and also advance the position. 506 */ 507static void navi10_ih_decode_iv(struct amdgpu_device *adev, 508 struct amdgpu_ih_ring *ih, 509 struct amdgpu_iv_entry *entry) 510{ 511 /* wptr/rptr are in bytes! */ 512 u32 ring_index = ih->rptr >> 2; 513 uint32_t dw[8]; 514 515 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 516 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 517 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 518 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 519 dw[4] = le32_to_cpu(ih->ring[ring_index + 4]); 520 dw[5] = le32_to_cpu(ih->ring[ring_index + 5]); 521 dw[6] = le32_to_cpu(ih->ring[ring_index + 6]); 522 dw[7] = le32_to_cpu(ih->ring[ring_index + 7]); 523 524 entry->client_id = dw[0] & 0xff; 525 entry->src_id = (dw[0] >> 8) & 0xff; 526 entry->ring_id = (dw[0] >> 16) & 0xff; 527 entry->vmid = (dw[0] >> 24) & 0xf; 528 entry->vmid_src = (dw[0] >> 31); 529 entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32); 530 entry->timestamp_src = dw[2] >> 31; 531 entry->pasid = dw[3] & 0xffff; 532 entry->pasid_src = dw[3] >> 31; 533 entry->src_data[0] = dw[4]; 534 entry->src_data[1] = dw[5]; 535 entry->src_data[2] = dw[6]; 536 entry->src_data[3] = dw[7]; 537 538 /* wptr/rptr are in bytes! */ 539 ih->rptr += 32; 540} 541 542/** 543 * navi10_ih_irq_rearm - rearm IRQ if lost 544 * 545 * @adev: amdgpu_device pointer 546 * 547 */ 548static void navi10_ih_irq_rearm(struct amdgpu_device *adev, 549 struct amdgpu_ih_ring *ih) 550{ 551 uint32_t reg_rptr = 0; 552 uint32_t v = 0; 553 uint32_t i = 0; 554 555 if (ih == &adev->irq.ih) 556 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 557 else if (ih == &adev->irq.ih1) 558 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); 559 else if (ih == &adev->irq.ih2) 560 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); 561 else 562 return; 563 564 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 565 for (i = 0; i < MAX_REARM_RETRY; i++) { 566 v = RREG32_NO_KIQ(reg_rptr); 567 if ((v < ih->ring_size) && (v != ih->rptr)) 568 WDOORBELL32(ih->doorbell_index, ih->rptr); 569 else 570 break; 571 } 572} 573 574/** 575 * navi10_ih_set_rptr - set the IH ring buffer rptr 576 * 577 * @adev: amdgpu_device pointer 578 * 579 * Set the IH ring buffer rptr. 580 */ 581static void navi10_ih_set_rptr(struct amdgpu_device *adev, 582 struct amdgpu_ih_ring *ih) 583{ 584 if (ih->use_doorbell) { 585 /* XXX check if swapping is necessary on BE */ 586 *ih->rptr_cpu = ih->rptr; 587 WDOORBELL32(ih->doorbell_index, ih->rptr); 588 589 if (amdgpu_sriov_vf(adev)) 590 navi10_ih_irq_rearm(adev, ih); 591 } else if (ih == &adev->irq.ih) { 592 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); 593 } else if (ih == &adev->irq.ih1) { 594 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); 595 } else if (ih == &adev->irq.ih2) { 596 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); 597 } 598} 599 600/** 601 * navi10_ih_self_irq - dispatch work for ring 1 and 2 602 * 603 * @adev: amdgpu_device pointer 604 * @source: irq source 605 * @entry: IV with WPTR update 606 * 607 * Update the WPTR from the IV and schedule work to handle the entries. 608 */ 609static int navi10_ih_self_irq(struct amdgpu_device *adev, 610 struct amdgpu_irq_src *source, 611 struct amdgpu_iv_entry *entry) 612{ 613 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 614 615 switch (entry->ring_id) { 616 case 1: 617 *adev->irq.ih1.wptr_cpu = wptr; 618 schedule_work(&adev->irq.ih1_work); 619 break; 620 case 2: 621 *adev->irq.ih2.wptr_cpu = wptr; 622 schedule_work(&adev->irq.ih2_work); 623 break; 624 default: break; 625 } 626 return 0; 627} 628 629static const struct amdgpu_irq_src_funcs navi10_ih_self_irq_funcs = { 630 .process = navi10_ih_self_irq, 631}; 632 633static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) 634{ 635 adev->irq.self_irq.num_types = 0; 636 adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; 637} 638 639static int navi10_ih_early_init(void *handle) 640{ 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 643 navi10_ih_set_interrupt_funcs(adev); 644 navi10_ih_set_self_irq_funcs(adev); 645 return 0; 646} 647 648static int navi10_ih_sw_init(void *handle) 649{ 650 int r; 651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 652 bool use_bus_addr; 653 654 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, 655 &adev->irq.self_irq); 656 657 if (r) 658 return r; 659 660 /* use gpu virtual address for ih ring 661 * until ih_checken is programmed to allow 662 * use bus address for ih ring by psp bl */ 663 use_bus_addr = 664 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true; 665 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 666 if (r) 667 return r; 668 669 adev->irq.ih.use_doorbell = true; 670 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 671 672 adev->irq.ih1.ring_size = 0; 673 adev->irq.ih2.ring_size = 0; 674 675 if (adev->asic_type < CHIP_NAVI10) { 676 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); 677 if (r) 678 return r; 679 680 adev->irq.ih1.use_doorbell = true; 681 adev->irq.ih1.doorbell_index = 682 (adev->doorbell_index.ih + 1) << 1; 683 684 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); 685 if (r) 686 return r; 687 688 adev->irq.ih2.use_doorbell = true; 689 adev->irq.ih2.doorbell_index = 690 (adev->doorbell_index.ih + 2) << 1; 691 } 692 693 r = amdgpu_irq_init(adev); 694 695 return r; 696} 697 698static int navi10_ih_sw_fini(void *handle) 699{ 700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 701 702 amdgpu_irq_fini(adev); 703 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); 704 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); 705 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 706 707 return 0; 708} 709 710static int navi10_ih_hw_init(void *handle) 711{ 712 int r; 713 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 714 715 r = navi10_ih_irq_init(adev); 716 if (r) 717 return r; 718 719 return 0; 720} 721 722static int navi10_ih_hw_fini(void *handle) 723{ 724 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 725 726 navi10_ih_irq_disable(adev); 727 728 return 0; 729} 730 731static int navi10_ih_suspend(void *handle) 732{ 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 735 return navi10_ih_hw_fini(adev); 736} 737 738static int navi10_ih_resume(void *handle) 739{ 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 return navi10_ih_hw_init(adev); 743} 744 745static bool navi10_ih_is_idle(void *handle) 746{ 747 /* todo */ 748 return true; 749} 750 751static int navi10_ih_wait_for_idle(void *handle) 752{ 753 /* todo */ 754 return -ETIMEDOUT; 755} 756 757static int navi10_ih_soft_reset(void *handle) 758{ 759 /* todo */ 760 return 0; 761} 762 763static void navi10_ih_update_clockgating_state(struct amdgpu_device *adev, 764 bool enable) 765{ 766 uint32_t data, def, field_val; 767 768 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 769 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL); 770 field_val = enable ? 0 : 1; 771 data = REG_SET_FIELD(data, IH_CLK_CTRL, 772 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 773 data = REG_SET_FIELD(data, IH_CLK_CTRL, 774 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 775 data = REG_SET_FIELD(data, IH_CLK_CTRL, 776 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 777 data = REG_SET_FIELD(data, IH_CLK_CTRL, 778 DYN_CLK_SOFT_OVERRIDE, field_val); 779 data = REG_SET_FIELD(data, IH_CLK_CTRL, 780 REG_CLK_SOFT_OVERRIDE, field_val); 781 if (def != data) 782 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); 783 } 784 785 return; 786} 787 788static int navi10_ih_set_clockgating_state(void *handle, 789 enum amd_clockgating_state state) 790{ 791 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 792 793 navi10_ih_update_clockgating_state(adev, 794 state == AMD_CG_STATE_GATE); 795 return 0; 796} 797 798static int navi10_ih_set_powergating_state(void *handle, 799 enum amd_powergating_state state) 800{ 801 return 0; 802} 803 804static void navi10_ih_get_clockgating_state(void *handle, u32 *flags) 805{ 806 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 807 808 if (!RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL)) 809 *flags |= AMD_CG_SUPPORT_IH_CG; 810 811 return; 812} 813 814static const struct amd_ip_funcs navi10_ih_ip_funcs = { 815 .name = "navi10_ih", 816 .early_init = navi10_ih_early_init, 817 .late_init = NULL, 818 .sw_init = navi10_ih_sw_init, 819 .sw_fini = navi10_ih_sw_fini, 820 .hw_init = navi10_ih_hw_init, 821 .hw_fini = navi10_ih_hw_fini, 822 .suspend = navi10_ih_suspend, 823 .resume = navi10_ih_resume, 824 .is_idle = navi10_ih_is_idle, 825 .wait_for_idle = navi10_ih_wait_for_idle, 826 .soft_reset = navi10_ih_soft_reset, 827 .set_clockgating_state = navi10_ih_set_clockgating_state, 828 .set_powergating_state = navi10_ih_set_powergating_state, 829 .get_clockgating_state = navi10_ih_get_clockgating_state, 830}; 831 832static const struct amdgpu_ih_funcs navi10_ih_funcs = { 833 .get_wptr = navi10_ih_get_wptr, 834 .decode_iv = navi10_ih_decode_iv, 835 .set_rptr = navi10_ih_set_rptr 836}; 837 838static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev) 839{ 840 if (adev->irq.ih_funcs == NULL) 841 adev->irq.ih_funcs = &navi10_ih_funcs; 842} 843 844const struct amdgpu_ip_block_version navi10_ih_ip_block = 845{ 846 .type = AMD_IP_BLOCK_TYPE_IH, 847 .major = 5, 848 .minor = 0, 849 .rev = 0, 850 .funcs = &navi10_ih_ip_funcs, 851}; 852