18c2ecf20Sopenharmony_ci/*
28c2ecf20Sopenharmony_ci * Copyright (C) 2019  Advanced Micro Devices, Inc.
38c2ecf20Sopenharmony_ci *
48c2ecf20Sopenharmony_ci * Permission is hereby granted, free of charge, to any person obtaining a
58c2ecf20Sopenharmony_ci * copy of this software and associated documentation files (the "Software"),
68c2ecf20Sopenharmony_ci * to deal in the Software without restriction, including without limitation
78c2ecf20Sopenharmony_ci * the rights to use, copy, modify, merge, publish, distribute, sublicense,
88c2ecf20Sopenharmony_ci * and/or sell copies of the Software, and to permit persons to whom the
98c2ecf20Sopenharmony_ci * Software is furnished to do so, subject to the following conditions:
108c2ecf20Sopenharmony_ci *
118c2ecf20Sopenharmony_ci * The above copyright notice and this permission notice shall be included
128c2ecf20Sopenharmony_ci * in all copies or substantial portions of the Software.
138c2ecf20Sopenharmony_ci *
148c2ecf20Sopenharmony_ci * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
158c2ecf20Sopenharmony_ci * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
168c2ecf20Sopenharmony_ci * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
178c2ecf20Sopenharmony_ci * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
188c2ecf20Sopenharmony_ci * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
198c2ecf20Sopenharmony_ci * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
208c2ecf20Sopenharmony_ci */
218c2ecf20Sopenharmony_ci#ifndef __AMDGPU_MMHUB_H__
228c2ecf20Sopenharmony_ci#define __AMDGPU_MMHUB_H__
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_cistruct amdgpu_mmhub_funcs {
258c2ecf20Sopenharmony_ci	void (*ras_init)(struct amdgpu_device *adev);
268c2ecf20Sopenharmony_ci	int (*ras_late_init)(struct amdgpu_device *adev);
278c2ecf20Sopenharmony_ci	void (*query_ras_error_count)(struct amdgpu_device *adev,
288c2ecf20Sopenharmony_ci					void *ras_error_status);
298c2ecf20Sopenharmony_ci	void (*reset_ras_error_count)(struct amdgpu_device *adev);
308c2ecf20Sopenharmony_ci	u64 (*get_fb_location)(struct amdgpu_device *adev);
318c2ecf20Sopenharmony_ci	void (*init)(struct amdgpu_device *adev);
328c2ecf20Sopenharmony_ci	int (*gart_enable)(struct amdgpu_device *adev);
338c2ecf20Sopenharmony_ci	void (*set_fault_enable_default)(struct amdgpu_device *adev,
348c2ecf20Sopenharmony_ci			bool value);
358c2ecf20Sopenharmony_ci	void (*gart_disable)(struct amdgpu_device *adev);
368c2ecf20Sopenharmony_ci	int (*set_clockgating)(struct amdgpu_device *adev,
378c2ecf20Sopenharmony_ci			       enum amd_clockgating_state state);
388c2ecf20Sopenharmony_ci	void (*get_clockgating)(struct amdgpu_device *adev, u32 *flags);
398c2ecf20Sopenharmony_ci	void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid,
408c2ecf20Sopenharmony_ci				uint64_t page_table_base);
418c2ecf20Sopenharmony_ci	void (*update_power_gating)(struct amdgpu_device *adev,
428c2ecf20Sopenharmony_ci                                bool enable);
438c2ecf20Sopenharmony_ci	void (*query_ras_error_status)(struct amdgpu_device *adev);
448c2ecf20Sopenharmony_ci};
458c2ecf20Sopenharmony_ci
468c2ecf20Sopenharmony_cistruct amdgpu_mmhub {
478c2ecf20Sopenharmony_ci	struct ras_common_if *ras_if;
488c2ecf20Sopenharmony_ci	const struct amdgpu_mmhub_funcs *funcs;
498c2ecf20Sopenharmony_ci};
508c2ecf20Sopenharmony_ci
518c2ecf20Sopenharmony_ciint amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
528c2ecf20Sopenharmony_civoid amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
538c2ecf20Sopenharmony_ci#endif
548c2ecf20Sopenharmony_ci
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