1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include "amdgpu.h" 30#include <drm/drm_debugfs.h> 31#include <drm/amdgpu_drm.h> 32#include "amdgpu_sched.h" 33#include "amdgpu_uvd.h" 34#include "amdgpu_vce.h" 35#include "atom.h" 36 37#include <linux/vga_switcheroo.h> 38#include <linux/slab.h> 39#include <linux/uaccess.h> 40#include <linux/pci.h> 41#include <linux/pm_runtime.h> 42#include "amdgpu_amdkfd.h" 43#include "amdgpu_gem.h" 44#include "amdgpu_display.h" 45#include "amdgpu_ras.h" 46 47void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 48{ 49 struct amdgpu_gpu_instance *gpu_instance; 50 int i; 51 52 mutex_lock(&mgpu_info.mutex); 53 54 for (i = 0; i < mgpu_info.num_gpu; i++) { 55 gpu_instance = &(mgpu_info.gpu_ins[i]); 56 if (gpu_instance->adev == adev) { 57 mgpu_info.gpu_ins[i] = 58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 59 mgpu_info.num_gpu--; 60 if (adev->flags & AMD_IS_APU) 61 mgpu_info.num_apu--; 62 else 63 mgpu_info.num_dgpu--; 64 break; 65 } 66 } 67 68 mutex_unlock(&mgpu_info.mutex); 69} 70 71/** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79void amdgpu_driver_unload_kms(struct drm_device *dev) 80{ 81 struct amdgpu_device *adev = drm_to_adev(dev); 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 return; 90 91 if (adev->runpm) { 92 pm_runtime_get_sync(dev->dev); 93 pm_runtime_forbid(dev->dev); 94 } 95 96 amdgpu_acpi_fini(adev); 97 amdgpu_device_fini(adev); 98} 99 100void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 101{ 102 struct amdgpu_gpu_instance *gpu_instance; 103 104 mutex_lock(&mgpu_info.mutex); 105 106 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 107 DRM_ERROR("Cannot register more gpu instance\n"); 108 mutex_unlock(&mgpu_info.mutex); 109 return; 110 } 111 112 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 113 gpu_instance->adev = adev; 114 gpu_instance->mgpu_fan_enabled = 0; 115 116 mgpu_info.num_gpu++; 117 if (adev->flags & AMD_IS_APU) 118 mgpu_info.num_apu++; 119 else 120 mgpu_info.num_dgpu++; 121 122 mutex_unlock(&mgpu_info.mutex); 123} 124 125/** 126 * amdgpu_driver_load_kms - Main load function for KMS. 127 * 128 * @adev: pointer to struct amdgpu_device 129 * @flags: device flags 130 * 131 * This is the main load function for KMS (all asics). 132 * Returns 0 on success, error on failure. 133 */ 134int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 135{ 136 struct drm_device *dev; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 if (amdgpu_has_atpx() && 142 (amdgpu_is_atpx_hybrid() || 143 amdgpu_has_atpx_dgpu_power_cntl()) && 144 ((flags & AMD_IS_APU) == 0) && 145 !pci_is_thunderbolt_attached(dev->pdev)) 146 flags |= AMD_IS_PX; 147 148 /* amdgpu_device_init should report only fatal error 149 * like memory allocation failure or iomapping failure, 150 * or memory manager initialization failure, it must 151 * properly initialize the GPU MC controller and permit 152 * VRAM allocation 153 */ 154 r = amdgpu_device_init(adev, flags); 155 if (r) { 156 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 157 goto out; 158 } 159 160 if (amdgpu_device_supports_boco(dev) && 161 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */ 162 adev->runpm = true; 163 } else if (amdgpu_device_supports_baco(dev) && 164 (amdgpu_runtime_pm != 0)) { 165 switch (adev->asic_type) { 166#ifdef CONFIG_DRM_AMDGPU_CIK 167 case CHIP_BONAIRE: 168 case CHIP_HAWAII: 169#endif 170 case CHIP_VEGA20: 171 case CHIP_ARCTURUS: 172 case CHIP_SIENNA_CICHLID: 173 case CHIP_NAVY_FLOUNDER: 174 /* enable runpm if runpm=1 */ 175 if (amdgpu_runtime_pm > 0) 176 adev->runpm = true; 177 break; 178 case CHIP_VEGA10: 179 /* turn runpm on if noretry=0 */ 180 if (!adev->gmc.noretry) 181 adev->runpm = true; 182 break; 183 default: 184 /* enable runpm on VI+ */ 185 adev->runpm = true; 186 break; 187 } 188 } 189 190 /* Call ACPI methods: require modeset init 191 * but failure is not fatal 192 */ 193 194 acpi_status = amdgpu_acpi_init(adev); 195 if (acpi_status) 196 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n"); 197 198 if (adev->runpm) { 199 /* only need to skip on ATPX */ 200 if (amdgpu_device_supports_boco(dev) && 201 !amdgpu_is_atpx_hybrid()) 202 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 203 pm_runtime_use_autosuspend(dev->dev); 204 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 205 pm_runtime_allow(dev->dev); 206 pm_runtime_mark_last_busy(dev->dev); 207 pm_runtime_put_autosuspend(dev->dev); 208 } 209 210out: 211 if (r) { 212 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */ 213 if (adev->rmmio && adev->runpm) 214 pm_runtime_put_noidle(dev->dev); 215 amdgpu_driver_unload_kms(dev); 216 } 217 218 return r; 219} 220 221static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 222 struct drm_amdgpu_query_fw *query_fw, 223 struct amdgpu_device *adev) 224{ 225 switch (query_fw->fw_type) { 226 case AMDGPU_INFO_FW_VCE: 227 fw_info->ver = adev->vce.fw_version; 228 fw_info->feature = adev->vce.fb_version; 229 break; 230 case AMDGPU_INFO_FW_UVD: 231 fw_info->ver = adev->uvd.fw_version; 232 fw_info->feature = 0; 233 break; 234 case AMDGPU_INFO_FW_VCN: 235 fw_info->ver = adev->vcn.fw_version; 236 fw_info->feature = 0; 237 break; 238 case AMDGPU_INFO_FW_GMC: 239 fw_info->ver = adev->gmc.fw_version; 240 fw_info->feature = 0; 241 break; 242 case AMDGPU_INFO_FW_GFX_ME: 243 fw_info->ver = adev->gfx.me_fw_version; 244 fw_info->feature = adev->gfx.me_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_PFP: 247 fw_info->ver = adev->gfx.pfp_fw_version; 248 fw_info->feature = adev->gfx.pfp_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_CE: 251 fw_info->ver = adev->gfx.ce_fw_version; 252 fw_info->feature = adev->gfx.ce_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLC: 255 fw_info->ver = adev->gfx.rlc_fw_version; 256 fw_info->feature = adev->gfx.rlc_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 259 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 260 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 263 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 264 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 265 break; 266 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 267 fw_info->ver = adev->gfx.rlc_srls_fw_version; 268 fw_info->feature = adev->gfx.rlc_srls_feature_version; 269 break; 270 case AMDGPU_INFO_FW_GFX_MEC: 271 if (query_fw->index == 0) { 272 fw_info->ver = adev->gfx.mec_fw_version; 273 fw_info->feature = adev->gfx.mec_feature_version; 274 } else if (query_fw->index == 1) { 275 fw_info->ver = adev->gfx.mec2_fw_version; 276 fw_info->feature = adev->gfx.mec2_feature_version; 277 } else 278 return -EINVAL; 279 break; 280 case AMDGPU_INFO_FW_SMC: 281 fw_info->ver = adev->pm.fw_version; 282 fw_info->feature = 0; 283 break; 284 case AMDGPU_INFO_FW_TA: 285 switch (query_fw->index) { 286 case 0: 287 fw_info->ver = adev->psp.ta_fw_version; 288 fw_info->feature = adev->psp.ta_xgmi_ucode_version; 289 break; 290 case 1: 291 fw_info->ver = adev->psp.ta_fw_version; 292 fw_info->feature = adev->psp.ta_ras_ucode_version; 293 break; 294 case 2: 295 fw_info->ver = adev->psp.ta_fw_version; 296 fw_info->feature = adev->psp.ta_hdcp_ucode_version; 297 break; 298 case 3: 299 fw_info->ver = adev->psp.ta_fw_version; 300 fw_info->feature = adev->psp.ta_dtm_ucode_version; 301 break; 302 default: 303 return -EINVAL; 304 } 305 break; 306 case AMDGPU_INFO_FW_SDMA: 307 if (query_fw->index >= adev->sdma.num_instances) 308 return -EINVAL; 309 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 310 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 311 break; 312 case AMDGPU_INFO_FW_SOS: 313 fw_info->ver = adev->psp.sos_fw_version; 314 fw_info->feature = adev->psp.sos_feature_version; 315 break; 316 case AMDGPU_INFO_FW_ASD: 317 fw_info->ver = adev->psp.asd_fw_version; 318 fw_info->feature = adev->psp.asd_feature_version; 319 break; 320 case AMDGPU_INFO_FW_DMCU: 321 fw_info->ver = adev->dm.dmcu_fw_version; 322 fw_info->feature = 0; 323 break; 324 case AMDGPU_INFO_FW_DMCUB: 325 fw_info->ver = adev->dm.dmcub_fw_version; 326 fw_info->feature = 0; 327 break; 328 default: 329 return -EINVAL; 330 } 331 return 0; 332} 333 334static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 335 struct drm_amdgpu_info *info, 336 struct drm_amdgpu_info_hw_ip *result) 337{ 338 uint32_t ib_start_alignment = 0; 339 uint32_t ib_size_alignment = 0; 340 enum amd_ip_block_type type; 341 unsigned int num_rings = 0; 342 unsigned int i, j; 343 344 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 345 return -EINVAL; 346 347 switch (info->query_hw_ip.type) { 348 case AMDGPU_HW_IP_GFX: 349 type = AMD_IP_BLOCK_TYPE_GFX; 350 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 351 if (adev->gfx.gfx_ring[i].sched.ready) 352 ++num_rings; 353 ib_start_alignment = 32; 354 ib_size_alignment = 32; 355 break; 356 case AMDGPU_HW_IP_COMPUTE: 357 type = AMD_IP_BLOCK_TYPE_GFX; 358 for (i = 0; i < adev->gfx.num_compute_rings; i++) 359 if (adev->gfx.compute_ring[i].sched.ready) 360 ++num_rings; 361 ib_start_alignment = 32; 362 ib_size_alignment = 32; 363 break; 364 case AMDGPU_HW_IP_DMA: 365 type = AMD_IP_BLOCK_TYPE_SDMA; 366 for (i = 0; i < adev->sdma.num_instances; i++) 367 if (adev->sdma.instance[i].ring.sched.ready) 368 ++num_rings; 369 ib_start_alignment = 256; 370 ib_size_alignment = 4; 371 break; 372 case AMDGPU_HW_IP_UVD: 373 type = AMD_IP_BLOCK_TYPE_UVD; 374 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 375 if (adev->uvd.harvest_config & (1 << i)) 376 continue; 377 378 if (adev->uvd.inst[i].ring.sched.ready) 379 ++num_rings; 380 } 381 ib_start_alignment = 64; 382 ib_size_alignment = 64; 383 break; 384 case AMDGPU_HW_IP_VCE: 385 type = AMD_IP_BLOCK_TYPE_VCE; 386 for (i = 0; i < adev->vce.num_rings; i++) 387 if (adev->vce.ring[i].sched.ready) 388 ++num_rings; 389 ib_start_alignment = 4; 390 ib_size_alignment = 1; 391 break; 392 case AMDGPU_HW_IP_UVD_ENC: 393 type = AMD_IP_BLOCK_TYPE_UVD; 394 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 395 if (adev->uvd.harvest_config & (1 << i)) 396 continue; 397 398 for (j = 0; j < adev->uvd.num_enc_rings; j++) 399 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 400 ++num_rings; 401 } 402 ib_start_alignment = 64; 403 ib_size_alignment = 64; 404 break; 405 case AMDGPU_HW_IP_VCN_DEC: 406 type = AMD_IP_BLOCK_TYPE_VCN; 407 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 408 if (adev->uvd.harvest_config & (1 << i)) 409 continue; 410 411 if (adev->vcn.inst[i].ring_dec.sched.ready) 412 ++num_rings; 413 } 414 ib_start_alignment = 16; 415 ib_size_alignment = 16; 416 break; 417 case AMDGPU_HW_IP_VCN_ENC: 418 type = AMD_IP_BLOCK_TYPE_VCN; 419 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 420 if (adev->uvd.harvest_config & (1 << i)) 421 continue; 422 423 for (j = 0; j < adev->vcn.num_enc_rings; j++) 424 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 425 ++num_rings; 426 } 427 ib_start_alignment = 64; 428 ib_size_alignment = 1; 429 break; 430 case AMDGPU_HW_IP_VCN_JPEG: 431 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 432 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 433 434 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 435 if (adev->jpeg.harvest_config & (1 << i)) 436 continue; 437 438 if (adev->jpeg.inst[i].ring_dec.sched.ready) 439 ++num_rings; 440 } 441 ib_start_alignment = 16; 442 ib_size_alignment = 16; 443 break; 444 default: 445 return -EINVAL; 446 } 447 448 for (i = 0; i < adev->num_ip_blocks; i++) 449 if (adev->ip_blocks[i].version->type == type && 450 adev->ip_blocks[i].status.valid) 451 break; 452 453 if (i == adev->num_ip_blocks) 454 return 0; 455 456 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 457 num_rings); 458 459 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 460 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 461 result->capabilities_flags = 0; 462 result->available_rings = (1 << num_rings) - 1; 463 result->ib_start_alignment = ib_start_alignment; 464 result->ib_size_alignment = ib_size_alignment; 465 return 0; 466} 467 468/* 469 * Userspace get information ioctl 470 */ 471/** 472 * amdgpu_info_ioctl - answer a device specific request. 473 * 474 * @adev: amdgpu device pointer 475 * @data: request object 476 * @filp: drm filp 477 * 478 * This function is used to pass device specific parameters to the userspace 479 * drivers. Examples include: pci device id, pipeline parms, tiling params, 480 * etc. (all asics). 481 * Returns 0 on success, -EINVAL on failure. 482 */ 483static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 484{ 485 struct amdgpu_device *adev = drm_to_adev(dev); 486 struct drm_amdgpu_info *info = data; 487 struct amdgpu_mode_info *minfo = &adev->mode_info; 488 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 489 uint32_t size = info->return_size; 490 struct drm_crtc *crtc; 491 uint32_t ui32 = 0; 492 uint64_t ui64 = 0; 493 int i, found; 494 int ui32_size = sizeof(ui32); 495 496 if (!info->return_size || !info->return_pointer) 497 return -EINVAL; 498 499 switch (info->query) { 500 case AMDGPU_INFO_ACCEL_WORKING: 501 ui32 = adev->accel_working; 502 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 503 case AMDGPU_INFO_CRTC_FROM_ID: 504 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 505 crtc = (struct drm_crtc *)minfo->crtcs[i]; 506 if (crtc && crtc->base.id == info->mode_crtc.id) { 507 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 508 509 ui32 = amdgpu_crtc->crtc_id; 510 found = 1; 511 break; 512 } 513 } 514 if (!found) { 515 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 516 return -EINVAL; 517 } 518 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 519 case AMDGPU_INFO_HW_IP_INFO: { 520 struct drm_amdgpu_info_hw_ip ip = {}; 521 int ret; 522 523 ret = amdgpu_hw_ip_info(adev, info, &ip); 524 if (ret) 525 return ret; 526 527 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); 528 return ret ? -EFAULT : 0; 529 } 530 case AMDGPU_INFO_HW_IP_COUNT: { 531 enum amd_ip_block_type type; 532 uint32_t count = 0; 533 534 switch (info->query_hw_ip.type) { 535 case AMDGPU_HW_IP_GFX: 536 type = AMD_IP_BLOCK_TYPE_GFX; 537 break; 538 case AMDGPU_HW_IP_COMPUTE: 539 type = AMD_IP_BLOCK_TYPE_GFX; 540 break; 541 case AMDGPU_HW_IP_DMA: 542 type = AMD_IP_BLOCK_TYPE_SDMA; 543 break; 544 case AMDGPU_HW_IP_UVD: 545 type = AMD_IP_BLOCK_TYPE_UVD; 546 break; 547 case AMDGPU_HW_IP_VCE: 548 type = AMD_IP_BLOCK_TYPE_VCE; 549 break; 550 case AMDGPU_HW_IP_UVD_ENC: 551 type = AMD_IP_BLOCK_TYPE_UVD; 552 break; 553 case AMDGPU_HW_IP_VCN_DEC: 554 case AMDGPU_HW_IP_VCN_ENC: 555 type = AMD_IP_BLOCK_TYPE_VCN; 556 break; 557 case AMDGPU_HW_IP_VCN_JPEG: 558 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 559 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 for (i = 0; i < adev->num_ip_blocks; i++) 566 if (adev->ip_blocks[i].version->type == type && 567 adev->ip_blocks[i].status.valid && 568 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 569 count++; 570 571 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 572 } 573 case AMDGPU_INFO_TIMESTAMP: 574 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 575 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 576 case AMDGPU_INFO_FW_VERSION: { 577 struct drm_amdgpu_info_firmware fw_info; 578 int ret; 579 580 /* We only support one instance of each IP block right now. */ 581 if (info->query_fw.ip_instance != 0) 582 return -EINVAL; 583 584 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 585 if (ret) 586 return ret; 587 588 return copy_to_user(out, &fw_info, 589 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 590 } 591 case AMDGPU_INFO_NUM_BYTES_MOVED: 592 ui64 = atomic64_read(&adev->num_bytes_moved); 593 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 594 case AMDGPU_INFO_NUM_EVICTIONS: 595 ui64 = atomic64_read(&adev->num_evictions); 596 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 597 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 598 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 600 case AMDGPU_INFO_VRAM_USAGE: 601 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 603 case AMDGPU_INFO_VIS_VRAM_USAGE: 604 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM)); 605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 606 case AMDGPU_INFO_GTT_USAGE: 607 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)); 608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 609 case AMDGPU_INFO_GDS_CONFIG: { 610 struct drm_amdgpu_info_gds gds_info; 611 612 memset(&gds_info, 0, sizeof(gds_info)); 613 gds_info.compute_partition_size = adev->gds.gds_size; 614 gds_info.gds_total_size = adev->gds.gds_size; 615 gds_info.gws_per_compute_partition = adev->gds.gws_size; 616 gds_info.oa_per_compute_partition = adev->gds.oa_size; 617 return copy_to_user(out, &gds_info, 618 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 619 } 620 case AMDGPU_INFO_VRAM_GTT: { 621 struct drm_amdgpu_info_vram_gtt vram_gtt; 622 623 vram_gtt.vram_size = adev->gmc.real_vram_size - 624 atomic64_read(&adev->vram_pin_size) - 625 AMDGPU_VM_RESERVED_VRAM; 626 vram_gtt.vram_cpu_accessible_size = 627 min(adev->gmc.visible_vram_size - 628 atomic64_read(&adev->visible_pin_size), 629 vram_gtt.vram_size); 630 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 631 vram_gtt.gtt_size *= PAGE_SIZE; 632 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 633 return copy_to_user(out, &vram_gtt, 634 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 635 } 636 case AMDGPU_INFO_MEMORY: { 637 struct drm_amdgpu_memory_info mem; 638 struct ttm_resource_manager *vram_man = 639 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 640 struct ttm_resource_manager *gtt_man = 641 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 642 memset(&mem, 0, sizeof(mem)); 643 mem.vram.total_heap_size = adev->gmc.real_vram_size; 644 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 645 atomic64_read(&adev->vram_pin_size) - 646 AMDGPU_VM_RESERVED_VRAM; 647 mem.vram.heap_usage = 648 amdgpu_vram_mgr_usage(vram_man); 649 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 650 651 mem.cpu_accessible_vram.total_heap_size = 652 adev->gmc.visible_vram_size; 653 mem.cpu_accessible_vram.usable_heap_size = 654 min(adev->gmc.visible_vram_size - 655 atomic64_read(&adev->visible_pin_size), 656 mem.vram.usable_heap_size); 657 mem.cpu_accessible_vram.heap_usage = 658 amdgpu_vram_mgr_vis_usage(vram_man); 659 mem.cpu_accessible_vram.max_allocation = 660 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 661 662 mem.gtt.total_heap_size = gtt_man->size; 663 mem.gtt.total_heap_size *= PAGE_SIZE; 664 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 665 atomic64_read(&adev->gart_pin_size); 666 mem.gtt.heap_usage = 667 amdgpu_gtt_mgr_usage(gtt_man); 668 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 669 670 return copy_to_user(out, &mem, 671 min((size_t)size, sizeof(mem))) 672 ? -EFAULT : 0; 673 } 674 case AMDGPU_INFO_READ_MMR_REG: { 675 unsigned int n, alloc_size; 676 uint32_t *regs; 677 unsigned int se_num = (info->read_mmr_reg.instance >> 678 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 679 AMDGPU_INFO_MMR_SE_INDEX_MASK; 680 unsigned int sh_num = (info->read_mmr_reg.instance >> 681 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 682 AMDGPU_INFO_MMR_SH_INDEX_MASK; 683 684 /* set full masks if the userspace set all bits 685 * in the bitfields 686 */ 687 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 688 se_num = 0xffffffff; 689 else if (se_num >= AMDGPU_GFX_MAX_SE) 690 return -EINVAL; 691 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 692 sh_num = 0xffffffff; 693 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 694 return -EINVAL; 695 696 if (info->read_mmr_reg.count > 128) 697 return -EINVAL; 698 699 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 700 if (!regs) 701 return -ENOMEM; 702 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 703 704 amdgpu_gfx_off_ctrl(adev, false); 705 for (i = 0; i < info->read_mmr_reg.count; i++) { 706 if (amdgpu_asic_read_register(adev, se_num, sh_num, 707 info->read_mmr_reg.dword_offset + i, 708 ®s[i])) { 709 DRM_DEBUG_KMS("unallowed offset %#x\n", 710 info->read_mmr_reg.dword_offset + i); 711 kfree(regs); 712 amdgpu_gfx_off_ctrl(adev, true); 713 return -EFAULT; 714 } 715 } 716 amdgpu_gfx_off_ctrl(adev, true); 717 n = copy_to_user(out, regs, min(size, alloc_size)); 718 kfree(regs); 719 return n ? -EFAULT : 0; 720 } 721 case AMDGPU_INFO_DEV_INFO: { 722 struct drm_amdgpu_info_device dev_info; 723 uint64_t vm_size; 724 725 memset(&dev_info, 0, sizeof(dev_info)); 726 dev_info.device_id = dev->pdev->device; 727 dev_info.chip_rev = adev->rev_id; 728 dev_info.external_rev = adev->external_rev_id; 729 dev_info.pci_rev = dev->pdev->revision; 730 dev_info.family = adev->family; 731 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 732 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 733 /* return all clocks in KHz */ 734 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 735 if (adev->pm.dpm_enabled) { 736 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 737 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 738 } else { 739 dev_info.max_engine_clock = adev->clock.default_sclk * 10; 740 dev_info.max_memory_clock = adev->clock.default_mclk * 10; 741 } 742 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 743 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 744 adev->gfx.config.max_shader_engines; 745 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 746 dev_info._pad = 0; 747 dev_info.ids_flags = 0; 748 if (adev->flags & AMD_IS_APU) 749 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 750 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 751 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 752 if (amdgpu_is_tmz(adev)) 753 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 754 755 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 756 vm_size -= AMDGPU_VA_RESERVED_SIZE; 757 758 /* Older VCE FW versions are buggy and can handle only 40bits */ 759 if (adev->vce.fw_version && 760 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 761 vm_size = min(vm_size, 1ULL << 40); 762 763 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 764 dev_info.virtual_address_max = 765 min(vm_size, AMDGPU_GMC_HOLE_START); 766 767 if (vm_size > AMDGPU_GMC_HOLE_START) { 768 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END; 769 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 770 } 771 dev_info.virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 772 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 773 dev_info.gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 774 dev_info.cu_active_number = adev->gfx.cu_info.number; 775 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 776 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 777 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 778 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 779 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 780 sizeof(adev->gfx.cu_info.bitmap)); 781 dev_info.vram_type = adev->gmc.vram_type; 782 dev_info.vram_bit_width = adev->gmc.vram_width; 783 dev_info.vce_harvest_config = adev->vce.harvest_config; 784 dev_info.gc_double_offchip_lds_buf = 785 adev->gfx.config.double_offchip_lds_buf; 786 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size; 787 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs; 788 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 789 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 790 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 791 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 792 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 793 794 if (adev->family >= AMDGPU_FAMILY_NV) 795 dev_info.pa_sc_tile_steering_override = 796 adev->gfx.config.pa_sc_tile_steering_override; 797 798 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 799 800 return copy_to_user(out, &dev_info, 801 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 802 } 803 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 804 unsigned int i; 805 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 806 struct amd_vce_state *vce_state; 807 808 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 809 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 810 if (vce_state) { 811 vce_clk_table.entries[i].sclk = vce_state->sclk; 812 vce_clk_table.entries[i].mclk = vce_state->mclk; 813 vce_clk_table.entries[i].eclk = vce_state->evclk; 814 vce_clk_table.num_valid_entries++; 815 } 816 } 817 818 return copy_to_user(out, &vce_clk_table, 819 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 820 } 821 case AMDGPU_INFO_VBIOS: { 822 uint32_t bios_size = adev->bios_size; 823 824 switch (info->vbios_info.type) { 825 case AMDGPU_INFO_VBIOS_SIZE: 826 return copy_to_user(out, &bios_size, 827 min((size_t)size, sizeof(bios_size))) 828 ? -EFAULT : 0; 829 case AMDGPU_INFO_VBIOS_IMAGE: { 830 uint8_t *bios; 831 uint32_t bios_offset = info->vbios_info.offset; 832 833 if (bios_offset >= bios_size) 834 return -EINVAL; 835 836 bios = adev->bios + bios_offset; 837 return copy_to_user(out, bios, 838 min((size_t)size, (size_t)(bios_size - bios_offset))) 839 ? -EFAULT : 0; 840 } 841 default: 842 DRM_DEBUG_KMS("Invalid request %d\n", 843 info->vbios_info.type); 844 return -EINVAL; 845 } 846 } 847 case AMDGPU_INFO_NUM_HANDLES: { 848 struct drm_amdgpu_info_num_handles handle; 849 850 switch (info->query_hw_ip.type) { 851 case AMDGPU_HW_IP_UVD: 852 /* Starting Polaris, we support unlimited UVD handles */ 853 if (adev->asic_type < CHIP_POLARIS10) { 854 handle.uvd_max_handles = adev->uvd.max_handles; 855 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 856 857 return copy_to_user(out, &handle, 858 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 859 } else { 860 return -ENODATA; 861 } 862 863 break; 864 default: 865 return -EINVAL; 866 } 867 } 868 case AMDGPU_INFO_SENSOR: { 869 if (!adev->pm.dpm_enabled) 870 return -ENOENT; 871 872 switch (info->sensor_info.type) { 873 case AMDGPU_INFO_SENSOR_GFX_SCLK: 874 /* get sclk in Mhz */ 875 if (amdgpu_dpm_read_sensor(adev, 876 AMDGPU_PP_SENSOR_GFX_SCLK, 877 (void *)&ui32, &ui32_size)) { 878 return -EINVAL; 879 } 880 ui32 /= 100; 881 break; 882 case AMDGPU_INFO_SENSOR_GFX_MCLK: 883 /* get mclk in Mhz */ 884 if (amdgpu_dpm_read_sensor(adev, 885 AMDGPU_PP_SENSOR_GFX_MCLK, 886 (void *)&ui32, &ui32_size)) { 887 return -EINVAL; 888 } 889 ui32 /= 100; 890 break; 891 case AMDGPU_INFO_SENSOR_GPU_TEMP: 892 /* get temperature in millidegrees C */ 893 if (amdgpu_dpm_read_sensor(adev, 894 AMDGPU_PP_SENSOR_GPU_TEMP, 895 (void *)&ui32, &ui32_size)) { 896 return -EINVAL; 897 } 898 break; 899 case AMDGPU_INFO_SENSOR_GPU_LOAD: 900 /* get GPU load */ 901 if (amdgpu_dpm_read_sensor(adev, 902 AMDGPU_PP_SENSOR_GPU_LOAD, 903 (void *)&ui32, &ui32_size)) { 904 return -EINVAL; 905 } 906 break; 907 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 908 /* get average GPU power */ 909 if (amdgpu_dpm_read_sensor(adev, 910 AMDGPU_PP_SENSOR_GPU_POWER, 911 (void *)&ui32, &ui32_size)) { 912 return -EINVAL; 913 } 914 ui32 >>= 8; 915 break; 916 case AMDGPU_INFO_SENSOR_VDDNB: 917 /* get VDDNB in millivolts */ 918 if (amdgpu_dpm_read_sensor(adev, 919 AMDGPU_PP_SENSOR_VDDNB, 920 (void *)&ui32, &ui32_size)) { 921 return -EINVAL; 922 } 923 break; 924 case AMDGPU_INFO_SENSOR_VDDGFX: 925 /* get VDDGFX in millivolts */ 926 if (amdgpu_dpm_read_sensor(adev, 927 AMDGPU_PP_SENSOR_VDDGFX, 928 (void *)&ui32, &ui32_size)) { 929 return -EINVAL; 930 } 931 break; 932 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 933 /* get stable pstate sclk in Mhz */ 934 if (amdgpu_dpm_read_sensor(adev, 935 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 936 (void *)&ui32, &ui32_size)) { 937 return -EINVAL; 938 } 939 ui32 /= 100; 940 break; 941 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 942 /* get stable pstate mclk in Mhz */ 943 if (amdgpu_dpm_read_sensor(adev, 944 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 945 (void *)&ui32, &ui32_size)) { 946 return -EINVAL; 947 } 948 ui32 /= 100; 949 break; 950 default: 951 DRM_DEBUG_KMS("Invalid request %d\n", 952 info->sensor_info.type); 953 return -EINVAL; 954 } 955 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 956 } 957 case AMDGPU_INFO_VRAM_LOST_COUNTER: 958 ui32 = atomic_read(&adev->vram_lost_counter); 959 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 960 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 961 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 962 uint64_t ras_mask; 963 964 if (!ras) 965 return -EINVAL; 966 ras_mask = (uint64_t)ras->supported << 32 | ras->features; 967 968 return copy_to_user(out, &ras_mask, 969 min_t(u64, size, sizeof(ras_mask))) ? 970 -EFAULT : 0; 971 } 972 default: 973 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 974 return -EINVAL; 975 } 976 return 0; 977} 978 979 980/* 981 * Outdated mess for old drm with Xorg being in charge (void function now). 982 */ 983/** 984 * amdgpu_driver_lastclose_kms - drm callback for last close 985 * 986 * @dev: drm dev pointer 987 * 988 * Switch vga_switcheroo state after last close (all asics). 989 */ 990void amdgpu_driver_lastclose_kms(struct drm_device *dev) 991{ 992 drm_fb_helper_lastclose(dev); 993 vga_switcheroo_process_delayed_switch(); 994} 995 996/** 997 * amdgpu_driver_open_kms - drm callback for open 998 * 999 * @dev: drm dev pointer 1000 * @file_priv: drm file 1001 * 1002 * On device open, init vm on cayman+ (all asics). 1003 * Returns 0 on success, error on failure. 1004 */ 1005int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1006{ 1007 struct amdgpu_device *adev = drm_to_adev(dev); 1008 struct amdgpu_fpriv *fpriv; 1009 int r, pasid; 1010 1011 /* Ensure IB tests are run on ring */ 1012 flush_delayed_work(&adev->delayed_init_work); 1013 1014 1015 if (amdgpu_ras_intr_triggered()) { 1016 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1017 return -EHWPOISON; 1018 } 1019 1020 file_priv->driver_priv = NULL; 1021 1022 r = pm_runtime_get_sync(dev->dev); 1023 if (r < 0) 1024 goto pm_put; 1025 1026 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1027 if (unlikely(!fpriv)) { 1028 r = -ENOMEM; 1029 goto out_suspend; 1030 } 1031 1032 pasid = amdgpu_pasid_alloc(16); 1033 if (pasid < 0) { 1034 dev_warn(adev->dev, "No more PASIDs available!"); 1035 pasid = 0; 1036 } 1037 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid); 1038 if (r) 1039 goto error_pasid; 1040 1041 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1042 if (!fpriv->prt_va) { 1043 r = -ENOMEM; 1044 goto error_vm; 1045 } 1046 1047 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1048 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1049 1050 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1051 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1052 if (r) 1053 goto error_vm; 1054 } 1055 1056 mutex_init(&fpriv->bo_list_lock); 1057 idr_init(&fpriv->bo_list_handles); 1058 1059 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 1060 1061 file_priv->driver_priv = fpriv; 1062 goto out_suspend; 1063 1064error_vm: 1065 amdgpu_vm_fini(adev, &fpriv->vm); 1066 1067error_pasid: 1068 if (pasid) 1069 amdgpu_pasid_free(pasid); 1070 1071 kfree(fpriv); 1072 1073out_suspend: 1074 pm_runtime_mark_last_busy(dev->dev); 1075pm_put: 1076 pm_runtime_put_autosuspend(dev->dev); 1077 1078 return r; 1079} 1080 1081/** 1082 * amdgpu_driver_postclose_kms - drm callback for post close 1083 * 1084 * @dev: drm dev pointer 1085 * @file_priv: drm file 1086 * 1087 * On device post close, tear down vm on cayman+ (all asics). 1088 */ 1089void amdgpu_driver_postclose_kms(struct drm_device *dev, 1090 struct drm_file *file_priv) 1091{ 1092 struct amdgpu_device *adev = drm_to_adev(dev); 1093 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1094 struct amdgpu_bo_list *list; 1095 struct amdgpu_bo *pd; 1096 u32 pasid; 1097 int handle; 1098 1099 if (!fpriv) 1100 return; 1101 1102 pm_runtime_get_sync(dev->dev); 1103 1104 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1105 amdgpu_uvd_free_handles(adev, file_priv); 1106 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1107 amdgpu_vce_free_handles(adev, file_priv); 1108 1109 amdgpu_vm_bo_rmv(adev, fpriv->prt_va); 1110 1111 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1112 /* TODO: how to handle reserve failure */ 1113 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1114 amdgpu_vm_bo_rmv(adev, fpriv->csa_va); 1115 fpriv->csa_va = NULL; 1116 amdgpu_bo_unreserve(adev->virt.csa_obj); 1117 } 1118 1119 pasid = fpriv->vm.pasid; 1120 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo); 1121 1122 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1123 amdgpu_vm_fini(adev, &fpriv->vm); 1124 1125 if (pasid) 1126 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1127 amdgpu_bo_unref(&pd); 1128 1129 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1130 amdgpu_bo_list_put(list); 1131 1132 idr_destroy(&fpriv->bo_list_handles); 1133 mutex_destroy(&fpriv->bo_list_lock); 1134 1135 kfree(fpriv); 1136 file_priv->driver_priv = NULL; 1137 1138 pm_runtime_mark_last_busy(dev->dev); 1139 pm_runtime_put_autosuspend(dev->dev); 1140} 1141 1142/* 1143 * VBlank related functions. 1144 */ 1145/** 1146 * amdgpu_get_vblank_counter_kms - get frame count 1147 * 1148 * @crtc: crtc to get the frame count from 1149 * 1150 * Gets the frame count on the requested crtc (all asics). 1151 * Returns frame count on success, -EINVAL on failure. 1152 */ 1153u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1154{ 1155 struct drm_device *dev = crtc->dev; 1156 unsigned int pipe = crtc->index; 1157 struct amdgpu_device *adev = drm_to_adev(dev); 1158 int vpos, hpos, stat; 1159 u32 count; 1160 1161 if (pipe >= adev->mode_info.num_crtc) { 1162 DRM_ERROR("Invalid crtc %u\n", pipe); 1163 return -EINVAL; 1164 } 1165 1166 /* The hw increments its frame counter at start of vsync, not at start 1167 * of vblank, as is required by DRM core vblank counter handling. 1168 * Cook the hw count here to make it appear to the caller as if it 1169 * incremented at start of vblank. We measure distance to start of 1170 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1171 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1172 * result by 1 to give the proper appearance to caller. 1173 */ 1174 if (adev->mode_info.crtcs[pipe]) { 1175 /* Repeat readout if needed to provide stable result if 1176 * we cross start of vsync during the queries. 1177 */ 1178 do { 1179 count = amdgpu_display_vblank_get_counter(adev, pipe); 1180 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1181 * vpos as distance to start of vblank, instead of 1182 * regular vertical scanout pos. 1183 */ 1184 stat = amdgpu_display_get_crtc_scanoutpos( 1185 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1186 &vpos, &hpos, NULL, NULL, 1187 &adev->mode_info.crtcs[pipe]->base.hwmode); 1188 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1189 1190 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1191 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1192 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1193 } else { 1194 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1195 pipe, vpos); 1196 1197 /* Bump counter if we are at >= leading edge of vblank, 1198 * but before vsync where vpos would turn negative and 1199 * the hw counter really increments. 1200 */ 1201 if (vpos >= 0) 1202 count++; 1203 } 1204 } else { 1205 /* Fallback to use value as is. */ 1206 count = amdgpu_display_vblank_get_counter(adev, pipe); 1207 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1208 } 1209 1210 return count; 1211} 1212 1213/** 1214 * amdgpu_enable_vblank_kms - enable vblank interrupt 1215 * 1216 * @crtc: crtc to enable vblank interrupt for 1217 * 1218 * Enable the interrupt on the requested crtc (all asics). 1219 * Returns 0 on success, -EINVAL on failure. 1220 */ 1221int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1222{ 1223 struct drm_device *dev = crtc->dev; 1224 unsigned int pipe = crtc->index; 1225 struct amdgpu_device *adev = drm_to_adev(dev); 1226 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1227 1228 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1229} 1230 1231/** 1232 * amdgpu_disable_vblank_kms - disable vblank interrupt 1233 * 1234 * @crtc: crtc to disable vblank interrupt for 1235 * 1236 * Disable the interrupt on the requested crtc (all asics). 1237 */ 1238void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1239{ 1240 struct drm_device *dev = crtc->dev; 1241 unsigned int pipe = crtc->index; 1242 struct amdgpu_device *adev = drm_to_adev(dev); 1243 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1244 1245 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1246} 1247 1248const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 1249 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1250 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1251 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1252 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 1253 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1254 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1255 /* KMS */ 1256 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1257 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1258 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1259 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1260 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1261 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1262 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1263 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1264 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 1265 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) 1266}; 1267const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 1268 1269/* 1270 * Debugfs info 1271 */ 1272#if defined(CONFIG_DEBUG_FS) 1273 1274static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data) 1275{ 1276 struct drm_info_node *node = (struct drm_info_node *) m->private; 1277 struct drm_device *dev = node->minor->dev; 1278 struct amdgpu_device *adev = drm_to_adev(dev); 1279 struct drm_amdgpu_info_firmware fw_info; 1280 struct drm_amdgpu_query_fw query_fw; 1281 struct atom_context *ctx = adev->mode_info.atom_context; 1282 int ret, i; 1283 1284 /* VCE */ 1285 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1286 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1287 if (ret) 1288 return ret; 1289 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1290 fw_info.feature, fw_info.ver); 1291 1292 /* UVD */ 1293 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1294 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1295 if (ret) 1296 return ret; 1297 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1298 fw_info.feature, fw_info.ver); 1299 1300 /* GMC */ 1301 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1302 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1303 if (ret) 1304 return ret; 1305 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1306 fw_info.feature, fw_info.ver); 1307 1308 /* ME */ 1309 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1310 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1311 if (ret) 1312 return ret; 1313 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1314 fw_info.feature, fw_info.ver); 1315 1316 /* PFP */ 1317 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1318 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1319 if (ret) 1320 return ret; 1321 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1322 fw_info.feature, fw_info.ver); 1323 1324 /* CE */ 1325 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1326 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1327 if (ret) 1328 return ret; 1329 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1330 fw_info.feature, fw_info.ver); 1331 1332 /* RLC */ 1333 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1334 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1335 if (ret) 1336 return ret; 1337 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1338 fw_info.feature, fw_info.ver); 1339 1340 /* RLC SAVE RESTORE LIST CNTL */ 1341 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1342 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1343 if (ret) 1344 return ret; 1345 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1346 fw_info.feature, fw_info.ver); 1347 1348 /* RLC SAVE RESTORE LIST GPM MEM */ 1349 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1350 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1351 if (ret) 1352 return ret; 1353 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1354 fw_info.feature, fw_info.ver); 1355 1356 /* RLC SAVE RESTORE LIST SRM MEM */ 1357 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1358 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1359 if (ret) 1360 return ret; 1361 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1362 fw_info.feature, fw_info.ver); 1363 1364 /* MEC */ 1365 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1366 query_fw.index = 0; 1367 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1368 if (ret) 1369 return ret; 1370 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1371 fw_info.feature, fw_info.ver); 1372 1373 /* MEC2 */ 1374 if (adev->gfx.mec2_fw) { 1375 query_fw.index = 1; 1376 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1377 if (ret) 1378 return ret; 1379 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1380 fw_info.feature, fw_info.ver); 1381 } 1382 1383 /* PSP SOS */ 1384 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1385 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1386 if (ret) 1387 return ret; 1388 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1389 fw_info.feature, fw_info.ver); 1390 1391 1392 /* PSP ASD */ 1393 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1394 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1395 if (ret) 1396 return ret; 1397 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1398 fw_info.feature, fw_info.ver); 1399 1400 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1401 for (i = 0; i < 4; i++) { 1402 query_fw.index = i; 1403 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1404 if (ret) 1405 continue; 1406 switch (query_fw.index) { 1407 case 0: 1408 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1409 "RAS", fw_info.feature, fw_info.ver); 1410 break; 1411 case 1: 1412 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1413 "XGMI", fw_info.feature, fw_info.ver); 1414 break; 1415 case 2: 1416 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1417 "HDCP", fw_info.feature, fw_info.ver); 1418 break; 1419 case 3: 1420 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1421 "DTM", fw_info.feature, fw_info.ver); 1422 break; 1423 default: 1424 return -EINVAL; 1425 } 1426 } 1427 1428 /* SMC */ 1429 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1431 if (ret) 1432 return ret; 1433 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n", 1434 fw_info.feature, fw_info.ver); 1435 1436 /* SDMA */ 1437 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1438 for (i = 0; i < adev->sdma.num_instances; i++) { 1439 query_fw.index = i; 1440 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1441 if (ret) 1442 return ret; 1443 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1444 i, fw_info.feature, fw_info.ver); 1445 } 1446 1447 /* VCN */ 1448 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1449 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1450 if (ret) 1451 return ret; 1452 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1453 fw_info.feature, fw_info.ver); 1454 1455 /* DMCU */ 1456 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1457 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1458 if (ret) 1459 return ret; 1460 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1461 fw_info.feature, fw_info.ver); 1462 1463 /* DMCUB */ 1464 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1465 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1466 if (ret) 1467 return ret; 1468 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1469 fw_info.feature, fw_info.ver); 1470 1471 1472 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1473 1474 return 0; 1475} 1476 1477static const struct drm_info_list amdgpu_firmware_info_list[] = { 1478 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL}, 1479}; 1480#endif 1481 1482int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1483{ 1484#if defined(CONFIG_DEBUG_FS) 1485 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list, 1486 ARRAY_SIZE(amdgpu_firmware_info_list)); 1487#else 1488 return 0; 1489#endif 1490} 1491