1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <linux/ktime.h> 29#include <linux/module.h> 30#include <linux/pagemap.h> 31#include <linux/pci.h> 32#include <linux/dma-buf.h> 33 34#include <drm/amdgpu_drm.h> 35#include <drm/drm_debugfs.h> 36 37#include "amdgpu.h" 38#include "amdgpu_display.h" 39#include "amdgpu_xgmi.h" 40 41void amdgpu_gem_object_free(struct drm_gem_object *gobj) 42{ 43 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 44 45 if (robj) { 46 amdgpu_mn_unregister(robj); 47 amdgpu_bo_unref(&robj); 48 } 49} 50 51int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 52 int alignment, u32 initial_domain, 53 u64 flags, enum ttm_bo_type type, 54 struct dma_resv *resv, 55 struct drm_gem_object **obj) 56{ 57 struct amdgpu_bo *bo; 58 struct amdgpu_bo_param bp; 59 int r; 60 61 memset(&bp, 0, sizeof(bp)); 62 *obj = NULL; 63 64 bp.size = size; 65 bp.byte_align = alignment; 66 bp.type = type; 67 bp.resv = resv; 68 bp.preferred_domain = initial_domain; 69 bp.flags = flags; 70 bp.domain = initial_domain; 71 r = amdgpu_bo_create(adev, &bp, &bo); 72 if (r) 73 return r; 74 75 *obj = &bo->tbo.base; 76 77 return 0; 78} 79 80void amdgpu_gem_force_release(struct amdgpu_device *adev) 81{ 82 struct drm_device *ddev = adev_to_drm(adev); 83 struct drm_file *file; 84 85 mutex_lock(&ddev->filelist_mutex); 86 87 list_for_each_entry(file, &ddev->filelist, lhead) { 88 struct drm_gem_object *gobj; 89 int handle; 90 91 WARN_ONCE(1, "Still active user space clients!\n"); 92 spin_lock(&file->table_lock); 93 idr_for_each_entry(&file->object_idr, gobj, handle) { 94 WARN_ONCE(1, "And also active allocations!\n"); 95 drm_gem_object_put(gobj); 96 } 97 idr_destroy(&file->object_idr); 98 spin_unlock(&file->table_lock); 99 } 100 101 mutex_unlock(&ddev->filelist_mutex); 102} 103 104/* 105 * Call from drm_gem_handle_create which appear in both new and open ioctl 106 * case. 107 */ 108int amdgpu_gem_object_open(struct drm_gem_object *obj, 109 struct drm_file *file_priv) 110{ 111 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); 112 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 113 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 114 struct amdgpu_vm *vm = &fpriv->vm; 115 struct amdgpu_bo_va *bo_va; 116 struct mm_struct *mm; 117 int r; 118 119 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); 120 if (mm && mm != current->mm) 121 return -EPERM; 122 123 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && 124 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv) 125 return -EPERM; 126 127 r = amdgpu_bo_reserve(abo, false); 128 if (r) 129 return r; 130 131 bo_va = amdgpu_vm_bo_find(vm, abo); 132 if (!bo_va) { 133 bo_va = amdgpu_vm_bo_add(adev, vm, abo); 134 } else { 135 ++bo_va->ref_count; 136 } 137 amdgpu_bo_unreserve(abo); 138 return 0; 139} 140 141void amdgpu_gem_object_close(struct drm_gem_object *obj, 142 struct drm_file *file_priv) 143{ 144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); 145 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 146 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 147 struct amdgpu_vm *vm = &fpriv->vm; 148 149 struct amdgpu_bo_list_entry vm_pd; 150 struct list_head list, duplicates; 151 struct dma_fence *fence = NULL; 152 struct ttm_validate_buffer tv; 153 struct ww_acquire_ctx ticket; 154 struct amdgpu_bo_va *bo_va; 155 long r; 156 157 INIT_LIST_HEAD(&list); 158 INIT_LIST_HEAD(&duplicates); 159 160 tv.bo = &bo->tbo; 161 tv.num_shared = 2; 162 list_add(&tv.head, &list); 163 164 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); 165 166 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); 167 if (r) { 168 dev_err(adev->dev, "leaking bo va because " 169 "we fail to reserve bo (%ld)\n", r); 170 return; 171 } 172 bo_va = amdgpu_vm_bo_find(vm, bo); 173 if (!bo_va || --bo_va->ref_count) 174 goto out_unlock; 175 176 amdgpu_vm_bo_rmv(adev, bo_va); 177 if (!amdgpu_vm_ready(vm)) 178 goto out_unlock; 179 180 fence = dma_resv_get_excl(bo->tbo.base.resv); 181 if (fence) { 182 amdgpu_bo_fence(bo, fence, true); 183 fence = NULL; 184 } 185 186 r = amdgpu_vm_clear_freed(adev, vm, &fence); 187 if (r || !fence) 188 goto out_unlock; 189 190 amdgpu_bo_fence(bo, fence, true); 191 dma_fence_put(fence); 192 193out_unlock: 194 if (unlikely(r < 0)) 195 dev_err(adev->dev, "failed to clear page " 196 "tables on GEM object close (%ld)\n", r); 197 ttm_eu_backoff_reservation(&ticket, &list); 198} 199 200/* 201 * GEM ioctls. 202 */ 203int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 204 struct drm_file *filp) 205{ 206 struct amdgpu_device *adev = drm_to_adev(dev); 207 struct amdgpu_fpriv *fpriv = filp->driver_priv; 208 struct amdgpu_vm *vm = &fpriv->vm; 209 union drm_amdgpu_gem_create *args = data; 210 uint64_t flags = args->in.domain_flags; 211 uint64_t size = args->in.bo_size; 212 struct dma_resv *resv = NULL; 213 struct drm_gem_object *gobj; 214 uint32_t handle, initial_domain; 215 int r; 216 217 /* reject invalid gem flags */ 218 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 219 AMDGPU_GEM_CREATE_NO_CPU_ACCESS | 220 AMDGPU_GEM_CREATE_CPU_GTT_USWC | 221 AMDGPU_GEM_CREATE_VRAM_CLEARED | 222 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | 223 AMDGPU_GEM_CREATE_EXPLICIT_SYNC | 224 AMDGPU_GEM_CREATE_ENCRYPTED)) 225 226 return -EINVAL; 227 228 /* reject invalid gem domains */ 229 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) 230 return -EINVAL; 231 232 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) { 233 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n"); 234 return -EINVAL; 235 } 236 237 /* create a gem object to contain this object in */ 238 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 239 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 240 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 241 /* if gds bo is created from user space, it must be 242 * passed to bo list 243 */ 244 DRM_ERROR("GDS bo cannot be per-vm-bo\n"); 245 return -EINVAL; 246 } 247 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 248 } 249 250 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 251 r = amdgpu_bo_reserve(vm->root.base.bo, false); 252 if (r) 253 return r; 254 255 resv = vm->root.base.bo->tbo.base.resv; 256 } 257 258retry: 259 initial_domain = (u32)(0xffffffff & args->in.domains); 260 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 261 initial_domain, 262 flags, ttm_bo_type_device, resv, &gobj); 263 if (r) { 264 if (r != -ERESTARTSYS) { 265 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { 266 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 267 goto retry; 268 } 269 270 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 271 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 272 goto retry; 273 } 274 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n", 275 size, initial_domain, args->in.alignment, r); 276 } 277 return r; 278 } 279 280 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 281 if (!r) { 282 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); 283 284 abo->parent = amdgpu_bo_ref(vm->root.base.bo); 285 } 286 amdgpu_bo_unreserve(vm->root.base.bo); 287 } 288 if (r) 289 return r; 290 291 r = drm_gem_handle_create(filp, gobj, &handle); 292 /* drop reference from allocate - handle holds it now */ 293 drm_gem_object_put(gobj); 294 if (r) 295 return r; 296 297 memset(args, 0, sizeof(*args)); 298 args->out.handle = handle; 299 return 0; 300} 301 302int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 303 struct drm_file *filp) 304{ 305 struct ttm_operation_ctx ctx = { true, false }; 306 struct amdgpu_device *adev = drm_to_adev(dev); 307 struct drm_amdgpu_gem_userptr *args = data; 308 struct drm_gem_object *gobj; 309 struct amdgpu_bo *bo; 310 uint32_t handle; 311 int r; 312 313 args->addr = untagged_addr(args->addr); 314 315 if (offset_in_page(args->addr | args->size)) 316 return -EINVAL; 317 318 /* reject unknown flag values */ 319 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 320 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 321 AMDGPU_GEM_USERPTR_REGISTER)) 322 return -EINVAL; 323 324 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && 325 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { 326 327 /* if we want to write to it we must install a MMU notifier */ 328 return -EACCES; 329 } 330 331 /* create a gem object to contain this object in */ 332 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 333 0, ttm_bo_type_device, NULL, &gobj); 334 if (r) 335 return r; 336 337 bo = gem_to_amdgpu_bo(gobj); 338 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 339 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 340 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags); 341 if (r) 342 goto release_object; 343 344 r = amdgpu_mn_register(bo, args->addr); 345 if (r) 346 goto release_object; 347 348 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 349 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); 350 if (r) 351 goto release_object; 352 353 r = amdgpu_bo_reserve(bo, true); 354 if (r) 355 goto user_pages_done; 356 357 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 358 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 359 amdgpu_bo_unreserve(bo); 360 if (r) 361 goto user_pages_done; 362 } 363 364 r = drm_gem_handle_create(filp, gobj, &handle); 365 if (r) 366 goto user_pages_done; 367 368 args->handle = handle; 369 370user_pages_done: 371 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) 372 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm); 373 374release_object: 375 drm_gem_object_put(gobj); 376 377 return r; 378} 379 380int amdgpu_mode_dumb_mmap(struct drm_file *filp, 381 struct drm_device *dev, 382 uint32_t handle, uint64_t *offset_p) 383{ 384 struct drm_gem_object *gobj; 385 struct amdgpu_bo *robj; 386 387 gobj = drm_gem_object_lookup(filp, handle); 388 if (gobj == NULL) { 389 return -ENOENT; 390 } 391 robj = gem_to_amdgpu_bo(gobj); 392 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || 393 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 394 drm_gem_object_put(gobj); 395 return -EPERM; 396 } 397 *offset_p = amdgpu_bo_mmap_offset(robj); 398 drm_gem_object_put(gobj); 399 return 0; 400} 401 402int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 403 struct drm_file *filp) 404{ 405 union drm_amdgpu_gem_mmap *args = data; 406 uint32_t handle = args->in.handle; 407 memset(args, 0, sizeof(*args)); 408 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 409} 410 411/** 412 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 413 * 414 * @timeout_ns: timeout in ns 415 * 416 * Calculate the timeout in jiffies from an absolute timeout in ns. 417 */ 418unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 419{ 420 unsigned long timeout_jiffies; 421 ktime_t timeout; 422 423 /* clamp timeout if it's to large */ 424 if (((int64_t)timeout_ns) < 0) 425 return MAX_SCHEDULE_TIMEOUT; 426 427 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 428 if (ktime_to_ns(timeout) < 0) 429 return 0; 430 431 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 432 /* clamp timeout to avoid unsigned-> signed overflow */ 433 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 434 return MAX_SCHEDULE_TIMEOUT - 1; 435 436 return timeout_jiffies; 437} 438 439int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 440 struct drm_file *filp) 441{ 442 union drm_amdgpu_gem_wait_idle *args = data; 443 struct drm_gem_object *gobj; 444 struct amdgpu_bo *robj; 445 uint32_t handle = args->in.handle; 446 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 447 int r = 0; 448 long ret; 449 450 gobj = drm_gem_object_lookup(filp, handle); 451 if (gobj == NULL) { 452 return -ENOENT; 453 } 454 robj = gem_to_amdgpu_bo(gobj); 455 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true, 456 timeout); 457 458 /* ret == 0 means not signaled, 459 * ret > 0 means signaled 460 * ret < 0 means interrupted before timeout 461 */ 462 if (ret >= 0) { 463 memset(args, 0, sizeof(*args)); 464 args->out.status = (ret == 0); 465 } else 466 r = ret; 467 468 drm_gem_object_put(gobj); 469 return r; 470} 471 472int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 473 struct drm_file *filp) 474{ 475 struct drm_amdgpu_gem_metadata *args = data; 476 struct drm_gem_object *gobj; 477 struct amdgpu_bo *robj; 478 int r = -1; 479 480 DRM_DEBUG("%d \n", args->handle); 481 gobj = drm_gem_object_lookup(filp, args->handle); 482 if (gobj == NULL) 483 return -ENOENT; 484 robj = gem_to_amdgpu_bo(gobj); 485 486 r = amdgpu_bo_reserve(robj, false); 487 if (unlikely(r != 0)) 488 goto out; 489 490 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 491 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 492 r = amdgpu_bo_get_metadata(robj, args->data.data, 493 sizeof(args->data.data), 494 &args->data.data_size_bytes, 495 &args->data.flags); 496 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 497 if (args->data.data_size_bytes > sizeof(args->data.data)) { 498 r = -EINVAL; 499 goto unreserve; 500 } 501 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 502 if (!r) 503 r = amdgpu_bo_set_metadata(robj, args->data.data, 504 args->data.data_size_bytes, 505 args->data.flags); 506 } 507 508unreserve: 509 amdgpu_bo_unreserve(robj); 510out: 511 drm_gem_object_put(gobj); 512 return r; 513} 514 515/** 516 * amdgpu_gem_va_update_vm -update the bo_va in its VM 517 * 518 * @adev: amdgpu_device pointer 519 * @vm: vm to update 520 * @bo_va: bo_va to update 521 * @operation: map, unmap or clear 522 * 523 * Update the bo_va directly after setting its address. Errors are not 524 * vital here, so they are not reported back to userspace. 525 */ 526static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 527 struct amdgpu_vm *vm, 528 struct amdgpu_bo_va *bo_va, 529 uint32_t operation) 530{ 531 int r; 532 533 if (!amdgpu_vm_ready(vm)) 534 return; 535 536 r = amdgpu_vm_clear_freed(adev, vm, NULL); 537 if (r) 538 goto error; 539 540 if (operation == AMDGPU_VA_OP_MAP || 541 operation == AMDGPU_VA_OP_REPLACE) { 542 r = amdgpu_vm_bo_update(adev, bo_va, false); 543 if (r) 544 goto error; 545 } 546 547 r = amdgpu_vm_update_pdes(adev, vm, false); 548 549error: 550 if (r && r != -ERESTARTSYS) 551 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 552} 553 554/** 555 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags 556 * 557 * @adev: amdgpu_device pointer 558 * @flags: GEM UAPI flags 559 * 560 * Returns the GEM UAPI flags mapped into hardware for the ASIC. 561 */ 562uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags) 563{ 564 uint64_t pte_flag = 0; 565 566 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 567 pte_flag |= AMDGPU_PTE_EXECUTABLE; 568 if (flags & AMDGPU_VM_PAGE_READABLE) 569 pte_flag |= AMDGPU_PTE_READABLE; 570 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 571 pte_flag |= AMDGPU_PTE_WRITEABLE; 572 if (flags & AMDGPU_VM_PAGE_PRT) 573 pte_flag |= AMDGPU_PTE_PRT; 574 575 if (adev->gmc.gmc_funcs->map_mtype) 576 pte_flag |= amdgpu_gmc_map_mtype(adev, 577 flags & AMDGPU_VM_MTYPE_MASK); 578 579 return pte_flag; 580} 581 582int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 583 struct drm_file *filp) 584{ 585 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | 586 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | 587 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; 588 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | 589 AMDGPU_VM_PAGE_PRT; 590 591 struct drm_amdgpu_gem_va *args = data; 592 struct drm_gem_object *gobj; 593 struct amdgpu_device *adev = drm_to_adev(dev); 594 struct amdgpu_fpriv *fpriv = filp->driver_priv; 595 struct amdgpu_bo *abo; 596 struct amdgpu_bo_va *bo_va; 597 struct amdgpu_bo_list_entry vm_pd; 598 struct ttm_validate_buffer tv; 599 struct ww_acquire_ctx ticket; 600 struct list_head list, duplicates; 601 uint64_t va_flags; 602 uint64_t vm_size; 603 int r = 0; 604 605 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 606 dev_dbg(&dev->pdev->dev, 607 "va_address 0x%LX is in reserved area 0x%LX\n", 608 args->va_address, AMDGPU_VA_RESERVED_SIZE); 609 return -EINVAL; 610 } 611 612 if (args->va_address >= AMDGPU_GMC_HOLE_START && 613 args->va_address < AMDGPU_GMC_HOLE_END) { 614 dev_dbg(&dev->pdev->dev, 615 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", 616 args->va_address, AMDGPU_GMC_HOLE_START, 617 AMDGPU_GMC_HOLE_END); 618 return -EINVAL; 619 } 620 621 args->va_address &= AMDGPU_GMC_HOLE_MASK; 622 623 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 624 vm_size -= AMDGPU_VA_RESERVED_SIZE; 625 if (args->va_address + args->map_size > vm_size) { 626 dev_dbg(&dev->pdev->dev, 627 "va_address 0x%llx is in top reserved area 0x%llx\n", 628 args->va_address + args->map_size, vm_size); 629 return -EINVAL; 630 } 631 632 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { 633 dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", 634 args->flags); 635 return -EINVAL; 636 } 637 638 switch (args->operation) { 639 case AMDGPU_VA_OP_MAP: 640 case AMDGPU_VA_OP_UNMAP: 641 case AMDGPU_VA_OP_CLEAR: 642 case AMDGPU_VA_OP_REPLACE: 643 break; 644 default: 645 dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", 646 args->operation); 647 return -EINVAL; 648 } 649 650 INIT_LIST_HEAD(&list); 651 INIT_LIST_HEAD(&duplicates); 652 if ((args->operation != AMDGPU_VA_OP_CLEAR) && 653 !(args->flags & AMDGPU_VM_PAGE_PRT)) { 654 gobj = drm_gem_object_lookup(filp, args->handle); 655 if (gobj == NULL) 656 return -ENOENT; 657 abo = gem_to_amdgpu_bo(gobj); 658 tv.bo = &abo->tbo; 659 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 660 tv.num_shared = 1; 661 else 662 tv.num_shared = 0; 663 list_add(&tv.head, &list); 664 } else { 665 gobj = NULL; 666 abo = NULL; 667 } 668 669 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); 670 671 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 672 if (r) 673 goto error_unref; 674 675 if (abo) { 676 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); 677 if (!bo_va) { 678 r = -ENOENT; 679 goto error_backoff; 680 } 681 } else if (args->operation != AMDGPU_VA_OP_CLEAR) { 682 bo_va = fpriv->prt_va; 683 } else { 684 bo_va = NULL; 685 } 686 687 switch (args->operation) { 688 case AMDGPU_VA_OP_MAP: 689 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 690 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 691 args->offset_in_bo, args->map_size, 692 va_flags); 693 break; 694 case AMDGPU_VA_OP_UNMAP: 695 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 696 break; 697 698 case AMDGPU_VA_OP_CLEAR: 699 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, 700 args->va_address, 701 args->map_size); 702 break; 703 case AMDGPU_VA_OP_REPLACE: 704 va_flags = amdgpu_gem_va_map_flags(adev, args->flags); 705 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, 706 args->offset_in_bo, args->map_size, 707 va_flags); 708 break; 709 default: 710 break; 711 } 712 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) 713 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, 714 args->operation); 715 716error_backoff: 717 ttm_eu_backoff_reservation(&ticket, &list); 718 719error_unref: 720 drm_gem_object_put(gobj); 721 return r; 722} 723 724int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 725 struct drm_file *filp) 726{ 727 struct amdgpu_device *adev = drm_to_adev(dev); 728 struct drm_amdgpu_gem_op *args = data; 729 struct drm_gem_object *gobj; 730 struct amdgpu_vm_bo_base *base; 731 struct amdgpu_bo *robj; 732 int r; 733 734 gobj = drm_gem_object_lookup(filp, args->handle); 735 if (gobj == NULL) { 736 return -ENOENT; 737 } 738 robj = gem_to_amdgpu_bo(gobj); 739 740 r = amdgpu_bo_reserve(robj, false); 741 if (unlikely(r)) 742 goto out; 743 744 switch (args->op) { 745 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 746 struct drm_amdgpu_gem_create_in info; 747 void __user *out = u64_to_user_ptr(args->value); 748 749 info.bo_size = robj->tbo.base.size; 750 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 751 info.domains = robj->preferred_domains; 752 info.domain_flags = robj->flags; 753 amdgpu_bo_unreserve(robj); 754 if (copy_to_user(out, &info, sizeof(info))) 755 r = -EFAULT; 756 break; 757 } 758 case AMDGPU_GEM_OP_SET_PLACEMENT: 759 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { 760 r = -EINVAL; 761 amdgpu_bo_unreserve(robj); 762 break; 763 } 764 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { 765 r = -EPERM; 766 amdgpu_bo_unreserve(robj); 767 break; 768 } 769 for (base = robj->vm_bo; base; base = base->next) 770 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev), 771 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) { 772 r = -EINVAL; 773 amdgpu_bo_unreserve(robj); 774 goto out; 775 } 776 777 778 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 779 AMDGPU_GEM_DOMAIN_GTT | 780 AMDGPU_GEM_DOMAIN_CPU); 781 robj->allowed_domains = robj->preferred_domains; 782 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 783 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 784 785 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) 786 amdgpu_vm_bo_invalidate(adev, robj, true); 787 788 amdgpu_bo_unreserve(robj); 789 break; 790 default: 791 amdgpu_bo_unreserve(robj); 792 r = -EINVAL; 793 } 794 795out: 796 drm_gem_object_put(gobj); 797 return r; 798} 799 800int amdgpu_mode_dumb_create(struct drm_file *file_priv, 801 struct drm_device *dev, 802 struct drm_mode_create_dumb *args) 803{ 804 struct amdgpu_device *adev = drm_to_adev(dev); 805 struct drm_gem_object *gobj; 806 uint32_t handle; 807 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 808 AMDGPU_GEM_CREATE_CPU_GTT_USWC; 809 u32 domain; 810 int r; 811 812 /* 813 * The buffer returned from this function should be cleared, but 814 * it can only be done if the ring is enabled or we'll fail to 815 * create the buffer. 816 */ 817 if (adev->mman.buffer_funcs_enabled) 818 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; 819 820 args->pitch = amdgpu_align_pitch(adev, args->width, 821 DIV_ROUND_UP(args->bpp, 8), 0); 822 args->size = (u64)args->pitch * args->height; 823 args->size = ALIGN(args->size, PAGE_SIZE); 824 domain = amdgpu_bo_get_preferred_pin_domain(adev, 825 amdgpu_display_supported_domains(adev, flags)); 826 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags, 827 ttm_bo_type_device, NULL, &gobj); 828 if (r) 829 return -ENOMEM; 830 831 r = drm_gem_handle_create(file_priv, gobj, &handle); 832 /* drop reference from allocate - handle holds it now */ 833 drm_gem_object_put(gobj); 834 if (r) { 835 return r; 836 } 837 args->handle = handle; 838 return 0; 839} 840 841#if defined(CONFIG_DEBUG_FS) 842 843#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ 844 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 845 seq_printf((m), " " #flag); \ 846 } 847 848static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) 849{ 850 struct drm_gem_object *gobj = ptr; 851 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); 852 struct seq_file *m = data; 853 854 struct dma_buf_attachment *attachment; 855 struct dma_buf *dma_buf; 856 unsigned domain; 857 const char *placement; 858 unsigned pin_count; 859 860 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 861 switch (domain) { 862 case AMDGPU_GEM_DOMAIN_VRAM: 863 placement = "VRAM"; 864 break; 865 case AMDGPU_GEM_DOMAIN_GTT: 866 placement = " GTT"; 867 break; 868 case AMDGPU_GEM_DOMAIN_CPU: 869 default: 870 placement = " CPU"; 871 break; 872 } 873 seq_printf(m, "\t0x%08x: %12ld byte %s", 874 id, amdgpu_bo_size(bo), placement); 875 876 pin_count = READ_ONCE(bo->pin_count); 877 if (pin_count) 878 seq_printf(m, " pin count %d", pin_count); 879 880 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 881 attachment = READ_ONCE(bo->tbo.base.import_attach); 882 883 if (attachment) 884 seq_printf(m, " imported from %p%s", dma_buf, 885 attachment->peer2peer ? " P2P" : ""); 886 else if (dma_buf) 887 seq_printf(m, " exported as %p", dma_buf); 888 889 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 890 amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); 891 amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); 892 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); 893 amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); 894 amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 895 amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); 896 amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); 897 898 seq_printf(m, "\n"); 899 900 return 0; 901} 902 903static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 904{ 905 struct drm_info_node *node = (struct drm_info_node *)m->private; 906 struct drm_device *dev = node->minor->dev; 907 struct drm_file *file; 908 int r; 909 910 r = mutex_lock_interruptible(&dev->filelist_mutex); 911 if (r) 912 return r; 913 914 list_for_each_entry(file, &dev->filelist, lhead) { 915 struct task_struct *task; 916 917 /* 918 * Although we have a valid reference on file->pid, that does 919 * not guarantee that the task_struct who called get_pid() is 920 * still alive (e.g. get_pid(current) => fork() => exit()). 921 * Therefore, we need to protect this ->comm access using RCU. 922 */ 923 rcu_read_lock(); 924 task = pid_task(file->pid, PIDTYPE_PID); 925 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), 926 task ? task->comm : "<unknown>"); 927 rcu_read_unlock(); 928 929 spin_lock(&file->table_lock); 930 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); 931 spin_unlock(&file->table_lock); 932 } 933 934 mutex_unlock(&dev->filelist_mutex); 935 return 0; 936} 937 938static const struct drm_info_list amdgpu_debugfs_gem_list[] = { 939 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 940}; 941#endif 942 943int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) 944{ 945#if defined(CONFIG_DEBUG_FS) 946 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 947 ARRAY_SIZE(amdgpu_debugfs_gem_list)); 948#endif 949 return 0; 950} 951