1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#include <linux/kthread.h> 27#include <linux/pci.h> 28#include <linux/uaccess.h> 29#include <linux/pm_runtime.h> 30#include <linux/poll.h> 31#include <drm/drm_debugfs.h> 32 33#include "amdgpu.h" 34#include "amdgpu_pm.h" 35#include "amdgpu_dm_debugfs.h" 36#include "amdgpu_ras.h" 37#include "amdgpu_rap.h" 38 39/** 40 * amdgpu_debugfs_add_files - Add simple debugfs entries 41 * 42 * @adev: Device to attach debugfs entries to 43 * @files: Array of function callbacks that respond to reads 44 * @nfiles: Number of callbacks to register 45 * 46 */ 47int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 48 const struct drm_info_list *files, 49 unsigned nfiles) 50{ 51 unsigned i; 52 53 for (i = 0; i < adev->debugfs_count; i++) { 54 if (adev->debugfs[i].files == files) { 55 /* Already registered */ 56 return 0; 57 } 58 } 59 60 i = adev->debugfs_count + 1; 61 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) { 62 DRM_ERROR("Reached maximum number of debugfs components.\n"); 63 DRM_ERROR("Report so we increase " 64 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n"); 65 return -EINVAL; 66 } 67 adev->debugfs[adev->debugfs_count].files = files; 68 adev->debugfs[adev->debugfs_count].num_files = nfiles; 69 adev->debugfs_count = i; 70#if defined(CONFIG_DEBUG_FS) 71 drm_debugfs_create_files(files, nfiles, 72 adev_to_drm(adev)->primary->debugfs_root, 73 adev_to_drm(adev)->primary); 74#endif 75 return 0; 76} 77 78int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev) 79{ 80#if defined(CONFIG_DEBUG_FS) 81 unsigned long timeout = 600 * HZ; 82 int ret; 83 84 wake_up_interruptible(&adev->autodump.gpu_hang); 85 86 ret = wait_for_completion_interruptible_timeout(&adev->autodump.dumping, timeout); 87 if (ret == 0) { 88 pr_err("autodump: timeout, move on to gpu recovery\n"); 89 return -ETIMEDOUT; 90 } 91#endif 92 return 0; 93} 94 95#if defined(CONFIG_DEBUG_FS) 96 97static int amdgpu_debugfs_autodump_open(struct inode *inode, struct file *file) 98{ 99 struct amdgpu_device *adev = inode->i_private; 100 int ret; 101 102 file->private_data = adev; 103 104 ret = down_read_killable(&adev->reset_sem); 105 if (ret) 106 return ret; 107 108 if (adev->autodump.dumping.done) { 109 reinit_completion(&adev->autodump.dumping); 110 ret = 0; 111 } else { 112 ret = -EBUSY; 113 } 114 115 up_read(&adev->reset_sem); 116 117 return ret; 118} 119 120static int amdgpu_debugfs_autodump_release(struct inode *inode, struct file *file) 121{ 122 struct amdgpu_device *adev = file->private_data; 123 124 complete_all(&adev->autodump.dumping); 125 return 0; 126} 127 128static unsigned int amdgpu_debugfs_autodump_poll(struct file *file, struct poll_table_struct *poll_table) 129{ 130 struct amdgpu_device *adev = file->private_data; 131 132 poll_wait(file, &adev->autodump.gpu_hang, poll_table); 133 134 if (amdgpu_in_reset(adev)) 135 return POLLIN | POLLRDNORM | POLLWRNORM; 136 137 return 0; 138} 139 140static const struct file_operations autodump_debug_fops = { 141 .owner = THIS_MODULE, 142 .open = amdgpu_debugfs_autodump_open, 143 .poll = amdgpu_debugfs_autodump_poll, 144 .release = amdgpu_debugfs_autodump_release, 145}; 146 147static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev) 148{ 149 init_completion(&adev->autodump.dumping); 150 complete_all(&adev->autodump.dumping); 151 init_waitqueue_head(&adev->autodump.gpu_hang); 152 153 debugfs_create_file("amdgpu_autodump", 0600, 154 adev_to_drm(adev)->primary->debugfs_root, 155 adev, &autodump_debug_fops); 156} 157 158/** 159 * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes 160 * 161 * @read: True if reading 162 * @f: open file handle 163 * @buf: User buffer to write/read to 164 * @size: Number of bytes to write/read 165 * @pos: Offset to seek to 166 * 167 * This debugfs entry has special meaning on the offset being sought. 168 * Various bits have different meanings: 169 * 170 * Bit 62: Indicates a GRBM bank switch is needed 171 * Bit 61: Indicates a SRBM bank switch is needed (implies bit 62 is 172 * zero) 173 * Bits 24..33: The SE or ME selector if needed 174 * Bits 34..43: The SH (or SA) or PIPE selector if needed 175 * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed 176 * 177 * Bit 23: Indicates that the PM power gating lock should be held 178 * This is necessary to read registers that might be 179 * unreliable during a power gating transistion. 180 * 181 * The lower bits are the BYTE offset of the register to read. This 182 * allows reading multiple registers in a single call and having 183 * the returned size reflect that. 184 */ 185static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, 186 char __user *buf, size_t size, loff_t *pos) 187{ 188 struct amdgpu_device *adev = file_inode(f)->i_private; 189 ssize_t result = 0; 190 int r; 191 bool pm_pg_lock, use_bank, use_ring; 192 unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid; 193 194 pm_pg_lock = use_bank = use_ring = false; 195 instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0; 196 197 if (size & 0x3 || *pos & 0x3 || 198 ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61)))) 199 return -EINVAL; 200 201 /* are we reading registers for which a PG lock is necessary? */ 202 pm_pg_lock = (*pos >> 23) & 1; 203 204 if (*pos & (1ULL << 62)) { 205 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; 206 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; 207 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; 208 209 if (se_bank == 0x3FF) 210 se_bank = 0xFFFFFFFF; 211 if (sh_bank == 0x3FF) 212 sh_bank = 0xFFFFFFFF; 213 if (instance_bank == 0x3FF) 214 instance_bank = 0xFFFFFFFF; 215 use_bank = true; 216 } else if (*pos & (1ULL << 61)) { 217 218 me = (*pos & GENMASK_ULL(33, 24)) >> 24; 219 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; 220 queue = (*pos & GENMASK_ULL(53, 44)) >> 44; 221 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; 222 223 use_ring = true; 224 } else { 225 use_bank = use_ring = false; 226 } 227 228 *pos &= (1UL << 22) - 1; 229 230 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 231 if (r < 0) { 232 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 233 return r; 234 } 235 236 r = amdgpu_virt_enable_access_debugfs(adev); 237 if (r < 0) { 238 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 239 return r; 240 } 241 242 if (use_bank) { 243 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || 244 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { 245 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 246 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 247 amdgpu_virt_disable_access_debugfs(adev); 248 return -EINVAL; 249 } 250 mutex_lock(&adev->grbm_idx_mutex); 251 amdgpu_gfx_select_se_sh(adev, se_bank, 252 sh_bank, instance_bank); 253 } else if (use_ring) { 254 mutex_lock(&adev->srbm_mutex); 255 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid); 256 } 257 258 if (pm_pg_lock) 259 mutex_lock(&adev->pm.mutex); 260 261 while (size) { 262 uint32_t value; 263 264 if (read) { 265 value = RREG32(*pos >> 2); 266 r = put_user(value, (uint32_t *)buf); 267 } else { 268 r = get_user(value, (uint32_t *)buf); 269 if (!r) 270 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value); 271 } 272 if (r) { 273 result = r; 274 goto end; 275 } 276 277 result += 4; 278 buf += 4; 279 *pos += 4; 280 size -= 4; 281 } 282 283end: 284 if (use_bank) { 285 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 286 mutex_unlock(&adev->grbm_idx_mutex); 287 } else if (use_ring) { 288 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0); 289 mutex_unlock(&adev->srbm_mutex); 290 } 291 292 if (pm_pg_lock) 293 mutex_unlock(&adev->pm.mutex); 294 295 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 296 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 297 298 amdgpu_virt_disable_access_debugfs(adev); 299 return result; 300} 301 302/** 303 * amdgpu_debugfs_regs_read - Callback for reading MMIO registers 304 */ 305static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, 306 size_t size, loff_t *pos) 307{ 308 return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos); 309} 310 311/** 312 * amdgpu_debugfs_regs_write - Callback for writing MMIO registers 313 */ 314static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, 315 size_t size, loff_t *pos) 316{ 317 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos); 318} 319 320 321/** 322 * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register 323 * 324 * @f: open file handle 325 * @buf: User buffer to store read data in 326 * @size: Number of bytes to read 327 * @pos: Offset to seek to 328 * 329 * The lower bits are the BYTE offset of the register to read. This 330 * allows reading multiple registers in a single call and having 331 * the returned size reflect that. 332 */ 333static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf, 334 size_t size, loff_t *pos) 335{ 336 struct amdgpu_device *adev = file_inode(f)->i_private; 337 ssize_t result = 0; 338 int r; 339 340 if (size & 0x3 || *pos & 0x3) 341 return -EINVAL; 342 343 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 344 if (r < 0) { 345 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 346 return r; 347 } 348 349 r = amdgpu_virt_enable_access_debugfs(adev); 350 if (r < 0) { 351 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 352 return r; 353 } 354 355 while (size) { 356 uint32_t value; 357 358 value = RREG32_PCIE(*pos); 359 r = put_user(value, (uint32_t *)buf); 360 if (r) { 361 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 362 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 363 amdgpu_virt_disable_access_debugfs(adev); 364 return r; 365 } 366 367 result += 4; 368 buf += 4; 369 *pos += 4; 370 size -= 4; 371 } 372 373 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 374 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 375 376 amdgpu_virt_disable_access_debugfs(adev); 377 return result; 378} 379 380/** 381 * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register 382 * 383 * @f: open file handle 384 * @buf: User buffer to write data from 385 * @size: Number of bytes to write 386 * @pos: Offset to seek to 387 * 388 * The lower bits are the BYTE offset of the register to write. This 389 * allows writing multiple registers in a single call and having 390 * the returned size reflect that. 391 */ 392static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf, 393 size_t size, loff_t *pos) 394{ 395 struct amdgpu_device *adev = file_inode(f)->i_private; 396 ssize_t result = 0; 397 int r; 398 399 if (size & 0x3 || *pos & 0x3) 400 return -EINVAL; 401 402 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 403 if (r < 0) { 404 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 405 return r; 406 } 407 408 r = amdgpu_virt_enable_access_debugfs(adev); 409 if (r < 0) { 410 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 411 return r; 412 } 413 414 while (size) { 415 uint32_t value; 416 417 r = get_user(value, (uint32_t *)buf); 418 if (r) { 419 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 420 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 421 amdgpu_virt_disable_access_debugfs(adev); 422 return r; 423 } 424 425 WREG32_PCIE(*pos, value); 426 427 result += 4; 428 buf += 4; 429 *pos += 4; 430 size -= 4; 431 } 432 433 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 434 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 435 436 amdgpu_virt_disable_access_debugfs(adev); 437 return result; 438} 439 440/** 441 * amdgpu_debugfs_regs_didt_read - Read from a DIDT register 442 * 443 * @f: open file handle 444 * @buf: User buffer to store read data in 445 * @size: Number of bytes to read 446 * @pos: Offset to seek to 447 * 448 * The lower bits are the BYTE offset of the register to read. This 449 * allows reading multiple registers in a single call and having 450 * the returned size reflect that. 451 */ 452static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, 453 size_t size, loff_t *pos) 454{ 455 struct amdgpu_device *adev = file_inode(f)->i_private; 456 ssize_t result = 0; 457 int r; 458 459 if (size & 0x3 || *pos & 0x3) 460 return -EINVAL; 461 462 if (!adev->didt_rreg) 463 return -EOPNOTSUPP; 464 465 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 466 if (r < 0) { 467 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 468 return r; 469 } 470 471 r = amdgpu_virt_enable_access_debugfs(adev); 472 if (r < 0) { 473 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 474 return r; 475 } 476 477 while (size) { 478 uint32_t value; 479 480 value = RREG32_DIDT(*pos >> 2); 481 r = put_user(value, (uint32_t *)buf); 482 if (r) { 483 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 484 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 485 amdgpu_virt_disable_access_debugfs(adev); 486 return r; 487 } 488 489 result += 4; 490 buf += 4; 491 *pos += 4; 492 size -= 4; 493 } 494 495 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 496 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 497 498 amdgpu_virt_disable_access_debugfs(adev); 499 return result; 500} 501 502/** 503 * amdgpu_debugfs_regs_didt_write - Write to a DIDT register 504 * 505 * @f: open file handle 506 * @buf: User buffer to write data from 507 * @size: Number of bytes to write 508 * @pos: Offset to seek to 509 * 510 * The lower bits are the BYTE offset of the register to write. This 511 * allows writing multiple registers in a single call and having 512 * the returned size reflect that. 513 */ 514static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf, 515 size_t size, loff_t *pos) 516{ 517 struct amdgpu_device *adev = file_inode(f)->i_private; 518 ssize_t result = 0; 519 int r; 520 521 if (size & 0x3 || *pos & 0x3) 522 return -EINVAL; 523 524 if (!adev->didt_wreg) 525 return -EOPNOTSUPP; 526 527 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 528 if (r < 0) { 529 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 530 return r; 531 } 532 533 r = amdgpu_virt_enable_access_debugfs(adev); 534 if (r < 0) { 535 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 536 return r; 537 } 538 539 while (size) { 540 uint32_t value; 541 542 r = get_user(value, (uint32_t *)buf); 543 if (r) { 544 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 545 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 546 amdgpu_virt_disable_access_debugfs(adev); 547 return r; 548 } 549 550 WREG32_DIDT(*pos >> 2, value); 551 552 result += 4; 553 buf += 4; 554 *pos += 4; 555 size -= 4; 556 } 557 558 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 559 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 560 561 amdgpu_virt_disable_access_debugfs(adev); 562 return result; 563} 564 565/** 566 * amdgpu_debugfs_regs_smc_read - Read from a SMC register 567 * 568 * @f: open file handle 569 * @buf: User buffer to store read data in 570 * @size: Number of bytes to read 571 * @pos: Offset to seek to 572 * 573 * The lower bits are the BYTE offset of the register to read. This 574 * allows reading multiple registers in a single call and having 575 * the returned size reflect that. 576 */ 577static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, 578 size_t size, loff_t *pos) 579{ 580 struct amdgpu_device *adev = file_inode(f)->i_private; 581 ssize_t result = 0; 582 int r; 583 584 if (!adev->smc_rreg) 585 return -EOPNOTSUPP; 586 587 if (size & 0x3 || *pos & 0x3) 588 return -EINVAL; 589 590 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 591 if (r < 0) { 592 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 593 return r; 594 } 595 596 r = amdgpu_virt_enable_access_debugfs(adev); 597 if (r < 0) { 598 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 599 return r; 600 } 601 602 while (size) { 603 uint32_t value; 604 605 value = RREG32_SMC(*pos); 606 r = put_user(value, (uint32_t *)buf); 607 if (r) { 608 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 609 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 610 amdgpu_virt_disable_access_debugfs(adev); 611 return r; 612 } 613 614 result += 4; 615 buf += 4; 616 *pos += 4; 617 size -= 4; 618 } 619 620 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 621 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 622 623 amdgpu_virt_disable_access_debugfs(adev); 624 return result; 625} 626 627/** 628 * amdgpu_debugfs_regs_smc_write - Write to a SMC register 629 * 630 * @f: open file handle 631 * @buf: User buffer to write data from 632 * @size: Number of bytes to write 633 * @pos: Offset to seek to 634 * 635 * The lower bits are the BYTE offset of the register to write. This 636 * allows writing multiple registers in a single call and having 637 * the returned size reflect that. 638 */ 639static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf, 640 size_t size, loff_t *pos) 641{ 642 struct amdgpu_device *adev = file_inode(f)->i_private; 643 ssize_t result = 0; 644 int r; 645 646 if (!adev->smc_wreg) 647 return -EOPNOTSUPP; 648 649 if (size & 0x3 || *pos & 0x3) 650 return -EINVAL; 651 652 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 653 if (r < 0) { 654 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 655 return r; 656 } 657 658 r = amdgpu_virt_enable_access_debugfs(adev); 659 if (r < 0) { 660 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 661 return r; 662 } 663 664 while (size) { 665 uint32_t value; 666 667 r = get_user(value, (uint32_t *)buf); 668 if (r) { 669 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 670 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 671 amdgpu_virt_disable_access_debugfs(adev); 672 return r; 673 } 674 675 WREG32_SMC(*pos, value); 676 677 result += 4; 678 buf += 4; 679 *pos += 4; 680 size -= 4; 681 } 682 683 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 684 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 685 686 amdgpu_virt_disable_access_debugfs(adev); 687 return result; 688} 689 690/** 691 * amdgpu_debugfs_gca_config_read - Read from gfx config data 692 * 693 * @f: open file handle 694 * @buf: User buffer to store read data in 695 * @size: Number of bytes to read 696 * @pos: Offset to seek to 697 * 698 * This file is used to access configuration data in a somewhat 699 * stable fashion. The format is a series of DWORDs with the first 700 * indicating which revision it is. New content is appended to the 701 * end so that older software can still read the data. 702 */ 703 704static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, 705 size_t size, loff_t *pos) 706{ 707 struct amdgpu_device *adev = file_inode(f)->i_private; 708 ssize_t result = 0; 709 int r; 710 uint32_t *config, no_regs = 0; 711 712 if (size & 0x3 || *pos & 0x3) 713 return -EINVAL; 714 715 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL); 716 if (!config) 717 return -ENOMEM; 718 719 /* version, increment each time something is added */ 720 config[no_regs++] = 3; 721 config[no_regs++] = adev->gfx.config.max_shader_engines; 722 config[no_regs++] = adev->gfx.config.max_tile_pipes; 723 config[no_regs++] = adev->gfx.config.max_cu_per_sh; 724 config[no_regs++] = adev->gfx.config.max_sh_per_se; 725 config[no_regs++] = adev->gfx.config.max_backends_per_se; 726 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; 727 config[no_regs++] = adev->gfx.config.max_gprs; 728 config[no_regs++] = adev->gfx.config.max_gs_threads; 729 config[no_regs++] = adev->gfx.config.max_hw_contexts; 730 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend; 731 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend; 732 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size; 733 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size; 734 config[no_regs++] = adev->gfx.config.num_tile_pipes; 735 config[no_regs++] = adev->gfx.config.backend_enable_mask; 736 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes; 737 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb; 738 config[no_regs++] = adev->gfx.config.shader_engine_tile_size; 739 config[no_regs++] = adev->gfx.config.num_gpus; 740 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size; 741 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg; 742 config[no_regs++] = adev->gfx.config.gb_addr_config; 743 config[no_regs++] = adev->gfx.config.num_rbs; 744 745 /* rev==1 */ 746 config[no_regs++] = adev->rev_id; 747 config[no_regs++] = adev->pg_flags; 748 config[no_regs++] = adev->cg_flags; 749 750 /* rev==2 */ 751 config[no_regs++] = adev->family; 752 config[no_regs++] = adev->external_rev_id; 753 754 /* rev==3 */ 755 config[no_regs++] = adev->pdev->device; 756 config[no_regs++] = adev->pdev->revision; 757 config[no_regs++] = adev->pdev->subsystem_device; 758 config[no_regs++] = adev->pdev->subsystem_vendor; 759 760 while (size && (*pos < no_regs * 4)) { 761 uint32_t value; 762 763 value = config[*pos >> 2]; 764 r = put_user(value, (uint32_t *)buf); 765 if (r) { 766 kfree(config); 767 return r; 768 } 769 770 result += 4; 771 buf += 4; 772 *pos += 4; 773 size -= 4; 774 } 775 776 kfree(config); 777 return result; 778} 779 780/** 781 * amdgpu_debugfs_sensor_read - Read from the powerplay sensors 782 * 783 * @f: open file handle 784 * @buf: User buffer to store read data in 785 * @size: Number of bytes to read 786 * @pos: Offset to seek to 787 * 788 * The offset is treated as the BYTE address of one of the sensors 789 * enumerated in amd/include/kgd_pp_interface.h under the 790 * 'amd_pp_sensors' enumeration. For instance to read the UVD VCLK 791 * you would use the offset 3 * 4 = 12. 792 */ 793static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf, 794 size_t size, loff_t *pos) 795{ 796 struct amdgpu_device *adev = file_inode(f)->i_private; 797 int idx, x, outsize, r, valuesize; 798 uint32_t values[16]; 799 800 if (size & 3 || *pos & 0x3) 801 return -EINVAL; 802 803 if (!adev->pm.dpm_enabled) 804 return -EINVAL; 805 806 /* convert offset to sensor number */ 807 idx = *pos >> 2; 808 809 valuesize = sizeof(values); 810 811 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 812 if (r < 0) { 813 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 814 return r; 815 } 816 817 r = amdgpu_virt_enable_access_debugfs(adev); 818 if (r < 0) { 819 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 820 return r; 821 } 822 823 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize); 824 825 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 826 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 827 828 if (r) { 829 amdgpu_virt_disable_access_debugfs(adev); 830 return r; 831 } 832 833 if (size > valuesize) { 834 amdgpu_virt_disable_access_debugfs(adev); 835 return -EINVAL; 836 } 837 838 outsize = 0; 839 x = 0; 840 if (!r) { 841 while (size) { 842 r = put_user(values[x++], (int32_t *)buf); 843 buf += 4; 844 size -= 4; 845 outsize += 4; 846 } 847 } 848 849 amdgpu_virt_disable_access_debugfs(adev); 850 return !r ? outsize : r; 851} 852 853/** amdgpu_debugfs_wave_read - Read WAVE STATUS data 854 * 855 * @f: open file handle 856 * @buf: User buffer to store read data in 857 * @size: Number of bytes to read 858 * @pos: Offset to seek to 859 * 860 * The offset being sought changes which wave that the status data 861 * will be returned for. The bits are used as follows: 862 * 863 * Bits 0..6: Byte offset into data 864 * Bits 7..14: SE selector 865 * Bits 15..22: SH/SA selector 866 * Bits 23..30: CU/{WGP+SIMD} selector 867 * Bits 31..36: WAVE ID selector 868 * Bits 37..44: SIMD ID selector 869 * 870 * The returned data begins with one DWORD of version information 871 * Followed by WAVE STATUS registers relevant to the GFX IP version 872 * being used. See gfx_v8_0_read_wave_data() for an example output. 873 */ 874static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 875 size_t size, loff_t *pos) 876{ 877 struct amdgpu_device *adev = f->f_inode->i_private; 878 int r, x; 879 ssize_t result=0; 880 uint32_t offset, se, sh, cu, wave, simd, data[32]; 881 882 if (size & 3 || *pos & 3) 883 return -EINVAL; 884 885 /* decode offset */ 886 offset = (*pos & GENMASK_ULL(6, 0)); 887 se = (*pos & GENMASK_ULL(14, 7)) >> 7; 888 sh = (*pos & GENMASK_ULL(22, 15)) >> 15; 889 cu = (*pos & GENMASK_ULL(30, 23)) >> 23; 890 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; 891 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; 892 893 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 894 if (r < 0) { 895 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 896 return r; 897 } 898 899 r = amdgpu_virt_enable_access_debugfs(adev); 900 if (r < 0) { 901 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 902 return r; 903 } 904 905 /* switch to the specific se/sh/cu */ 906 mutex_lock(&adev->grbm_idx_mutex); 907 amdgpu_gfx_select_se_sh(adev, se, sh, cu); 908 909 x = 0; 910 if (adev->gfx.funcs->read_wave_data) 911 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); 912 913 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 914 mutex_unlock(&adev->grbm_idx_mutex); 915 916 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 917 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 918 919 if (!x) { 920 amdgpu_virt_disable_access_debugfs(adev); 921 return -EINVAL; 922 } 923 924 while (size && (offset < x * 4)) { 925 uint32_t value; 926 927 value = data[offset >> 2]; 928 r = put_user(value, (uint32_t *)buf); 929 if (r) { 930 amdgpu_virt_disable_access_debugfs(adev); 931 return r; 932 } 933 934 result += 4; 935 buf += 4; 936 offset += 4; 937 size -= 4; 938 } 939 940 amdgpu_virt_disable_access_debugfs(adev); 941 return result; 942} 943 944/** amdgpu_debugfs_gpr_read - Read wave gprs 945 * 946 * @f: open file handle 947 * @buf: User buffer to store read data in 948 * @size: Number of bytes to read 949 * @pos: Offset to seek to 950 * 951 * The offset being sought changes which wave that the status data 952 * will be returned for. The bits are used as follows: 953 * 954 * Bits 0..11: Byte offset into data 955 * Bits 12..19: SE selector 956 * Bits 20..27: SH/SA selector 957 * Bits 28..35: CU/{WGP+SIMD} selector 958 * Bits 36..43: WAVE ID selector 959 * Bits 37..44: SIMD ID selector 960 * Bits 52..59: Thread selector 961 * Bits 60..61: Bank selector (VGPR=0,SGPR=1) 962 * 963 * The return data comes from the SGPR or VGPR register bank for 964 * the selected operational unit. 965 */ 966static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 967 size_t size, loff_t *pos) 968{ 969 struct amdgpu_device *adev = f->f_inode->i_private; 970 int r; 971 ssize_t result = 0; 972 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; 973 974 if (size > 4096 || size & 3 || *pos & 3) 975 return -EINVAL; 976 977 /* decode offset */ 978 offset = (*pos & GENMASK_ULL(11, 0)) >> 2; 979 se = (*pos & GENMASK_ULL(19, 12)) >> 12; 980 sh = (*pos & GENMASK_ULL(27, 20)) >> 20; 981 cu = (*pos & GENMASK_ULL(35, 28)) >> 28; 982 wave = (*pos & GENMASK_ULL(43, 36)) >> 36; 983 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; 984 thread = (*pos & GENMASK_ULL(59, 52)) >> 52; 985 bank = (*pos & GENMASK_ULL(61, 60)) >> 60; 986 987 data = kcalloc(1024, sizeof(*data), GFP_KERNEL); 988 if (!data) 989 return -ENOMEM; 990 991 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 992 if (r < 0) 993 goto err; 994 995 r = amdgpu_virt_enable_access_debugfs(adev); 996 if (r < 0) 997 goto err; 998 999 /* switch to the specific se/sh/cu */ 1000 mutex_lock(&adev->grbm_idx_mutex); 1001 amdgpu_gfx_select_se_sh(adev, se, sh, cu); 1002 1003 if (bank == 0) { 1004 if (adev->gfx.funcs->read_wave_vgprs) 1005 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); 1006 } else { 1007 if (adev->gfx.funcs->read_wave_sgprs) 1008 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); 1009 } 1010 1011 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 1012 mutex_unlock(&adev->grbm_idx_mutex); 1013 1014 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1015 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1016 1017 while (size) { 1018 uint32_t value; 1019 1020 value = data[result >> 2]; 1021 r = put_user(value, (uint32_t *)buf); 1022 if (r) { 1023 amdgpu_virt_disable_access_debugfs(adev); 1024 goto err; 1025 } 1026 1027 result += 4; 1028 buf += 4; 1029 size -= 4; 1030 } 1031 1032 kfree(data); 1033 amdgpu_virt_disable_access_debugfs(adev); 1034 return result; 1035 1036err: 1037 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1038 kfree(data); 1039 return r; 1040} 1041 1042/** 1043 * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF 1044 * 1045 * @f: open file handle 1046 * @buf: User buffer to write data from 1047 * @size: Number of bytes to write 1048 * @pos: Offset to seek to 1049 * 1050 * Write a 32-bit zero to disable or a 32-bit non-zero to enable 1051 */ 1052static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf, 1053 size_t size, loff_t *pos) 1054{ 1055 struct amdgpu_device *adev = file_inode(f)->i_private; 1056 ssize_t result = 0; 1057 int r; 1058 1059 if (size & 0x3 || *pos & 0x3) 1060 return -EINVAL; 1061 1062 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1063 if (r < 0) { 1064 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1065 return r; 1066 } 1067 1068 while (size) { 1069 uint32_t value; 1070 1071 r = get_user(value, (uint32_t *)buf); 1072 if (r) { 1073 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1074 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1075 return r; 1076 } 1077 1078 amdgpu_gfx_off_ctrl(adev, value ? true : false); 1079 1080 result += 4; 1081 buf += 4; 1082 *pos += 4; 1083 size -= 4; 1084 } 1085 1086 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1087 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1088 1089 return result; 1090} 1091 1092 1093/** 1094 * amdgpu_debugfs_regs_gfxoff_status - read gfxoff status 1095 * 1096 * @f: open file handle 1097 * @buf: User buffer to store read data in 1098 * @size: Number of bytes to read 1099 * @pos: Offset to seek to 1100 */ 1101static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf, 1102 size_t size, loff_t *pos) 1103{ 1104 struct amdgpu_device *adev = file_inode(f)->i_private; 1105 ssize_t result = 0; 1106 int r; 1107 1108 if (size & 0x3 || *pos & 0x3) 1109 return -EINVAL; 1110 1111 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1112 if (r < 0) 1113 return r; 1114 1115 while (size) { 1116 uint32_t value; 1117 1118 r = amdgpu_get_gfx_off_status(adev, &value); 1119 if (r) { 1120 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1121 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1122 return r; 1123 } 1124 1125 r = put_user(value, (uint32_t *)buf); 1126 if (r) { 1127 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1128 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1129 return r; 1130 } 1131 1132 result += 4; 1133 buf += 4; 1134 *pos += 4; 1135 size -= 4; 1136 } 1137 1138 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1139 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1140 1141 return result; 1142} 1143 1144static const struct file_operations amdgpu_debugfs_regs_fops = { 1145 .owner = THIS_MODULE, 1146 .read = amdgpu_debugfs_regs_read, 1147 .write = amdgpu_debugfs_regs_write, 1148 .llseek = default_llseek 1149}; 1150static const struct file_operations amdgpu_debugfs_regs_didt_fops = { 1151 .owner = THIS_MODULE, 1152 .read = amdgpu_debugfs_regs_didt_read, 1153 .write = amdgpu_debugfs_regs_didt_write, 1154 .llseek = default_llseek 1155}; 1156static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { 1157 .owner = THIS_MODULE, 1158 .read = amdgpu_debugfs_regs_pcie_read, 1159 .write = amdgpu_debugfs_regs_pcie_write, 1160 .llseek = default_llseek 1161}; 1162static const struct file_operations amdgpu_debugfs_regs_smc_fops = { 1163 .owner = THIS_MODULE, 1164 .read = amdgpu_debugfs_regs_smc_read, 1165 .write = amdgpu_debugfs_regs_smc_write, 1166 .llseek = default_llseek 1167}; 1168 1169static const struct file_operations amdgpu_debugfs_gca_config_fops = { 1170 .owner = THIS_MODULE, 1171 .read = amdgpu_debugfs_gca_config_read, 1172 .llseek = default_llseek 1173}; 1174 1175static const struct file_operations amdgpu_debugfs_sensors_fops = { 1176 .owner = THIS_MODULE, 1177 .read = amdgpu_debugfs_sensor_read, 1178 .llseek = default_llseek 1179}; 1180 1181static const struct file_operations amdgpu_debugfs_wave_fops = { 1182 .owner = THIS_MODULE, 1183 .read = amdgpu_debugfs_wave_read, 1184 .llseek = default_llseek 1185}; 1186static const struct file_operations amdgpu_debugfs_gpr_fops = { 1187 .owner = THIS_MODULE, 1188 .read = amdgpu_debugfs_gpr_read, 1189 .llseek = default_llseek 1190}; 1191 1192static const struct file_operations amdgpu_debugfs_gfxoff_fops = { 1193 .owner = THIS_MODULE, 1194 .read = amdgpu_debugfs_gfxoff_read, 1195 .write = amdgpu_debugfs_gfxoff_write, 1196 .llseek = default_llseek 1197}; 1198 1199static const struct file_operations *debugfs_regs[] = { 1200 &amdgpu_debugfs_regs_fops, 1201 &amdgpu_debugfs_regs_didt_fops, 1202 &amdgpu_debugfs_regs_pcie_fops, 1203 &amdgpu_debugfs_regs_smc_fops, 1204 &amdgpu_debugfs_gca_config_fops, 1205 &amdgpu_debugfs_sensors_fops, 1206 &amdgpu_debugfs_wave_fops, 1207 &amdgpu_debugfs_gpr_fops, 1208 &amdgpu_debugfs_gfxoff_fops, 1209}; 1210 1211static const char *debugfs_regs_names[] = { 1212 "amdgpu_regs", 1213 "amdgpu_regs_didt", 1214 "amdgpu_regs_pcie", 1215 "amdgpu_regs_smc", 1216 "amdgpu_gca_config", 1217 "amdgpu_sensors", 1218 "amdgpu_wave", 1219 "amdgpu_gpr", 1220 "amdgpu_gfxoff", 1221}; 1222 1223/** 1224 * amdgpu_debugfs_regs_init - Initialize debugfs entries that provide 1225 * register access. 1226 * 1227 * @adev: The device to attach the debugfs entries to 1228 */ 1229int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 1230{ 1231 struct drm_minor *minor = adev_to_drm(adev)->primary; 1232 struct dentry *ent, *root = minor->debugfs_root; 1233 unsigned int i; 1234 1235 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 1236 ent = debugfs_create_file(debugfs_regs_names[i], 1237 S_IFREG | S_IRUGO, root, 1238 adev, debugfs_regs[i]); 1239 if (!i && !IS_ERR_OR_NULL(ent)) 1240 i_size_write(ent->d_inode, adev->rmmio_size); 1241 adev->debugfs_regs[i] = ent; 1242 } 1243 1244 return 0; 1245} 1246 1247static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data) 1248{ 1249 struct drm_info_node *node = (struct drm_info_node *) m->private; 1250 struct drm_device *dev = node->minor->dev; 1251 struct amdgpu_device *adev = drm_to_adev(dev); 1252 int r = 0, i; 1253 1254 r = pm_runtime_get_sync(dev->dev); 1255 if (r < 0) { 1256 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1257 return r; 1258 } 1259 1260 /* Avoid accidently unparking the sched thread during GPU reset */ 1261 r = down_read_killable(&adev->reset_sem); 1262 if (r) 1263 return r; 1264 1265 /* hold on the scheduler */ 1266 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1267 struct amdgpu_ring *ring = adev->rings[i]; 1268 1269 if (!ring || !ring->sched.thread) 1270 continue; 1271 kthread_park(ring->sched.thread); 1272 } 1273 1274 seq_printf(m, "run ib test:\n"); 1275 r = amdgpu_ib_ring_tests(adev); 1276 if (r) 1277 seq_printf(m, "ib ring tests failed (%d).\n", r); 1278 else 1279 seq_printf(m, "ib ring tests passed.\n"); 1280 1281 /* go on the scheduler */ 1282 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1283 struct amdgpu_ring *ring = adev->rings[i]; 1284 1285 if (!ring || !ring->sched.thread) 1286 continue; 1287 kthread_unpark(ring->sched.thread); 1288 } 1289 1290 up_read(&adev->reset_sem); 1291 1292 pm_runtime_mark_last_busy(dev->dev); 1293 pm_runtime_put_autosuspend(dev->dev); 1294 1295 return 0; 1296} 1297 1298static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data) 1299{ 1300 struct drm_info_node *node = (struct drm_info_node *) m->private; 1301 struct drm_device *dev = node->minor->dev; 1302 struct amdgpu_device *adev = drm_to_adev(dev); 1303 1304 seq_write(m, adev->bios, adev->bios_size); 1305 return 0; 1306} 1307 1308static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data) 1309{ 1310 struct drm_info_node *node = (struct drm_info_node *)m->private; 1311 struct drm_device *dev = node->minor->dev; 1312 struct amdgpu_device *adev = drm_to_adev(dev); 1313 int r; 1314 1315 r = pm_runtime_get_sync(dev->dev); 1316 if (r < 0) { 1317 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1318 return r; 1319 } 1320 1321 seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev)); 1322 1323 pm_runtime_mark_last_busy(dev->dev); 1324 pm_runtime_put_autosuspend(dev->dev); 1325 1326 return 0; 1327} 1328 1329static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data) 1330{ 1331 struct drm_info_node *node = (struct drm_info_node *)m->private; 1332 struct drm_device *dev = node->minor->dev; 1333 struct amdgpu_device *adev = drm_to_adev(dev); 1334 int r; 1335 1336 r = pm_runtime_get_sync(dev->dev); 1337 if (r < 0) { 1338 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1339 return r; 1340 } 1341 1342 seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT)); 1343 1344 pm_runtime_mark_last_busy(dev->dev); 1345 pm_runtime_put_autosuspend(dev->dev); 1346 1347 return 0; 1348} 1349 1350static const struct drm_info_list amdgpu_debugfs_list[] = { 1351 {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump}, 1352 {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}, 1353 {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram}, 1354 {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt}, 1355}; 1356 1357static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, 1358 struct dma_fence **fences) 1359{ 1360 struct amdgpu_fence_driver *drv = &ring->fence_drv; 1361 uint32_t sync_seq, last_seq; 1362 1363 last_seq = atomic_read(&ring->fence_drv.last_seq); 1364 sync_seq = ring->fence_drv.sync_seq; 1365 1366 last_seq &= drv->num_fences_mask; 1367 sync_seq &= drv->num_fences_mask; 1368 1369 do { 1370 struct dma_fence *fence, **ptr; 1371 1372 ++last_seq; 1373 last_seq &= drv->num_fences_mask; 1374 ptr = &drv->fences[last_seq]; 1375 1376 fence = rcu_dereference_protected(*ptr, 1); 1377 RCU_INIT_POINTER(*ptr, NULL); 1378 1379 if (!fence) 1380 continue; 1381 1382 fences[last_seq] = fence; 1383 1384 } while (last_seq != sync_seq); 1385} 1386 1387static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences, 1388 int length) 1389{ 1390 int i; 1391 struct dma_fence *fence; 1392 1393 for (i = 0; i < length; i++) { 1394 fence = fences[i]; 1395 if (!fence) 1396 continue; 1397 dma_fence_signal(fence); 1398 dma_fence_put(fence); 1399 } 1400} 1401 1402static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched) 1403{ 1404 struct drm_sched_job *s_job; 1405 struct dma_fence *fence; 1406 1407 spin_lock(&sched->job_list_lock); 1408 list_for_each_entry(s_job, &sched->ring_mirror_list, node) { 1409 fence = sched->ops->run_job(s_job); 1410 dma_fence_put(fence); 1411 } 1412 spin_unlock(&sched->job_list_lock); 1413} 1414 1415static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring) 1416{ 1417 struct amdgpu_job *job; 1418 struct drm_sched_job *s_job, *tmp; 1419 uint32_t preempt_seq; 1420 struct dma_fence *fence, **ptr; 1421 struct amdgpu_fence_driver *drv = &ring->fence_drv; 1422 struct drm_gpu_scheduler *sched = &ring->sched; 1423 bool preempted = true; 1424 1425 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) 1426 return; 1427 1428 preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2)); 1429 if (preempt_seq <= atomic_read(&drv->last_seq)) { 1430 preempted = false; 1431 goto no_preempt; 1432 } 1433 1434 preempt_seq &= drv->num_fences_mask; 1435 ptr = &drv->fences[preempt_seq]; 1436 fence = rcu_dereference_protected(*ptr, 1); 1437 1438no_preempt: 1439 spin_lock(&sched->job_list_lock); 1440 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { 1441 if (dma_fence_is_signaled(&s_job->s_fence->finished)) { 1442 /* remove job from ring_mirror_list */ 1443 list_del_init(&s_job->node); 1444 sched->ops->free_job(s_job); 1445 continue; 1446 } 1447 job = to_amdgpu_job(s_job); 1448 if (preempted && job->fence == fence) 1449 /* mark the job as preempted */ 1450 job->preemption_status |= AMDGPU_IB_PREEMPTED; 1451 } 1452 spin_unlock(&sched->job_list_lock); 1453} 1454 1455static int amdgpu_debugfs_ib_preempt(void *data, u64 val) 1456{ 1457 int r, resched, length; 1458 struct amdgpu_ring *ring; 1459 struct dma_fence **fences = NULL; 1460 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1461 1462 if (val >= AMDGPU_MAX_RINGS) 1463 return -EINVAL; 1464 1465 ring = adev->rings[val]; 1466 1467 if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread) 1468 return -EINVAL; 1469 1470 /* the last preemption failed */ 1471 if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr)) 1472 return -EBUSY; 1473 1474 length = ring->fence_drv.num_fences_mask + 1; 1475 fences = kcalloc(length, sizeof(void *), GFP_KERNEL); 1476 if (!fences) 1477 return -ENOMEM; 1478 1479 /* Avoid accidently unparking the sched thread during GPU reset */ 1480 r = down_read_killable(&adev->reset_sem); 1481 if (r) 1482 goto pro_end; 1483 1484 /* stop the scheduler */ 1485 kthread_park(ring->sched.thread); 1486 1487 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev); 1488 1489 /* preempt the IB */ 1490 r = amdgpu_ring_preempt_ib(ring); 1491 if (r) { 1492 DRM_WARN("failed to preempt ring %d\n", ring->idx); 1493 goto failure; 1494 } 1495 1496 amdgpu_fence_process(ring); 1497 1498 if (atomic_read(&ring->fence_drv.last_seq) != 1499 ring->fence_drv.sync_seq) { 1500 DRM_INFO("ring %d was preempted\n", ring->idx); 1501 1502 amdgpu_ib_preempt_mark_partial_job(ring); 1503 1504 /* swap out the old fences */ 1505 amdgpu_ib_preempt_fences_swap(ring, fences); 1506 1507 amdgpu_fence_driver_force_completion(ring); 1508 1509 /* resubmit unfinished jobs */ 1510 amdgpu_ib_preempt_job_recovery(&ring->sched); 1511 1512 /* wait for jobs finished */ 1513 amdgpu_fence_wait_empty(ring); 1514 1515 /* signal the old fences */ 1516 amdgpu_ib_preempt_signal_fences(fences, length); 1517 } 1518 1519failure: 1520 /* restart the scheduler */ 1521 kthread_unpark(ring->sched.thread); 1522 1523 up_read(&adev->reset_sem); 1524 1525 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched); 1526 1527pro_end: 1528 kfree(fences); 1529 1530 return r; 1531} 1532 1533static int amdgpu_debugfs_sclk_set(void *data, u64 val) 1534{ 1535 int ret = 0; 1536 uint32_t max_freq, min_freq; 1537 struct amdgpu_device *adev = (struct amdgpu_device *)data; 1538 1539 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1540 return -EINVAL; 1541 1542 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 1543 if (ret < 0) { 1544 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1545 return ret; 1546 } 1547 1548 if (is_support_sw_smu(adev)) { 1549 ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq); 1550 if (ret || val > max_freq || val < min_freq) 1551 return -EINVAL; 1552 ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val); 1553 } else { 1554 return 0; 1555 } 1556 1557 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 1558 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 1559 1560 if (ret) 1561 return -EINVAL; 1562 1563 return 0; 1564} 1565 1566DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL, 1567 amdgpu_debugfs_ib_preempt, "%llu\n"); 1568 1569DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL, 1570 amdgpu_debugfs_sclk_set, "%llu\n"); 1571 1572int amdgpu_debugfs_init(struct amdgpu_device *adev) 1573{ 1574 int r, i; 1575 1576 adev->debugfs_preempt = 1577 debugfs_create_file("amdgpu_preempt_ib", 0600, 1578 adev_to_drm(adev)->primary->debugfs_root, adev, 1579 &fops_ib_preempt); 1580 if (!(adev->debugfs_preempt)) { 1581 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n"); 1582 return -EIO; 1583 } 1584 1585 adev->smu.debugfs_sclk = 1586 debugfs_create_file("amdgpu_force_sclk", 0200, 1587 adev_to_drm(adev)->primary->debugfs_root, adev, 1588 &fops_sclk_set); 1589 if (!(adev->smu.debugfs_sclk)) { 1590 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); 1591 return -EIO; 1592 } 1593 1594 /* Register debugfs entries for amdgpu_ttm */ 1595 r = amdgpu_ttm_debugfs_init(adev); 1596 if (r) { 1597 DRM_ERROR("Failed to init debugfs\n"); 1598 return r; 1599 } 1600 1601 r = amdgpu_debugfs_pm_init(adev); 1602 if (r) { 1603 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1604 return r; 1605 } 1606 1607 if (amdgpu_debugfs_sa_init(adev)) { 1608 dev_err(adev->dev, "failed to register debugfs file for SA\n"); 1609 } 1610 1611 if (amdgpu_debugfs_fence_init(adev)) 1612 dev_err(adev->dev, "fence debugfs file creation failed\n"); 1613 1614 r = amdgpu_debugfs_gem_init(adev); 1615 if (r) 1616 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1617 1618 r = amdgpu_debugfs_regs_init(adev); 1619 if (r) 1620 DRM_ERROR("registering register debugfs failed (%d).\n", r); 1621 1622 r = amdgpu_debugfs_firmware_init(adev); 1623 if (r) 1624 DRM_ERROR("registering firmware debugfs failed (%d).\n", r); 1625 1626#if defined(CONFIG_DRM_AMD_DC) 1627 if (amdgpu_device_has_dc_support(adev)) { 1628 if (dtn_debugfs_init(adev)) 1629 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n"); 1630 } 1631#endif 1632 1633 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 1634 struct amdgpu_ring *ring = adev->rings[i]; 1635 1636 if (!ring) 1637 continue; 1638 1639 if (amdgpu_debugfs_ring_init(adev, ring)) { 1640 DRM_ERROR("Failed to register debugfs file for rings !\n"); 1641 } 1642 } 1643 1644 amdgpu_ras_debugfs_create_all(adev); 1645 1646 amdgpu_debugfs_autodump_init(adev); 1647 1648 amdgpu_rap_debugfs_init(adev); 1649 1650 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list, 1651 ARRAY_SIZE(amdgpu_debugfs_list)); 1652} 1653 1654#else 1655int amdgpu_debugfs_init(struct amdgpu_device *adev) 1656{ 1657 return 0; 1658} 1659int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 1660{ 1661 return 0; 1662} 1663#endif 1664