18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0+ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Linux GPIOlib driver for the VIA VX855 integrated southbridge GPIO 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2009 VIA Technologies, Inc. 68c2ecf20Sopenharmony_ci * Copyright (C) 2010 One Laptop per Child 78c2ecf20Sopenharmony_ci * Author: Harald Welte <HaraldWelte@viatech.com> 88c2ecf20Sopenharmony_ci * All rights reserved. 98c2ecf20Sopenharmony_ci */ 108c2ecf20Sopenharmony_ci#include <linux/kernel.h> 118c2ecf20Sopenharmony_ci#include <linux/module.h> 128c2ecf20Sopenharmony_ci#include <linux/gpio/driver.h> 138c2ecf20Sopenharmony_ci#include <linux/slab.h> 148c2ecf20Sopenharmony_ci#include <linux/device.h> 158c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 168c2ecf20Sopenharmony_ci#include <linux/pci.h> 178c2ecf20Sopenharmony_ci#include <linux/io.h> 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci#define MODULE_NAME "vx855_gpio" 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_ci/* The VX855 south bridge has the following GPIO pins: 228c2ecf20Sopenharmony_ci * GPI 0...13 General Purpose Input 238c2ecf20Sopenharmony_ci * GPO 0...12 General Purpose Output 248c2ecf20Sopenharmony_ci * GPIO 0...14 General Purpose I/O (Open-Drain) 258c2ecf20Sopenharmony_ci */ 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci#define NR_VX855_GPI 14 288c2ecf20Sopenharmony_ci#define NR_VX855_GPO 13 298c2ecf20Sopenharmony_ci#define NR_VX855_GPIO 15 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#define NR_VX855_GPInO (NR_VX855_GPI + NR_VX855_GPO) 328c2ecf20Sopenharmony_ci#define NR_VX855_GP (NR_VX855_GPI + NR_VX855_GPO + NR_VX855_GPIO) 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_cistruct vx855_gpio { 358c2ecf20Sopenharmony_ci struct gpio_chip gpio; 368c2ecf20Sopenharmony_ci spinlock_t lock; 378c2ecf20Sopenharmony_ci u32 io_gpi; 388c2ecf20Sopenharmony_ci u32 io_gpo; 398c2ecf20Sopenharmony_ci}; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci/* resolve a GPIx into the corresponding bit position */ 428c2ecf20Sopenharmony_cistatic inline u_int32_t gpi_i_bit(int i) 438c2ecf20Sopenharmony_ci{ 448c2ecf20Sopenharmony_ci if (i < 10) 458c2ecf20Sopenharmony_ci return 1 << i; 468c2ecf20Sopenharmony_ci else 478c2ecf20Sopenharmony_ci return 1 << (i + 14); 488c2ecf20Sopenharmony_ci} 498c2ecf20Sopenharmony_ci 508c2ecf20Sopenharmony_cistatic inline u_int32_t gpo_o_bit(int i) 518c2ecf20Sopenharmony_ci{ 528c2ecf20Sopenharmony_ci if (i < 11) 538c2ecf20Sopenharmony_ci return 1 << i; 548c2ecf20Sopenharmony_ci else 558c2ecf20Sopenharmony_ci return 1 << (i + 14); 568c2ecf20Sopenharmony_ci} 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_cistatic inline u_int32_t gpio_i_bit(int i) 598c2ecf20Sopenharmony_ci{ 608c2ecf20Sopenharmony_ci if (i < 14) 618c2ecf20Sopenharmony_ci return 1 << (i + 10); 628c2ecf20Sopenharmony_ci else 638c2ecf20Sopenharmony_ci return 1 << (i + 14); 648c2ecf20Sopenharmony_ci} 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_cistatic inline u_int32_t gpio_o_bit(int i) 678c2ecf20Sopenharmony_ci{ 688c2ecf20Sopenharmony_ci if (i < 14) 698c2ecf20Sopenharmony_ci return 1 << (i + 11); 708c2ecf20Sopenharmony_ci else 718c2ecf20Sopenharmony_ci return 1 << (i + 13); 728c2ecf20Sopenharmony_ci} 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci/* Mapping between numeric GPIO ID and the actual GPIO hardware numbering: 758c2ecf20Sopenharmony_ci * 0..13 GPI 0..13 768c2ecf20Sopenharmony_ci * 14..26 GPO 0..12 778c2ecf20Sopenharmony_ci * 27..41 GPIO 0..14 788c2ecf20Sopenharmony_ci */ 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_cistatic int vx855gpio_direction_input(struct gpio_chip *gpio, 818c2ecf20Sopenharmony_ci unsigned int nr) 828c2ecf20Sopenharmony_ci{ 838c2ecf20Sopenharmony_ci struct vx855_gpio *vg = gpiochip_get_data(gpio); 848c2ecf20Sopenharmony_ci unsigned long flags; 858c2ecf20Sopenharmony_ci u_int32_t reg_out; 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci /* Real GPI bits are always in input direction */ 888c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPI) 898c2ecf20Sopenharmony_ci return 0; 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ci /* Real GPO bits cannot be put in output direction */ 928c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPInO) 938c2ecf20Sopenharmony_ci return -EINVAL; 948c2ecf20Sopenharmony_ci 958c2ecf20Sopenharmony_ci /* Open Drain GPIO have to be set to one */ 968c2ecf20Sopenharmony_ci spin_lock_irqsave(&vg->lock, flags); 978c2ecf20Sopenharmony_ci reg_out = inl(vg->io_gpo); 988c2ecf20Sopenharmony_ci reg_out |= gpio_o_bit(nr - NR_VX855_GPInO); 998c2ecf20Sopenharmony_ci outl(reg_out, vg->io_gpo); 1008c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&vg->lock, flags); 1018c2ecf20Sopenharmony_ci 1028c2ecf20Sopenharmony_ci return 0; 1038c2ecf20Sopenharmony_ci} 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_cistatic int vx855gpio_get(struct gpio_chip *gpio, unsigned int nr) 1068c2ecf20Sopenharmony_ci{ 1078c2ecf20Sopenharmony_ci struct vx855_gpio *vg = gpiochip_get_data(gpio); 1088c2ecf20Sopenharmony_ci u_int32_t reg_in; 1098c2ecf20Sopenharmony_ci int ret = 0; 1108c2ecf20Sopenharmony_ci 1118c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPI) { 1128c2ecf20Sopenharmony_ci reg_in = inl(vg->io_gpi); 1138c2ecf20Sopenharmony_ci if (reg_in & gpi_i_bit(nr)) 1148c2ecf20Sopenharmony_ci ret = 1; 1158c2ecf20Sopenharmony_ci } else if (nr < NR_VX855_GPInO) { 1168c2ecf20Sopenharmony_ci /* GPO don't have an input bit, we need to read it 1178c2ecf20Sopenharmony_ci * back from the output register */ 1188c2ecf20Sopenharmony_ci reg_in = inl(vg->io_gpo); 1198c2ecf20Sopenharmony_ci if (reg_in & gpo_o_bit(nr - NR_VX855_GPI)) 1208c2ecf20Sopenharmony_ci ret = 1; 1218c2ecf20Sopenharmony_ci } else { 1228c2ecf20Sopenharmony_ci reg_in = inl(vg->io_gpi); 1238c2ecf20Sopenharmony_ci if (reg_in & gpio_i_bit(nr - NR_VX855_GPInO)) 1248c2ecf20Sopenharmony_ci ret = 1; 1258c2ecf20Sopenharmony_ci } 1268c2ecf20Sopenharmony_ci 1278c2ecf20Sopenharmony_ci return ret; 1288c2ecf20Sopenharmony_ci} 1298c2ecf20Sopenharmony_ci 1308c2ecf20Sopenharmony_cistatic void vx855gpio_set(struct gpio_chip *gpio, unsigned int nr, 1318c2ecf20Sopenharmony_ci int val) 1328c2ecf20Sopenharmony_ci{ 1338c2ecf20Sopenharmony_ci struct vx855_gpio *vg = gpiochip_get_data(gpio); 1348c2ecf20Sopenharmony_ci unsigned long flags; 1358c2ecf20Sopenharmony_ci u_int32_t reg_out; 1368c2ecf20Sopenharmony_ci 1378c2ecf20Sopenharmony_ci /* True GPI cannot be switched to output mode */ 1388c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPI) 1398c2ecf20Sopenharmony_ci return; 1408c2ecf20Sopenharmony_ci 1418c2ecf20Sopenharmony_ci spin_lock_irqsave(&vg->lock, flags); 1428c2ecf20Sopenharmony_ci reg_out = inl(vg->io_gpo); 1438c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPInO) { 1448c2ecf20Sopenharmony_ci if (val) 1458c2ecf20Sopenharmony_ci reg_out |= gpo_o_bit(nr - NR_VX855_GPI); 1468c2ecf20Sopenharmony_ci else 1478c2ecf20Sopenharmony_ci reg_out &= ~gpo_o_bit(nr - NR_VX855_GPI); 1488c2ecf20Sopenharmony_ci } else { 1498c2ecf20Sopenharmony_ci if (val) 1508c2ecf20Sopenharmony_ci reg_out |= gpio_o_bit(nr - NR_VX855_GPInO); 1518c2ecf20Sopenharmony_ci else 1528c2ecf20Sopenharmony_ci reg_out &= ~gpio_o_bit(nr - NR_VX855_GPInO); 1538c2ecf20Sopenharmony_ci } 1548c2ecf20Sopenharmony_ci outl(reg_out, vg->io_gpo); 1558c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&vg->lock, flags); 1568c2ecf20Sopenharmony_ci} 1578c2ecf20Sopenharmony_ci 1588c2ecf20Sopenharmony_cistatic int vx855gpio_direction_output(struct gpio_chip *gpio, 1598c2ecf20Sopenharmony_ci unsigned int nr, int val) 1608c2ecf20Sopenharmony_ci{ 1618c2ecf20Sopenharmony_ci /* True GPI cannot be switched to output mode */ 1628c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPI) 1638c2ecf20Sopenharmony_ci return -EINVAL; 1648c2ecf20Sopenharmony_ci 1658c2ecf20Sopenharmony_ci /* True GPO don't need to be switched to output mode, 1668c2ecf20Sopenharmony_ci * and GPIO are open-drain, i.e. also need no switching, 1678c2ecf20Sopenharmony_ci * so all we do is set the level */ 1688c2ecf20Sopenharmony_ci vx855gpio_set(gpio, nr, val); 1698c2ecf20Sopenharmony_ci 1708c2ecf20Sopenharmony_ci return 0; 1718c2ecf20Sopenharmony_ci} 1728c2ecf20Sopenharmony_ci 1738c2ecf20Sopenharmony_cistatic int vx855gpio_set_config(struct gpio_chip *gpio, unsigned int nr, 1748c2ecf20Sopenharmony_ci unsigned long config) 1758c2ecf20Sopenharmony_ci{ 1768c2ecf20Sopenharmony_ci enum pin_config_param param = pinconf_to_config_param(config); 1778c2ecf20Sopenharmony_ci 1788c2ecf20Sopenharmony_ci /* The GPI cannot be single-ended */ 1798c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPI) 1808c2ecf20Sopenharmony_ci return -EINVAL; 1818c2ecf20Sopenharmony_ci 1828c2ecf20Sopenharmony_ci /* The GPO's are push-pull */ 1838c2ecf20Sopenharmony_ci if (nr < NR_VX855_GPInO) { 1848c2ecf20Sopenharmony_ci if (param != PIN_CONFIG_DRIVE_PUSH_PULL) 1858c2ecf20Sopenharmony_ci return -ENOTSUPP; 1868c2ecf20Sopenharmony_ci return 0; 1878c2ecf20Sopenharmony_ci } 1888c2ecf20Sopenharmony_ci 1898c2ecf20Sopenharmony_ci /* The GPIO's are open drain */ 1908c2ecf20Sopenharmony_ci if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN) 1918c2ecf20Sopenharmony_ci return -ENOTSUPP; 1928c2ecf20Sopenharmony_ci 1938c2ecf20Sopenharmony_ci return 0; 1948c2ecf20Sopenharmony_ci} 1958c2ecf20Sopenharmony_ci 1968c2ecf20Sopenharmony_cistatic const char *vx855gpio_names[NR_VX855_GP] = { 1978c2ecf20Sopenharmony_ci "VX855_GPI0", "VX855_GPI1", "VX855_GPI2", "VX855_GPI3", "VX855_GPI4", 1988c2ecf20Sopenharmony_ci "VX855_GPI5", "VX855_GPI6", "VX855_GPI7", "VX855_GPI8", "VX855_GPI9", 1998c2ecf20Sopenharmony_ci "VX855_GPI10", "VX855_GPI11", "VX855_GPI12", "VX855_GPI13", 2008c2ecf20Sopenharmony_ci "VX855_GPO0", "VX855_GPO1", "VX855_GPO2", "VX855_GPO3", "VX855_GPO4", 2018c2ecf20Sopenharmony_ci "VX855_GPO5", "VX855_GPO6", "VX855_GPO7", "VX855_GPO8", "VX855_GPO9", 2028c2ecf20Sopenharmony_ci "VX855_GPO10", "VX855_GPO11", "VX855_GPO12", 2038c2ecf20Sopenharmony_ci "VX855_GPIO0", "VX855_GPIO1", "VX855_GPIO2", "VX855_GPIO3", 2048c2ecf20Sopenharmony_ci "VX855_GPIO4", "VX855_GPIO5", "VX855_GPIO6", "VX855_GPIO7", 2058c2ecf20Sopenharmony_ci "VX855_GPIO8", "VX855_GPIO9", "VX855_GPIO10", "VX855_GPIO11", 2068c2ecf20Sopenharmony_ci "VX855_GPIO12", "VX855_GPIO13", "VX855_GPIO14" 2078c2ecf20Sopenharmony_ci}; 2088c2ecf20Sopenharmony_ci 2098c2ecf20Sopenharmony_cistatic void vx855gpio_gpio_setup(struct vx855_gpio *vg) 2108c2ecf20Sopenharmony_ci{ 2118c2ecf20Sopenharmony_ci struct gpio_chip *c = &vg->gpio; 2128c2ecf20Sopenharmony_ci 2138c2ecf20Sopenharmony_ci c->label = "VX855 South Bridge"; 2148c2ecf20Sopenharmony_ci c->owner = THIS_MODULE; 2158c2ecf20Sopenharmony_ci c->direction_input = vx855gpio_direction_input; 2168c2ecf20Sopenharmony_ci c->direction_output = vx855gpio_direction_output; 2178c2ecf20Sopenharmony_ci c->get = vx855gpio_get; 2188c2ecf20Sopenharmony_ci c->set = vx855gpio_set; 2198c2ecf20Sopenharmony_ci c->set_config = vx855gpio_set_config, 2208c2ecf20Sopenharmony_ci c->dbg_show = NULL; 2218c2ecf20Sopenharmony_ci c->base = 0; 2228c2ecf20Sopenharmony_ci c->ngpio = NR_VX855_GP; 2238c2ecf20Sopenharmony_ci c->can_sleep = false; 2248c2ecf20Sopenharmony_ci c->names = vx855gpio_names; 2258c2ecf20Sopenharmony_ci} 2268c2ecf20Sopenharmony_ci 2278c2ecf20Sopenharmony_ci/* This platform device is ordinarily registered by the vx855 mfd driver */ 2288c2ecf20Sopenharmony_cistatic int vx855gpio_probe(struct platform_device *pdev) 2298c2ecf20Sopenharmony_ci{ 2308c2ecf20Sopenharmony_ci struct resource *res_gpi; 2318c2ecf20Sopenharmony_ci struct resource *res_gpo; 2328c2ecf20Sopenharmony_ci struct vx855_gpio *vg; 2338c2ecf20Sopenharmony_ci 2348c2ecf20Sopenharmony_ci res_gpi = platform_get_resource(pdev, IORESOURCE_IO, 0); 2358c2ecf20Sopenharmony_ci res_gpo = platform_get_resource(pdev, IORESOURCE_IO, 1); 2368c2ecf20Sopenharmony_ci if (!res_gpi || !res_gpo) 2378c2ecf20Sopenharmony_ci return -EBUSY; 2388c2ecf20Sopenharmony_ci 2398c2ecf20Sopenharmony_ci vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL); 2408c2ecf20Sopenharmony_ci if (!vg) 2418c2ecf20Sopenharmony_ci return -ENOMEM; 2428c2ecf20Sopenharmony_ci 2438c2ecf20Sopenharmony_ci platform_set_drvdata(pdev, vg); 2448c2ecf20Sopenharmony_ci 2458c2ecf20Sopenharmony_ci dev_info(&pdev->dev, "found VX855 GPIO controller\n"); 2468c2ecf20Sopenharmony_ci vg->io_gpi = res_gpi->start; 2478c2ecf20Sopenharmony_ci vg->io_gpo = res_gpo->start; 2488c2ecf20Sopenharmony_ci spin_lock_init(&vg->lock); 2498c2ecf20Sopenharmony_ci 2508c2ecf20Sopenharmony_ci /* 2518c2ecf20Sopenharmony_ci * A single byte is used to control various GPIO ports on the VX855, 2528c2ecf20Sopenharmony_ci * and in the case of the OLPC XO-1.5, some of those ports are used 2538c2ecf20Sopenharmony_ci * for switches that are interpreted and exposed through ACPI. ACPI 2548c2ecf20Sopenharmony_ci * will have reserved the region, so our own reservation will not 2558c2ecf20Sopenharmony_ci * succeed. Ignore and continue. 2568c2ecf20Sopenharmony_ci */ 2578c2ecf20Sopenharmony_ci 2588c2ecf20Sopenharmony_ci if (!devm_request_region(&pdev->dev, res_gpi->start, 2598c2ecf20Sopenharmony_ci resource_size(res_gpi), MODULE_NAME "_gpi")) 2608c2ecf20Sopenharmony_ci dev_warn(&pdev->dev, 2618c2ecf20Sopenharmony_ci "GPI I/O resource busy, probably claimed by ACPI\n"); 2628c2ecf20Sopenharmony_ci 2638c2ecf20Sopenharmony_ci if (!devm_request_region(&pdev->dev, res_gpo->start, 2648c2ecf20Sopenharmony_ci resource_size(res_gpo), MODULE_NAME "_gpo")) 2658c2ecf20Sopenharmony_ci dev_warn(&pdev->dev, 2668c2ecf20Sopenharmony_ci "GPO I/O resource busy, probably claimed by ACPI\n"); 2678c2ecf20Sopenharmony_ci 2688c2ecf20Sopenharmony_ci vx855gpio_gpio_setup(vg); 2698c2ecf20Sopenharmony_ci 2708c2ecf20Sopenharmony_ci return devm_gpiochip_add_data(&pdev->dev, &vg->gpio, vg); 2718c2ecf20Sopenharmony_ci} 2728c2ecf20Sopenharmony_ci 2738c2ecf20Sopenharmony_cistatic struct platform_driver vx855gpio_driver = { 2748c2ecf20Sopenharmony_ci .driver = { 2758c2ecf20Sopenharmony_ci .name = MODULE_NAME, 2768c2ecf20Sopenharmony_ci }, 2778c2ecf20Sopenharmony_ci .probe = vx855gpio_probe, 2788c2ecf20Sopenharmony_ci}; 2798c2ecf20Sopenharmony_ci 2808c2ecf20Sopenharmony_cimodule_platform_driver(vx855gpio_driver); 2818c2ecf20Sopenharmony_ci 2828c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 2838c2ecf20Sopenharmony_ciMODULE_AUTHOR("Harald Welte <HaraldWelte@viatech.com>"); 2848c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("GPIO driver for the VIA VX855 chipset"); 2858c2ecf20Sopenharmony_ciMODULE_ALIAS("platform:vx855_gpio"); 286