1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016-2017 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 */ 7 8#include <linux/gpio/driver.h> 9#include <linux/interrupt.h> 10#include <linux/irq.h> 11#include <linux/module.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14 15#include <dt-bindings/gpio/tegra186-gpio.h> 16#include <dt-bindings/gpio/tegra194-gpio.h> 17 18/* security registers */ 19#define TEGRA186_GPIO_CTL_SCR 0x0c 20#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 21#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 22 23#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 24 25/* control registers */ 26#define TEGRA186_GPIO_ENABLE_CONFIG 0x00 27#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 28#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 29#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 30#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 31#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 32#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 33#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 34#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 35#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 36#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 37 38#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 39#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 40 41#define TEGRA186_GPIO_INPUT 0x08 42#define TEGRA186_GPIO_INPUT_HIGH BIT(0) 43 44#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 45#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 46 47#define TEGRA186_GPIO_OUTPUT_VALUE 0x10 48#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 49 50#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 51 52#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 53 54struct tegra_gpio_port { 55 const char *name; 56 unsigned int bank; 57 unsigned int port; 58 unsigned int pins; 59}; 60 61struct tegra186_pin_range { 62 unsigned int offset; 63 const char *group; 64}; 65 66struct tegra_gpio_soc { 67 const struct tegra_gpio_port *ports; 68 unsigned int num_ports; 69 const char *name; 70 unsigned int instance; 71 72 const struct tegra186_pin_range *pin_ranges; 73 unsigned int num_pin_ranges; 74 const char *pinmux; 75}; 76 77struct tegra_gpio { 78 struct gpio_chip gpio; 79 struct irq_chip intc; 80 unsigned int num_irq; 81 unsigned int *irq; 82 83 const struct tegra_gpio_soc *soc; 84 85 void __iomem *secure; 86 void __iomem *base; 87}; 88 89static const struct tegra_gpio_port * 90tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 91{ 92 unsigned int start = 0, i; 93 94 for (i = 0; i < gpio->soc->num_ports; i++) { 95 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 96 97 if (*pin >= start && *pin < start + port->pins) { 98 *pin -= start; 99 return port; 100 } 101 102 start += port->pins; 103 } 104 105 return NULL; 106} 107 108static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 109 unsigned int pin) 110{ 111 const struct tegra_gpio_port *port; 112 unsigned int offset; 113 114 port = tegra186_gpio_get_port(gpio, &pin); 115 if (!port) 116 return NULL; 117 118 offset = port->bank * 0x1000 + port->port * 0x200; 119 120 return gpio->base + offset + pin * 0x20; 121} 122 123static int tegra186_gpio_get_direction(struct gpio_chip *chip, 124 unsigned int offset) 125{ 126 struct tegra_gpio *gpio = gpiochip_get_data(chip); 127 void __iomem *base; 128 u32 value; 129 130 base = tegra186_gpio_get_base(gpio, offset); 131 if (WARN_ON(base == NULL)) 132 return -ENODEV; 133 134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 136 return GPIO_LINE_DIRECTION_OUT; 137 138 return GPIO_LINE_DIRECTION_IN; 139} 140 141static int tegra186_gpio_direction_input(struct gpio_chip *chip, 142 unsigned int offset) 143{ 144 struct tegra_gpio *gpio = gpiochip_get_data(chip); 145 void __iomem *base; 146 u32 value; 147 148 base = tegra186_gpio_get_base(gpio, offset); 149 if (WARN_ON(base == NULL)) 150 return -ENODEV; 151 152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 155 156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 160 161 return 0; 162} 163 164static int tegra186_gpio_direction_output(struct gpio_chip *chip, 165 unsigned int offset, int level) 166{ 167 struct tegra_gpio *gpio = gpiochip_get_data(chip); 168 void __iomem *base; 169 u32 value; 170 171 /* configure output level first */ 172 chip->set(chip, offset, level); 173 174 base = tegra186_gpio_get_base(gpio, offset); 175 if (WARN_ON(base == NULL)) 176 return -EINVAL; 177 178 /* set the direction */ 179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 182 183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 187 188 return 0; 189} 190 191static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 192{ 193 struct tegra_gpio *gpio = gpiochip_get_data(chip); 194 void __iomem *base; 195 u32 value; 196 197 base = tegra186_gpio_get_base(gpio, offset); 198 if (WARN_ON(base == NULL)) 199 return -ENODEV; 200 201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 204 else 205 value = readl(base + TEGRA186_GPIO_INPUT); 206 207 return value & BIT(0); 208} 209 210static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 211 int level) 212{ 213 struct tegra_gpio *gpio = gpiochip_get_data(chip); 214 void __iomem *base; 215 u32 value; 216 217 base = tegra186_gpio_get_base(gpio, offset); 218 if (WARN_ON(base == NULL)) 219 return; 220 221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 222 if (level == 0) 223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 224 else 225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 226 227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 228} 229 230static int tegra186_gpio_set_config(struct gpio_chip *chip, 231 unsigned int offset, 232 unsigned long config) 233{ 234 struct tegra_gpio *gpio = gpiochip_get_data(chip); 235 u32 debounce, value; 236 void __iomem *base; 237 238 base = tegra186_gpio_get_base(gpio, offset); 239 if (base == NULL) 240 return -ENXIO; 241 242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 243 return -ENOTSUPP; 244 245 debounce = pinconf_to_config_argument(config); 246 247 /* 248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 249 * time. 250 */ 251 if (debounce > 255000) 252 return -EINVAL; 253 254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 255 256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 258 259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 262 263 return 0; 264} 265 266static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 267{ 268 struct tegra_gpio *gpio = gpiochip_get_data(chip); 269 struct pinctrl_dev *pctldev; 270 struct device_node *np; 271 unsigned int i, j; 272 int err; 273 274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 275 return 0; 276 277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 278 if (!np) 279 return -ENODEV; 280 281 pctldev = of_pinctrl_get(np); 282 of_node_put(np); 283 if (!pctldev) 284 return -EPROBE_DEFER; 285 286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 288 const char *group = gpio->soc->pin_ranges[i].group; 289 290 port = pin / 8; 291 pin = pin % 8; 292 293 if (port >= gpio->soc->num_ports) { 294 dev_warn(chip->parent, "invalid port %u for %s\n", 295 port, group); 296 continue; 297 } 298 299 for (j = 0; j < port; j++) 300 pin += gpio->soc->ports[j].pins; 301 302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 303 if (err < 0) 304 return err; 305 } 306 307 return 0; 308} 309 310static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 311 const struct of_phandle_args *spec, 312 u32 *flags) 313{ 314 struct tegra_gpio *gpio = gpiochip_get_data(chip); 315 unsigned int port, pin, i, offset = 0; 316 317 if (WARN_ON(chip->of_gpio_n_cells < 2)) 318 return -EINVAL; 319 320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 321 return -EINVAL; 322 323 port = spec->args[0] / 8; 324 pin = spec->args[0] % 8; 325 326 if (port >= gpio->soc->num_ports) { 327 dev_err(chip->parent, "invalid port number: %u\n", port); 328 return -EINVAL; 329 } 330 331 for (i = 0; i < port; i++) 332 offset += gpio->soc->ports[i].pins; 333 334 if (flags) 335 *flags = spec->args[1]; 336 337 return offset + pin; 338} 339 340#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 341 342static void tegra186_irq_ack(struct irq_data *data) 343{ 344 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 345 struct tegra_gpio *gpio = to_tegra_gpio(gc); 346 void __iomem *base; 347 348 base = tegra186_gpio_get_base(gpio, data->hwirq); 349 if (WARN_ON(base == NULL)) 350 return; 351 352 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 353} 354 355static void tegra186_irq_mask(struct irq_data *data) 356{ 357 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 358 struct tegra_gpio *gpio = to_tegra_gpio(gc); 359 void __iomem *base; 360 u32 value; 361 362 base = tegra186_gpio_get_base(gpio, data->hwirq); 363 if (WARN_ON(base == NULL)) 364 return; 365 366 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 367 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 368 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 369} 370 371static void tegra186_irq_unmask(struct irq_data *data) 372{ 373 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 374 struct tegra_gpio *gpio = to_tegra_gpio(gc); 375 void __iomem *base; 376 u32 value; 377 378 base = tegra186_gpio_get_base(gpio, data->hwirq); 379 if (WARN_ON(base == NULL)) 380 return; 381 382 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 383 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 384 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 385} 386 387static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 388{ 389 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 390 struct tegra_gpio *gpio = to_tegra_gpio(gc); 391 void __iomem *base; 392 u32 value; 393 394 base = tegra186_gpio_get_base(gpio, data->hwirq); 395 if (WARN_ON(base == NULL)) 396 return -ENODEV; 397 398 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 399 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 400 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 401 402 switch (type & IRQ_TYPE_SENSE_MASK) { 403 case IRQ_TYPE_NONE: 404 break; 405 406 case IRQ_TYPE_EDGE_RISING: 407 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 408 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 409 break; 410 411 case IRQ_TYPE_EDGE_FALLING: 412 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 413 break; 414 415 case IRQ_TYPE_EDGE_BOTH: 416 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 417 break; 418 419 case IRQ_TYPE_LEVEL_HIGH: 420 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 421 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 422 break; 423 424 case IRQ_TYPE_LEVEL_LOW: 425 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 426 break; 427 428 default: 429 return -EINVAL; 430 } 431 432 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 433 434 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 435 irq_set_handler_locked(data, handle_level_irq); 436 else 437 irq_set_handler_locked(data, handle_edge_irq); 438 439 if (data->parent_data) 440 return irq_chip_set_type_parent(data, type); 441 442 return 0; 443} 444 445static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 446{ 447 if (data->parent_data) 448 return irq_chip_set_wake_parent(data, on); 449 450 return 0; 451} 452 453static void tegra186_gpio_irq(struct irq_desc *desc) 454{ 455 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 456 struct irq_domain *domain = gpio->gpio.irq.domain; 457 struct irq_chip *chip = irq_desc_get_chip(desc); 458 unsigned int parent = irq_desc_get_irq(desc); 459 unsigned int i, offset = 0; 460 461 chained_irq_enter(chip, desc); 462 463 for (i = 0; i < gpio->soc->num_ports; i++) { 464 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 465 unsigned int pin, irq; 466 unsigned long value; 467 void __iomem *base; 468 469 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 470 471 /* skip ports that are not associated with this bank */ 472 if (parent != gpio->irq[port->bank]) 473 goto skip; 474 475 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 476 477 for_each_set_bit(pin, &value, port->pins) { 478 irq = irq_find_mapping(domain, offset + pin); 479 if (WARN_ON(irq == 0)) 480 continue; 481 482 generic_handle_irq(irq); 483 } 484 485skip: 486 offset += port->pins; 487 } 488 489 chained_irq_exit(chip, desc); 490} 491 492static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 493 struct irq_fwspec *fwspec, 494 unsigned long *hwirq, 495 unsigned int *type) 496{ 497 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 498 unsigned int port, pin, i, offset = 0; 499 500 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 501 return -EINVAL; 502 503 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 504 return -EINVAL; 505 506 port = fwspec->param[0] / 8; 507 pin = fwspec->param[0] % 8; 508 509 if (port >= gpio->soc->num_ports) 510 return -EINVAL; 511 512 for (i = 0; i < port; i++) 513 offset += gpio->soc->ports[i].pins; 514 515 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 516 *hwirq = offset + pin; 517 518 return 0; 519} 520 521static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 522 unsigned int parent_hwirq, 523 unsigned int parent_type) 524{ 525 struct tegra_gpio *gpio = gpiochip_get_data(chip); 526 struct irq_fwspec *fwspec; 527 528 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); 529 if (!fwspec) 530 return NULL; 531 532 fwspec->fwnode = chip->irq.parent_domain->fwnode; 533 fwspec->param_count = 3; 534 fwspec->param[0] = gpio->soc->instance; 535 fwspec->param[1] = parent_hwirq; 536 fwspec->param[2] = parent_type; 537 538 return fwspec; 539} 540 541static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 542 unsigned int hwirq, 543 unsigned int type, 544 unsigned int *parent_hwirq, 545 unsigned int *parent_type) 546{ 547 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 548 *parent_type = type; 549 550 return 0; 551} 552 553static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 554 unsigned int offset) 555{ 556 struct tegra_gpio *gpio = gpiochip_get_data(chip); 557 unsigned int i; 558 559 for (i = 0; i < gpio->soc->num_ports; i++) { 560 if (offset < gpio->soc->ports[i].pins) 561 break; 562 563 offset -= gpio->soc->ports[i].pins; 564 } 565 566 return offset + i * 8; 567} 568 569static const struct of_device_id tegra186_pmc_of_match[] = { 570 { .compatible = "nvidia,tegra186-pmc" }, 571 { .compatible = "nvidia,tegra194-pmc" }, 572 { /* sentinel */ } 573}; 574 575static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 576{ 577 unsigned int i, j; 578 u32 value; 579 580 for (i = 0; i < gpio->soc->num_ports; i++) { 581 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 582 unsigned int offset, p = port->port; 583 void __iomem *base; 584 585 base = gpio->secure + port->bank * 0x1000 + 0x800; 586 587 value = readl(base + TEGRA186_GPIO_CTL_SCR); 588 589 /* 590 * For controllers that haven't been locked down yet, make 591 * sure to program the default interrupt route mapping. 592 */ 593 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 594 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 595 for (j = 0; j < 8; j++) { 596 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); 597 598 value = readl(base + offset); 599 value = BIT(port->pins) - 1; 600 writel(value, base + offset); 601 } 602 } 603 } 604} 605 606static int tegra186_gpio_probe(struct platform_device *pdev) 607{ 608 unsigned int i, j, offset; 609 struct gpio_irq_chip *irq; 610 struct tegra_gpio *gpio; 611 struct device_node *np; 612 char **names; 613 int err; 614 615 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 616 if (!gpio) 617 return -ENOMEM; 618 619 gpio->soc = of_device_get_match_data(&pdev->dev); 620 621 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); 622 if (IS_ERR(gpio->secure)) 623 return PTR_ERR(gpio->secure); 624 625 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); 626 if (IS_ERR(gpio->base)) 627 return PTR_ERR(gpio->base); 628 629 err = platform_irq_count(pdev); 630 if (err < 0) 631 return err; 632 633 gpio->num_irq = err; 634 635 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 636 GFP_KERNEL); 637 if (!gpio->irq) 638 return -ENOMEM; 639 640 for (i = 0; i < gpio->num_irq; i++) { 641 err = platform_get_irq(pdev, i); 642 if (err < 0) 643 return err; 644 645 gpio->irq[i] = err; 646 } 647 648 gpio->gpio.label = gpio->soc->name; 649 gpio->gpio.parent = &pdev->dev; 650 651 gpio->gpio.request = gpiochip_generic_request; 652 gpio->gpio.free = gpiochip_generic_free; 653 gpio->gpio.get_direction = tegra186_gpio_get_direction; 654 gpio->gpio.direction_input = tegra186_gpio_direction_input; 655 gpio->gpio.direction_output = tegra186_gpio_direction_output; 656 gpio->gpio.get = tegra186_gpio_get, 657 gpio->gpio.set = tegra186_gpio_set; 658 gpio->gpio.set_config = tegra186_gpio_set_config; 659 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 660 661 gpio->gpio.base = -1; 662 663 for (i = 0; i < gpio->soc->num_ports; i++) 664 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 665 666 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 667 sizeof(*names), GFP_KERNEL); 668 if (!names) 669 return -ENOMEM; 670 671 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 672 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 673 char *name; 674 675 for (j = 0; j < port->pins; j++) { 676 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 677 "P%s.%02x", port->name, j); 678 if (!name) 679 return -ENOMEM; 680 681 names[offset + j] = name; 682 } 683 684 offset += port->pins; 685 } 686 687 gpio->gpio.names = (const char * const *)names; 688 689 gpio->gpio.of_node = pdev->dev.of_node; 690 gpio->gpio.of_gpio_n_cells = 2; 691 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 692 693 gpio->intc.name = pdev->dev.of_node->name; 694 gpio->intc.irq_ack = tegra186_irq_ack; 695 gpio->intc.irq_mask = tegra186_irq_mask; 696 gpio->intc.irq_unmask = tegra186_irq_unmask; 697 gpio->intc.irq_set_type = tegra186_irq_set_type; 698 gpio->intc.irq_set_wake = tegra186_irq_set_wake; 699 700 irq = &gpio->gpio.irq; 701 irq->chip = &gpio->intc; 702 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); 703 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 704 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 705 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 706 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 707 irq->handler = handle_simple_irq; 708 irq->default_type = IRQ_TYPE_NONE; 709 irq->parent_handler = tegra186_gpio_irq; 710 irq->parent_handler_data = gpio; 711 irq->num_parents = gpio->num_irq; 712 irq->parents = gpio->irq; 713 714 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 715 if (np) { 716 irq->parent_domain = irq_find_host(np); 717 of_node_put(np); 718 719 if (!irq->parent_domain) 720 return -EPROBE_DEFER; 721 } 722 723 tegra186_gpio_init_route_mapping(gpio); 724 725 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 726 sizeof(*irq->map), GFP_KERNEL); 727 if (!irq->map) 728 return -ENOMEM; 729 730 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 731 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 732 733 for (j = 0; j < port->pins; j++) 734 irq->map[offset + j] = irq->parents[port->bank]; 735 736 offset += port->pins; 737 } 738 739 platform_set_drvdata(pdev, gpio); 740 741 err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 742 if (err < 0) 743 return err; 744 745 return 0; 746} 747 748static int tegra186_gpio_remove(struct platform_device *pdev) 749{ 750 return 0; 751} 752 753#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 754 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 755 .name = #_name, \ 756 .bank = _bank, \ 757 .port = _port, \ 758 .pins = _pins, \ 759 } 760 761static const struct tegra_gpio_port tegra186_main_ports[] = { 762 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 763 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 764 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 765 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 766 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 767 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 768 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 769 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 770 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 771 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 772 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 773 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 774 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 775 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 776 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 777 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 778 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 779 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 780 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 781 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 782 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 783 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 784 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 785}; 786 787static const struct tegra_gpio_soc tegra186_main_soc = { 788 .num_ports = ARRAY_SIZE(tegra186_main_ports), 789 .ports = tegra186_main_ports, 790 .name = "tegra186-gpio", 791 .instance = 0, 792}; 793 794#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 795 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 796 .name = #_name, \ 797 .bank = _bank, \ 798 .port = _port, \ 799 .pins = _pins, \ 800 } 801 802static const struct tegra_gpio_port tegra186_aon_ports[] = { 803 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 804 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 805 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 806 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 807 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 808 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 809 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 810 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 811}; 812 813static const struct tegra_gpio_soc tegra186_aon_soc = { 814 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 815 .ports = tegra186_aon_ports, 816 .name = "tegra186-gpio-aon", 817 .instance = 1, 818}; 819 820#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 821 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 822 .name = #_name, \ 823 .bank = _bank, \ 824 .port = _port, \ 825 .pins = _pins, \ 826 } 827 828static const struct tegra_gpio_port tegra194_main_ports[] = { 829 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 830 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 831 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 832 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 833 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 834 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 835 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 836 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 837 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 838 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 839 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 840 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 841 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 842 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 843 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 844 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 845 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 846 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 847 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 848 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 849 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 850 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 851 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 852 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 853 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 854 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 855 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 856 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 857}; 858 859static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 860 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 861 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 862}; 863 864static const struct tegra_gpio_soc tegra194_main_soc = { 865 .num_ports = ARRAY_SIZE(tegra194_main_ports), 866 .ports = tegra194_main_ports, 867 .name = "tegra194-gpio", 868 .instance = 0, 869 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 870 .pin_ranges = tegra194_main_pin_ranges, 871 .pinmux = "nvidia,tegra194-pinmux", 872}; 873 874#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 875 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 876 .name = #_name, \ 877 .bank = _bank, \ 878 .port = _port, \ 879 .pins = _pins, \ 880 } 881 882static const struct tegra_gpio_port tegra194_aon_ports[] = { 883 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 884 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 885 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 886 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 887 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 888}; 889 890static const struct tegra_gpio_soc tegra194_aon_soc = { 891 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 892 .ports = tegra194_aon_ports, 893 .name = "tegra194-gpio-aon", 894 .instance = 1, 895}; 896 897static const struct of_device_id tegra186_gpio_of_match[] = { 898 { 899 .compatible = "nvidia,tegra186-gpio", 900 .data = &tegra186_main_soc 901 }, { 902 .compatible = "nvidia,tegra186-gpio-aon", 903 .data = &tegra186_aon_soc 904 }, { 905 .compatible = "nvidia,tegra194-gpio", 906 .data = &tegra194_main_soc 907 }, { 908 .compatible = "nvidia,tegra194-gpio-aon", 909 .data = &tegra194_aon_soc 910 }, { 911 /* sentinel */ 912 } 913}; 914MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 915 916static struct platform_driver tegra186_gpio_driver = { 917 .driver = { 918 .name = "tegra186-gpio", 919 .of_match_table = tegra186_gpio_of_match, 920 }, 921 .probe = tegra186_gpio_probe, 922 .remove = tegra186_gpio_remove, 923}; 924module_platform_driver(tegra186_gpio_driver); 925 926MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 927MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 928MODULE_LICENSE("GPL v2"); 929