1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/syscore_ops.h>
22#include <linux/gpio/driver.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/bug.h>
26
27enum mxc_gpio_hwtype {
28	IMX1_GPIO,	/* runs on i.mx1 */
29	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
30	IMX31_GPIO,	/* runs on i.mx31 */
31	IMX35_GPIO,	/* runs on all other i.mx */
32};
33
34/* device type dependent stuff */
35struct mxc_gpio_hwdata {
36	unsigned dr_reg;
37	unsigned gdir_reg;
38	unsigned psr_reg;
39	unsigned icr1_reg;
40	unsigned icr2_reg;
41	unsigned imr_reg;
42	unsigned isr_reg;
43	int edge_sel_reg;
44	unsigned low_level;
45	unsigned high_level;
46	unsigned rise_edge;
47	unsigned fall_edge;
48};
49
50struct mxc_gpio_reg_saved {
51	u32 icr1;
52	u32 icr2;
53	u32 imr;
54	u32 gdir;
55	u32 edge_sel;
56	u32 dr;
57};
58
59struct mxc_gpio_port {
60	struct list_head node;
61	void __iomem *base;
62	struct clk *clk;
63	int irq;
64	int irq_high;
65	struct irq_domain *domain;
66	struct gpio_chip gc;
67	struct device *dev;
68	u32 both_edges;
69	struct mxc_gpio_reg_saved gpio_saved_reg;
70	bool power_off;
71};
72
73static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
74	.dr_reg		= 0x1c,
75	.gdir_reg	= 0x00,
76	.psr_reg	= 0x24,
77	.icr1_reg	= 0x28,
78	.icr2_reg	= 0x2c,
79	.imr_reg	= 0x30,
80	.isr_reg	= 0x34,
81	.edge_sel_reg	= -EINVAL,
82	.low_level	= 0x03,
83	.high_level	= 0x02,
84	.rise_edge	= 0x00,
85	.fall_edge	= 0x01,
86};
87
88static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
89	.dr_reg		= 0x00,
90	.gdir_reg	= 0x04,
91	.psr_reg	= 0x08,
92	.icr1_reg	= 0x0c,
93	.icr2_reg	= 0x10,
94	.imr_reg	= 0x14,
95	.isr_reg	= 0x18,
96	.edge_sel_reg	= -EINVAL,
97	.low_level	= 0x00,
98	.high_level	= 0x01,
99	.rise_edge	= 0x02,
100	.fall_edge	= 0x03,
101};
102
103static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
104	.dr_reg		= 0x00,
105	.gdir_reg	= 0x04,
106	.psr_reg	= 0x08,
107	.icr1_reg	= 0x0c,
108	.icr2_reg	= 0x10,
109	.imr_reg	= 0x14,
110	.isr_reg	= 0x18,
111	.edge_sel_reg	= 0x1c,
112	.low_level	= 0x00,
113	.high_level	= 0x01,
114	.rise_edge	= 0x02,
115	.fall_edge	= 0x03,
116};
117
118static enum mxc_gpio_hwtype mxc_gpio_hwtype;
119static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
120
121#define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
122#define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
123#define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
124#define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
125#define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
126#define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
127#define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)
128#define GPIO_EDGE_SEL		(mxc_gpio_hwdata->edge_sel_reg)
129
130#define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
131#define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
132#define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
133#define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
134#define GPIO_INT_BOTH_EDGES	0x4
135
136static const struct platform_device_id mxc_gpio_devtype[] = {
137	{
138		.name = "imx1-gpio",
139		.driver_data = IMX1_GPIO,
140	}, {
141		.name = "imx21-gpio",
142		.driver_data = IMX21_GPIO,
143	}, {
144		.name = "imx31-gpio",
145		.driver_data = IMX31_GPIO,
146	}, {
147		.name = "imx35-gpio",
148		.driver_data = IMX35_GPIO,
149	}, {
150		/* sentinel */
151	}
152};
153
154static const struct of_device_id mxc_gpio_dt_ids[] = {
155	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
156	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
157	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
158	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
159	{ .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
160	{ /* sentinel */ }
161};
162MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
163
164/*
165 * MX2 has one interrupt *for all* gpio ports. The list is used
166 * to save the references to all ports, so that mx2_gpio_irq_handler
167 * can walk through all interrupt status registers.
168 */
169static LIST_HEAD(mxc_gpio_ports);
170
171/* Note: This driver assumes 32 GPIOs are handled in one register */
172
173static int gpio_set_irq_type(struct irq_data *d, u32 type)
174{
175	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
176	struct mxc_gpio_port *port = gc->private;
177	u32 bit, val;
178	u32 gpio_idx = d->hwirq;
179	int edge;
180	void __iomem *reg = port->base;
181
182	port->both_edges &= ~(1 << gpio_idx);
183	switch (type) {
184	case IRQ_TYPE_EDGE_RISING:
185		edge = GPIO_INT_RISE_EDGE;
186		break;
187	case IRQ_TYPE_EDGE_FALLING:
188		edge = GPIO_INT_FALL_EDGE;
189		break;
190	case IRQ_TYPE_EDGE_BOTH:
191		if (GPIO_EDGE_SEL >= 0) {
192			edge = GPIO_INT_BOTH_EDGES;
193		} else {
194			val = port->gc.get(&port->gc, gpio_idx);
195			if (val) {
196				edge = GPIO_INT_LOW_LEV;
197				pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
198			} else {
199				edge = GPIO_INT_HIGH_LEV;
200				pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
201			}
202			port->both_edges |= 1 << gpio_idx;
203		}
204		break;
205	case IRQ_TYPE_LEVEL_LOW:
206		edge = GPIO_INT_LOW_LEV;
207		break;
208	case IRQ_TYPE_LEVEL_HIGH:
209		edge = GPIO_INT_HIGH_LEV;
210		break;
211	default:
212		return -EINVAL;
213	}
214
215	if (GPIO_EDGE_SEL >= 0) {
216		val = readl(port->base + GPIO_EDGE_SEL);
217		if (edge == GPIO_INT_BOTH_EDGES)
218			writel(val | (1 << gpio_idx),
219				port->base + GPIO_EDGE_SEL);
220		else
221			writel(val & ~(1 << gpio_idx),
222				port->base + GPIO_EDGE_SEL);
223	}
224
225	if (edge != GPIO_INT_BOTH_EDGES) {
226		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
227		bit = gpio_idx & 0xf;
228		val = readl(reg) & ~(0x3 << (bit << 1));
229		writel(val | (edge << (bit << 1)), reg);
230	}
231
232	writel(1 << gpio_idx, port->base + GPIO_ISR);
233
234	return port->gc.direction_input(&port->gc, gpio_idx);
235}
236
237static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
238{
239	void __iomem *reg = port->base;
240	u32 bit, val;
241	int edge;
242
243	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
244	bit = gpio & 0xf;
245	val = readl(reg);
246	edge = (val >> (bit << 1)) & 3;
247	val &= ~(0x3 << (bit << 1));
248	if (edge == GPIO_INT_HIGH_LEV) {
249		edge = GPIO_INT_LOW_LEV;
250		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
251	} else if (edge == GPIO_INT_LOW_LEV) {
252		edge = GPIO_INT_HIGH_LEV;
253		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
254	} else {
255		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
256		       gpio, edge);
257		return;
258	}
259	writel(val | (edge << (bit << 1)), reg);
260}
261
262/* handle 32 interrupts in one status register */
263static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
264{
265	while (irq_stat != 0) {
266		int irqoffset = fls(irq_stat) - 1;
267
268		if (port->both_edges & (1 << irqoffset))
269			mxc_flip_edge(port, irqoffset);
270
271		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
272
273		irq_stat &= ~(1 << irqoffset);
274	}
275}
276
277/* MX1 and MX3 has one interrupt *per* gpio port */
278static void mx3_gpio_irq_handler(struct irq_desc *desc)
279{
280	u32 irq_stat;
281	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
282	struct irq_chip *chip = irq_desc_get_chip(desc);
283
284	chained_irq_enter(chip, desc);
285
286	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
287
288	mxc_gpio_irq_handler(port, irq_stat);
289
290	chained_irq_exit(chip, desc);
291}
292
293/* MX2 has one interrupt *for all* gpio ports */
294static void mx2_gpio_irq_handler(struct irq_desc *desc)
295{
296	u32 irq_msk, irq_stat;
297	struct mxc_gpio_port *port;
298	struct irq_chip *chip = irq_desc_get_chip(desc);
299
300	chained_irq_enter(chip, desc);
301
302	/* walk through all interrupt status registers */
303	list_for_each_entry(port, &mxc_gpio_ports, node) {
304		irq_msk = readl(port->base + GPIO_IMR);
305		if (!irq_msk)
306			continue;
307
308		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
309		if (irq_stat)
310			mxc_gpio_irq_handler(port, irq_stat);
311	}
312	chained_irq_exit(chip, desc);
313}
314
315/*
316 * Set interrupt number "irq" in the GPIO as a wake-up source.
317 * While system is running, all registered GPIO interrupts need to have
318 * wake-up enabled. When system is suspended, only selected GPIO interrupts
319 * need to have wake-up enabled.
320 * @param  irq          interrupt source number
321 * @param  enable       enable as wake-up if equal to non-zero
322 * @return       This function returns 0 on success.
323 */
324static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
325{
326	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
327	struct mxc_gpio_port *port = gc->private;
328	u32 gpio_idx = d->hwirq;
329	int ret;
330
331	if (enable) {
332		if (port->irq_high && (gpio_idx >= 16))
333			ret = enable_irq_wake(port->irq_high);
334		else
335			ret = enable_irq_wake(port->irq);
336	} else {
337		if (port->irq_high && (gpio_idx >= 16))
338			ret = disable_irq_wake(port->irq_high);
339		else
340			ret = disable_irq_wake(port->irq);
341	}
342
343	return ret;
344}
345
346static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
347{
348	struct irq_chip_generic *gc;
349	struct irq_chip_type *ct;
350	int rv;
351
352	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
353					 port->base, handle_level_irq);
354	if (!gc)
355		return -ENOMEM;
356	gc->private = port;
357
358	ct = gc->chip_types;
359	ct->chip.irq_ack = irq_gc_ack_set_bit;
360	ct->chip.irq_mask = irq_gc_mask_clr_bit;
361	ct->chip.irq_unmask = irq_gc_mask_set_bit;
362	ct->chip.irq_set_type = gpio_set_irq_type;
363	ct->chip.irq_set_wake = gpio_set_wake_irq;
364	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
365	ct->regs.ack = GPIO_ISR;
366	ct->regs.mask = GPIO_IMR;
367
368	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
369					 IRQ_GC_INIT_NESTED_LOCK,
370					 IRQ_NOREQUEST, 0);
371
372	return rv;
373}
374
375static void mxc_gpio_get_hw(struct platform_device *pdev)
376{
377	const struct of_device_id *of_id =
378			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
379	enum mxc_gpio_hwtype hwtype;
380
381	if (of_id)
382		pdev->id_entry = of_id->data;
383	hwtype = pdev->id_entry->driver_data;
384
385	if (mxc_gpio_hwtype) {
386		/*
387		 * The driver works with a reasonable presupposition,
388		 * that is all gpio ports must be the same type when
389		 * running on one soc.
390		 */
391		BUG_ON(mxc_gpio_hwtype != hwtype);
392		return;
393	}
394
395	if (hwtype == IMX35_GPIO)
396		mxc_gpio_hwdata = &imx35_gpio_hwdata;
397	else if (hwtype == IMX31_GPIO)
398		mxc_gpio_hwdata = &imx31_gpio_hwdata;
399	else
400		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
401
402	mxc_gpio_hwtype = hwtype;
403}
404
405static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
406{
407	struct mxc_gpio_port *port = gpiochip_get_data(gc);
408
409	return irq_find_mapping(port->domain, offset);
410}
411
412static int mxc_gpio_probe(struct platform_device *pdev)
413{
414	struct device_node *np = pdev->dev.of_node;
415	struct mxc_gpio_port *port;
416	int irq_count;
417	int irq_base;
418	int err;
419
420	mxc_gpio_get_hw(pdev);
421
422	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
423	if (!port)
424		return -ENOMEM;
425
426	port->dev = &pdev->dev;
427
428	port->base = devm_platform_ioremap_resource(pdev, 0);
429	if (IS_ERR(port->base))
430		return PTR_ERR(port->base);
431
432	irq_count = platform_irq_count(pdev);
433	if (irq_count < 0)
434		return irq_count;
435
436	if (irq_count > 1) {
437		port->irq_high = platform_get_irq(pdev, 1);
438		if (port->irq_high < 0)
439			port->irq_high = 0;
440	}
441
442	port->irq = platform_get_irq(pdev, 0);
443	if (port->irq < 0)
444		return port->irq;
445
446	/* the controller clock is optional */
447	port->clk = devm_clk_get_optional(&pdev->dev, NULL);
448	if (IS_ERR(port->clk))
449		return PTR_ERR(port->clk);
450
451	err = clk_prepare_enable(port->clk);
452	if (err) {
453		dev_err(&pdev->dev, "Unable to enable clock.\n");
454		return err;
455	}
456
457	if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
458		port->power_off = true;
459
460	/* disable the interrupt and clear the status */
461	writel(0, port->base + GPIO_IMR);
462	writel(~0, port->base + GPIO_ISR);
463
464	if (mxc_gpio_hwtype == IMX21_GPIO) {
465		/*
466		 * Setup one handler for all GPIO interrupts. Actually setting
467		 * the handler is needed only once, but doing it for every port
468		 * is more robust and easier.
469		 */
470		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
471	} else {
472		/* setup one handler for each entry */
473		irq_set_chained_handler_and_data(port->irq,
474						 mx3_gpio_irq_handler, port);
475		if (port->irq_high > 0)
476			/* setup handler for GPIO 16 to 31 */
477			irq_set_chained_handler_and_data(port->irq_high,
478							 mx3_gpio_irq_handler,
479							 port);
480	}
481
482	err = bgpio_init(&port->gc, &pdev->dev, 4,
483			 port->base + GPIO_PSR,
484			 port->base + GPIO_DR, NULL,
485			 port->base + GPIO_GDIR, NULL,
486			 BGPIOF_READ_OUTPUT_REG_SET);
487	if (err)
488		goto out_bgio;
489
490	port->gc.request = gpiochip_generic_request;
491	port->gc.free = gpiochip_generic_free;
492	port->gc.to_irq = mxc_gpio_to_irq;
493	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
494					     pdev->id * 32;
495
496	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
497	if (err)
498		goto out_bgio;
499
500	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
501	if (irq_base < 0) {
502		err = irq_base;
503		goto out_bgio;
504	}
505
506	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
507					     &irq_domain_simple_ops, NULL);
508	if (!port->domain) {
509		err = -ENODEV;
510		goto out_bgio;
511	}
512
513	/* gpio-mxc can be a generic irq chip */
514	err = mxc_gpio_init_gc(port, irq_base);
515	if (err < 0)
516		goto out_irqdomain_remove;
517
518	list_add_tail(&port->node, &mxc_gpio_ports);
519
520	platform_set_drvdata(pdev, port);
521
522	return 0;
523
524out_irqdomain_remove:
525	irq_domain_remove(port->domain);
526out_bgio:
527	clk_disable_unprepare(port->clk);
528	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
529	return err;
530}
531
532static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
533{
534	if (!port->power_off)
535		return;
536
537	port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
538	port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
539	port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
540	port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
541	port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
542	port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
543}
544
545static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
546{
547	if (!port->power_off)
548		return;
549
550	writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
551	writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
552	writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
553	writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
554	writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
555	writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
556}
557
558static int mxc_gpio_syscore_suspend(void)
559{
560	struct mxc_gpio_port *port;
561
562	/* walk through all ports */
563	list_for_each_entry(port, &mxc_gpio_ports, node) {
564		mxc_gpio_save_regs(port);
565		clk_disable_unprepare(port->clk);
566	}
567
568	return 0;
569}
570
571static void mxc_gpio_syscore_resume(void)
572{
573	struct mxc_gpio_port *port;
574	int ret;
575
576	/* walk through all ports */
577	list_for_each_entry(port, &mxc_gpio_ports, node) {
578		ret = clk_prepare_enable(port->clk);
579		if (ret) {
580			pr_err("mxc: failed to enable gpio clock %d\n", ret);
581			return;
582		}
583		mxc_gpio_restore_regs(port);
584	}
585}
586
587static struct syscore_ops mxc_gpio_syscore_ops = {
588	.suspend = mxc_gpio_syscore_suspend,
589	.resume = mxc_gpio_syscore_resume,
590};
591
592static struct platform_driver mxc_gpio_driver = {
593	.driver		= {
594		.name	= "gpio-mxc",
595		.of_match_table = mxc_gpio_dt_ids,
596		.suppress_bind_attrs = true,
597	},
598	.probe		= mxc_gpio_probe,
599	.id_table	= mxc_gpio_devtype,
600};
601
602static int __init gpio_mxc_init(void)
603{
604	register_syscore_ops(&mxc_gpio_syscore_ops);
605
606	return platform_driver_register(&mxc_gpio_driver);
607}
608subsys_initcall(gpio_mxc_init);
609
610MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
611MODULE_DESCRIPTION("i.MX GPIO Driver");
612MODULE_LICENSE("GPL");
613