1/* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36#include <linux/bitops.h> 37#include <linux/clk.h> 38#include <linux/err.h> 39#include <linux/gpio/driver.h> 40#include <linux/gpio/consumer.h> 41#include <linux/gpio/machine.h> 42#include <linux/init.h> 43#include <linux/io.h> 44#include <linux/irq.h> 45#include <linux/irqchip/chained_irq.h> 46#include <linux/irqdomain.h> 47#include <linux/mfd/syscon.h> 48#include <linux/of_device.h> 49#include <linux/pinctrl/consumer.h> 50#include <linux/platform_device.h> 51#include <linux/pwm.h> 52#include <linux/regmap.h> 53#include <linux/slab.h> 54 55/* 56 * GPIO unit register offsets. 57 */ 58#define GPIO_OUT_OFF 0x0000 59#define GPIO_IO_CONF_OFF 0x0004 60#define GPIO_BLINK_EN_OFF 0x0008 61#define GPIO_IN_POL_OFF 0x000c 62#define GPIO_DATA_IN_OFF 0x0010 63#define GPIO_EDGE_CAUSE_OFF 0x0014 64#define GPIO_EDGE_MASK_OFF 0x0018 65#define GPIO_LEVEL_MASK_OFF 0x001c 66#define GPIO_BLINK_CNT_SELECT_OFF 0x0020 67 68/* 69 * PWM register offsets. 70 */ 71#define PWM_BLINK_ON_DURATION_OFF 0x0 72#define PWM_BLINK_OFF_DURATION_OFF 0x4 73 74 75/* The MV78200 has per-CPU registers for edge mask and level mask */ 76#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 77#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 78 79/* 80 * The Armada XP has per-CPU registers for interrupt cause, interrupt 81 * mask and interrupt level mask. Those are relative to the 82 * percpu_membase. 83 */ 84#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 85#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 86#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 87 88#define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 89#define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 90#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 91#define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 92 93#define MVEBU_MAX_GPIO_PER_BANK 32 94 95struct mvebu_pwm { 96 void __iomem *membase; 97 unsigned long clk_rate; 98 struct gpio_desc *gpiod; 99 struct pwm_chip chip; 100 spinlock_t lock; 101 struct mvebu_gpio_chip *mvchip; 102 103 /* Used to preserve GPIO/PWM registers across suspend/resume */ 104 u32 blink_select; 105 u32 blink_on_duration; 106 u32 blink_off_duration; 107}; 108 109struct mvebu_gpio_chip { 110 struct gpio_chip chip; 111 struct regmap *regs; 112 u32 offset; 113 struct regmap *percpu_regs; 114 int irqbase; 115 struct irq_domain *domain; 116 int soc_variant; 117 118 /* Used for PWM support */ 119 struct clk *clk; 120 struct mvebu_pwm *mvpwm; 121 122 /* Used to preserve GPIO registers across suspend/resume */ 123 u32 out_reg; 124 u32 io_conf_reg; 125 u32 blink_en_reg; 126 u32 in_pol_reg; 127 u32 edge_mask_regs[4]; 128 u32 level_mask_regs[4]; 129}; 130 131/* 132 * Functions returning addresses of individual registers for a given 133 * GPIO controller. 134 */ 135 136static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 137 struct regmap **map, unsigned int *offset) 138{ 139 int cpu; 140 141 switch (mvchip->soc_variant) { 142 case MVEBU_GPIO_SOC_VARIANT_ORION: 143 case MVEBU_GPIO_SOC_VARIANT_MV78200: 144 case MVEBU_GPIO_SOC_VARIANT_A8K: 145 *map = mvchip->regs; 146 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 147 break; 148 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 149 cpu = smp_processor_id(); 150 *map = mvchip->percpu_regs; 151 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 152 break; 153 default: 154 BUG(); 155 } 156} 157 158static u32 159mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 160{ 161 struct regmap *map; 162 unsigned int offset; 163 u32 val; 164 165 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 166 regmap_read(map, offset, &val); 167 168 return val; 169} 170 171static void 172mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 173{ 174 struct regmap *map; 175 unsigned int offset; 176 177 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 178 regmap_write(map, offset, val); 179} 180 181static inline void 182mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 183 struct regmap **map, unsigned int *offset) 184{ 185 int cpu; 186 187 switch (mvchip->soc_variant) { 188 case MVEBU_GPIO_SOC_VARIANT_ORION: 189 case MVEBU_GPIO_SOC_VARIANT_A8K: 190 *map = mvchip->regs; 191 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 192 break; 193 case MVEBU_GPIO_SOC_VARIANT_MV78200: 194 cpu = smp_processor_id(); 195 *map = mvchip->regs; 196 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 197 break; 198 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 199 cpu = smp_processor_id(); 200 *map = mvchip->percpu_regs; 201 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 202 break; 203 default: 204 BUG(); 205 } 206} 207 208static u32 209mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 210{ 211 struct regmap *map; 212 unsigned int offset; 213 u32 val; 214 215 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 216 regmap_read(map, offset, &val); 217 218 return val; 219} 220 221static void 222mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 223{ 224 struct regmap *map; 225 unsigned int offset; 226 227 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 228 regmap_write(map, offset, val); 229} 230 231static void 232mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 233 struct regmap **map, unsigned int *offset) 234{ 235 int cpu; 236 237 switch (mvchip->soc_variant) { 238 case MVEBU_GPIO_SOC_VARIANT_ORION: 239 case MVEBU_GPIO_SOC_VARIANT_A8K: 240 *map = mvchip->regs; 241 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 242 break; 243 case MVEBU_GPIO_SOC_VARIANT_MV78200: 244 cpu = smp_processor_id(); 245 *map = mvchip->regs; 246 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 247 break; 248 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 249 cpu = smp_processor_id(); 250 *map = mvchip->percpu_regs; 251 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 252 break; 253 default: 254 BUG(); 255 } 256} 257 258static u32 259mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 260{ 261 struct regmap *map; 262 unsigned int offset; 263 u32 val; 264 265 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 266 regmap_read(map, offset, &val); 267 268 return val; 269} 270 271static void 272mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 273{ 274 struct regmap *map; 275 unsigned int offset; 276 277 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 278 regmap_write(map, offset, val); 279} 280 281/* 282 * Functions returning addresses of individual registers for a given 283 * PWM controller. 284 */ 285static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 286{ 287 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; 288} 289 290static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 291{ 292 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; 293} 294 295/* 296 * Functions implementing the gpio_chip methods 297 */ 298static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 299{ 300 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 301 302 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 303 BIT(pin), value ? BIT(pin) : 0); 304} 305 306static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 307{ 308 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 309 u32 u; 310 311 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 312 313 if (u & BIT(pin)) { 314 u32 data_in, in_pol; 315 316 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 317 &data_in); 318 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 319 &in_pol); 320 u = data_in ^ in_pol; 321 } else { 322 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 323 } 324 325 return (u >> pin) & 1; 326} 327 328static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 329 int value) 330{ 331 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 332 333 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 334 BIT(pin), value ? BIT(pin) : 0); 335} 336 337static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 338{ 339 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 340 int ret; 341 342 /* 343 * Check with the pinctrl driver whether this pin is usable as 344 * an input GPIO 345 */ 346 ret = pinctrl_gpio_direction_input(chip->base + pin); 347 if (ret) 348 return ret; 349 350 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 351 BIT(pin), BIT(pin)); 352 353 return 0; 354} 355 356static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 357 int value) 358{ 359 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 360 int ret; 361 362 /* 363 * Check with the pinctrl driver whether this pin is usable as 364 * an output GPIO 365 */ 366 ret = pinctrl_gpio_direction_output(chip->base + pin); 367 if (ret) 368 return ret; 369 370 mvebu_gpio_blink(chip, pin, 0); 371 mvebu_gpio_set(chip, pin, value); 372 373 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 374 BIT(pin), 0); 375 376 return 0; 377} 378 379static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 380{ 381 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 382 u32 u; 383 384 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 385 386 if (u & BIT(pin)) 387 return GPIO_LINE_DIRECTION_IN; 388 389 return GPIO_LINE_DIRECTION_OUT; 390} 391 392static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 393{ 394 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 395 396 return irq_create_mapping(mvchip->domain, pin); 397} 398 399/* 400 * Functions implementing the irq_chip methods 401 */ 402static void mvebu_gpio_irq_ack(struct irq_data *d) 403{ 404 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 405 struct mvebu_gpio_chip *mvchip = gc->private; 406 u32 mask = d->mask; 407 408 irq_gc_lock(gc); 409 mvebu_gpio_write_edge_cause(mvchip, ~mask); 410 irq_gc_unlock(gc); 411} 412 413static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 414{ 415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 416 struct mvebu_gpio_chip *mvchip = gc->private; 417 struct irq_chip_type *ct = irq_data_get_chip_type(d); 418 u32 mask = d->mask; 419 420 irq_gc_lock(gc); 421 ct->mask_cache_priv &= ~mask; 422 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 423 irq_gc_unlock(gc); 424} 425 426static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 427{ 428 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 429 struct mvebu_gpio_chip *mvchip = gc->private; 430 struct irq_chip_type *ct = irq_data_get_chip_type(d); 431 u32 mask = d->mask; 432 433 irq_gc_lock(gc); 434 mvebu_gpio_write_edge_cause(mvchip, ~mask); 435 ct->mask_cache_priv |= mask; 436 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 437 irq_gc_unlock(gc); 438} 439 440static void mvebu_gpio_level_irq_mask(struct irq_data *d) 441{ 442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 443 struct mvebu_gpio_chip *mvchip = gc->private; 444 struct irq_chip_type *ct = irq_data_get_chip_type(d); 445 u32 mask = d->mask; 446 447 irq_gc_lock(gc); 448 ct->mask_cache_priv &= ~mask; 449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 450 irq_gc_unlock(gc); 451} 452 453static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 454{ 455 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 456 struct mvebu_gpio_chip *mvchip = gc->private; 457 struct irq_chip_type *ct = irq_data_get_chip_type(d); 458 u32 mask = d->mask; 459 460 irq_gc_lock(gc); 461 ct->mask_cache_priv |= mask; 462 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 463 irq_gc_unlock(gc); 464} 465 466/***************************************************************************** 467 * MVEBU GPIO IRQ 468 * 469 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 470 * value of the line or the opposite value. 471 * 472 * Level IRQ handlers: DATA_IN is used directly as cause register. 473 * Interrupt are masked by LEVEL_MASK registers. 474 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 475 * Interrupt are masked by EDGE_MASK registers. 476 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 477 * the polarity to catch the next line transaction. 478 * This is a race condition that might not perfectly 479 * work on some use cases. 480 * 481 * Every eight GPIO lines are grouped (OR'ed) before going up to main 482 * cause register. 483 * 484 * EDGE cause mask 485 * data-in /--------| |-----| |----\ 486 * -----| |----- ---- to main cause reg 487 * X \----------------| |----/ 488 * polarity LEVEL mask 489 * 490 ****************************************************************************/ 491 492static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 493{ 494 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 495 struct irq_chip_type *ct = irq_data_get_chip_type(d); 496 struct mvebu_gpio_chip *mvchip = gc->private; 497 int pin; 498 u32 u; 499 500 pin = d->hwirq; 501 502 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 503 if ((u & BIT(pin)) == 0) 504 return -EINVAL; 505 506 type &= IRQ_TYPE_SENSE_MASK; 507 if (type == IRQ_TYPE_NONE) 508 return -EINVAL; 509 510 /* Check if we need to change chip and handler */ 511 if (!(ct->type & type)) 512 if (irq_setup_alt_chip(d, type)) 513 return -EINVAL; 514 515 /* 516 * Configure interrupt polarity. 517 */ 518 switch (type) { 519 case IRQ_TYPE_EDGE_RISING: 520 case IRQ_TYPE_LEVEL_HIGH: 521 regmap_update_bits(mvchip->regs, 522 GPIO_IN_POL_OFF + mvchip->offset, 523 BIT(pin), 0); 524 break; 525 case IRQ_TYPE_EDGE_FALLING: 526 case IRQ_TYPE_LEVEL_LOW: 527 regmap_update_bits(mvchip->regs, 528 GPIO_IN_POL_OFF + mvchip->offset, 529 BIT(pin), BIT(pin)); 530 break; 531 case IRQ_TYPE_EDGE_BOTH: { 532 u32 data_in, in_pol, val; 533 534 regmap_read(mvchip->regs, 535 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 536 regmap_read(mvchip->regs, 537 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 538 539 /* 540 * set initial polarity based on current input level 541 */ 542 if ((data_in ^ in_pol) & BIT(pin)) 543 val = BIT(pin); /* falling */ 544 else 545 val = 0; /* raising */ 546 547 regmap_update_bits(mvchip->regs, 548 GPIO_IN_POL_OFF + mvchip->offset, 549 BIT(pin), val); 550 break; 551 } 552 } 553 return 0; 554} 555 556static void mvebu_gpio_irq_handler(struct irq_desc *desc) 557{ 558 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 559 struct irq_chip *chip = irq_desc_get_chip(desc); 560 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 561 int i; 562 563 if (mvchip == NULL) 564 return; 565 566 chained_irq_enter(chip, desc); 567 568 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 569 level_mask = mvebu_gpio_read_level_mask(mvchip); 570 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 571 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 572 573 cause = (data_in & level_mask) | (edge_cause & edge_mask); 574 575 for (i = 0; i < mvchip->chip.ngpio; i++) { 576 int irq; 577 578 irq = irq_find_mapping(mvchip->domain, i); 579 580 if (!(cause & BIT(i))) 581 continue; 582 583 type = irq_get_trigger_type(irq); 584 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 585 /* Swap polarity (race with GPIO line) */ 586 u32 polarity; 587 588 regmap_read(mvchip->regs, 589 GPIO_IN_POL_OFF + mvchip->offset, 590 &polarity); 591 polarity ^= BIT(i); 592 regmap_write(mvchip->regs, 593 GPIO_IN_POL_OFF + mvchip->offset, 594 polarity); 595 } 596 597 generic_handle_irq(irq); 598 } 599 600 chained_irq_exit(chip, desc); 601} 602 603/* 604 * Functions implementing the pwm_chip methods 605 */ 606static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 607{ 608 return container_of(chip, struct mvebu_pwm, chip); 609} 610 611static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 612{ 613 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 614 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 615 struct gpio_desc *desc; 616 unsigned long flags; 617 int ret = 0; 618 619 spin_lock_irqsave(&mvpwm->lock, flags); 620 621 if (mvpwm->gpiod) { 622 ret = -EBUSY; 623 } else { 624 desc = gpiochip_request_own_desc(&mvchip->chip, 625 pwm->hwpwm, "mvebu-pwm", 626 GPIO_ACTIVE_HIGH, 627 GPIOD_OUT_LOW); 628 if (IS_ERR(desc)) { 629 ret = PTR_ERR(desc); 630 goto out; 631 } 632 633 mvpwm->gpiod = desc; 634 } 635out: 636 spin_unlock_irqrestore(&mvpwm->lock, flags); 637 return ret; 638} 639 640static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 641{ 642 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 643 unsigned long flags; 644 645 spin_lock_irqsave(&mvpwm->lock, flags); 646 gpiochip_free_own_desc(mvpwm->gpiod); 647 mvpwm->gpiod = NULL; 648 spin_unlock_irqrestore(&mvpwm->lock, flags); 649} 650 651static void mvebu_pwm_get_state(struct pwm_chip *chip, 652 struct pwm_device *pwm, 653 struct pwm_state *state) { 654 655 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 656 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 657 unsigned long long val; 658 unsigned long flags; 659 u32 u; 660 661 spin_lock_irqsave(&mvpwm->lock, flags); 662 663 u = readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 664 val = (unsigned long long) u * NSEC_PER_SEC; 665 do_div(val, mvpwm->clk_rate); 666 if (val > UINT_MAX) 667 state->duty_cycle = UINT_MAX; 668 else if (val) 669 state->duty_cycle = val; 670 else 671 state->duty_cycle = 1; 672 673 val = (unsigned long long) u; /* on duration */ 674 /* period = on + off duration */ 675 val += readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 676 val *= NSEC_PER_SEC; 677 do_div(val, mvpwm->clk_rate); 678 if (val > UINT_MAX) 679 state->period = UINT_MAX; 680 else if (val) 681 state->period = val; 682 else 683 state->period = 1; 684 685 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 686 if (u) 687 state->enabled = true; 688 else 689 state->enabled = false; 690 691 spin_unlock_irqrestore(&mvpwm->lock, flags); 692} 693 694static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 695 const struct pwm_state *state) 696{ 697 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 698 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 699 unsigned long long val; 700 unsigned long flags; 701 unsigned int on, off; 702 703 if (state->polarity != PWM_POLARITY_NORMAL) 704 return -EINVAL; 705 706 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 707 do_div(val, NSEC_PER_SEC); 708 if (val > UINT_MAX) 709 return -EINVAL; 710 if (val) 711 on = val; 712 else 713 on = 1; 714 715 val = (unsigned long long) mvpwm->clk_rate * 716 (state->period - state->duty_cycle); 717 do_div(val, NSEC_PER_SEC); 718 if (val > UINT_MAX) 719 return -EINVAL; 720 if (val) 721 off = val; 722 else 723 off = 1; 724 725 spin_lock_irqsave(&mvpwm->lock, flags); 726 727 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm)); 728 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm)); 729 if (state->enabled) 730 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 731 else 732 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 733 734 spin_unlock_irqrestore(&mvpwm->lock, flags); 735 736 return 0; 737} 738 739static const struct pwm_ops mvebu_pwm_ops = { 740 .request = mvebu_pwm_request, 741 .free = mvebu_pwm_free, 742 .get_state = mvebu_pwm_get_state, 743 .apply = mvebu_pwm_apply, 744 .owner = THIS_MODULE, 745}; 746 747static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 748{ 749 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 750 751 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 752 &mvpwm->blink_select); 753 mvpwm->blink_on_duration = 754 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 755 mvpwm->blink_off_duration = 756 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 757} 758 759static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 760{ 761 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 762 763 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 764 mvpwm->blink_select); 765 writel_relaxed(mvpwm->blink_on_duration, 766 mvebu_pwmreg_blink_on_duration(mvpwm)); 767 writel_relaxed(mvpwm->blink_off_duration, 768 mvebu_pwmreg_blink_off_duration(mvpwm)); 769} 770 771static int mvebu_pwm_probe(struct platform_device *pdev, 772 struct mvebu_gpio_chip *mvchip, 773 int id) 774{ 775 struct device *dev = &pdev->dev; 776 struct mvebu_pwm *mvpwm; 777 u32 set; 778 779 if (!of_device_is_compatible(mvchip->chip.of_node, 780 "marvell,armada-370-gpio")) 781 return 0; 782 783 /* 784 * There are only two sets of PWM configuration registers for 785 * all the GPIO lines on those SoCs which this driver reserves 786 * for the first two GPIO chips. So if the resource is missing 787 * we can't treat it as an error. 788 */ 789 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 790 return 0; 791 792 if (IS_ERR(mvchip->clk)) 793 return PTR_ERR(mvchip->clk); 794 795 /* 796 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 797 * with id 1. Don't allow further GPIO chips to be used for PWM. 798 */ 799 if (id == 0) 800 set = 0; 801 else if (id == 1) 802 set = U32_MAX; 803 else 804 return -EINVAL; 805 regmap_write(mvchip->regs, 806 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 807 808 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 809 if (!mvpwm) 810 return -ENOMEM; 811 mvchip->mvpwm = mvpwm; 812 mvpwm->mvchip = mvchip; 813 814 mvpwm->membase = devm_platform_ioremap_resource_byname(pdev, "pwm"); 815 if (IS_ERR(mvpwm->membase)) 816 return PTR_ERR(mvpwm->membase); 817 818 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 819 if (!mvpwm->clk_rate) { 820 dev_err(dev, "failed to get clock rate\n"); 821 return -EINVAL; 822 } 823 824 mvpwm->chip.dev = dev; 825 mvpwm->chip.ops = &mvebu_pwm_ops; 826 mvpwm->chip.npwm = mvchip->chip.ngpio; 827 /* 828 * There may already be some PWM allocated, so we can't force 829 * mvpwm->chip.base to a fixed point like mvchip->chip.base. 830 * So, we let pwmchip_add() do the numbering and take the next free 831 * region. 832 */ 833 mvpwm->chip.base = -1; 834 835 spin_lock_init(&mvpwm->lock); 836 837 return pwmchip_add(&mvpwm->chip); 838} 839 840#ifdef CONFIG_DEBUG_FS 841#include <linux/seq_file.h> 842 843static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 844{ 845 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 846 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 847 const char *label; 848 int i; 849 850 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 851 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 852 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 853 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 854 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 855 cause = mvebu_gpio_read_edge_cause(mvchip); 856 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 857 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 858 859 for_each_requested_gpio(chip, i, label) { 860 u32 msk; 861 bool is_out; 862 863 msk = BIT(i); 864 is_out = !(io_conf & msk); 865 866 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 867 868 if (is_out) { 869 seq_printf(s, " out %s %s\n", 870 out & msk ? "hi" : "lo", 871 blink & msk ? "(blink )" : ""); 872 continue; 873 } 874 875 seq_printf(s, " in %s (act %s) - IRQ", 876 (data_in ^ in_pol) & msk ? "hi" : "lo", 877 in_pol & msk ? "lo" : "hi"); 878 if (!((edg_msk | lvl_msk) & msk)) { 879 seq_puts(s, " disabled\n"); 880 continue; 881 } 882 if (edg_msk & msk) 883 seq_puts(s, " edge "); 884 if (lvl_msk & msk) 885 seq_puts(s, " level"); 886 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 887 } 888} 889#else 890#define mvebu_gpio_dbg_show NULL 891#endif 892 893static const struct of_device_id mvebu_gpio_of_match[] = { 894 { 895 .compatible = "marvell,orion-gpio", 896 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 897 }, 898 { 899 .compatible = "marvell,mv78200-gpio", 900 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 901 }, 902 { 903 .compatible = "marvell,armadaxp-gpio", 904 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 905 }, 906 { 907 .compatible = "marvell,armada-370-gpio", 908 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 909 }, 910 { 911 .compatible = "marvell,armada-8k-gpio", 912 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 913 }, 914 { 915 /* sentinel */ 916 }, 917}; 918 919static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 920{ 921 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 922 int i; 923 924 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 925 &mvchip->out_reg); 926 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 927 &mvchip->io_conf_reg); 928 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 929 &mvchip->blink_en_reg); 930 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 931 &mvchip->in_pol_reg); 932 933 switch (mvchip->soc_variant) { 934 case MVEBU_GPIO_SOC_VARIANT_ORION: 935 case MVEBU_GPIO_SOC_VARIANT_A8K: 936 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 937 &mvchip->edge_mask_regs[0]); 938 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 939 &mvchip->level_mask_regs[0]); 940 break; 941 case MVEBU_GPIO_SOC_VARIANT_MV78200: 942 for (i = 0; i < 2; i++) { 943 regmap_read(mvchip->regs, 944 GPIO_EDGE_MASK_MV78200_OFF(i), 945 &mvchip->edge_mask_regs[i]); 946 regmap_read(mvchip->regs, 947 GPIO_LEVEL_MASK_MV78200_OFF(i), 948 &mvchip->level_mask_regs[i]); 949 } 950 break; 951 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 952 for (i = 0; i < 4; i++) { 953 regmap_read(mvchip->regs, 954 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 955 &mvchip->edge_mask_regs[i]); 956 regmap_read(mvchip->regs, 957 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 958 &mvchip->level_mask_regs[i]); 959 } 960 break; 961 default: 962 BUG(); 963 } 964 965 if (IS_ENABLED(CONFIG_PWM)) 966 mvebu_pwm_suspend(mvchip); 967 968 return 0; 969} 970 971static int mvebu_gpio_resume(struct platform_device *pdev) 972{ 973 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 974 int i; 975 976 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 977 mvchip->out_reg); 978 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 979 mvchip->io_conf_reg); 980 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 981 mvchip->blink_en_reg); 982 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 983 mvchip->in_pol_reg); 984 985 switch (mvchip->soc_variant) { 986 case MVEBU_GPIO_SOC_VARIANT_ORION: 987 case MVEBU_GPIO_SOC_VARIANT_A8K: 988 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 989 mvchip->edge_mask_regs[0]); 990 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 991 mvchip->level_mask_regs[0]); 992 break; 993 case MVEBU_GPIO_SOC_VARIANT_MV78200: 994 for (i = 0; i < 2; i++) { 995 regmap_write(mvchip->regs, 996 GPIO_EDGE_MASK_MV78200_OFF(i), 997 mvchip->edge_mask_regs[i]); 998 regmap_write(mvchip->regs, 999 GPIO_LEVEL_MASK_MV78200_OFF(i), 1000 mvchip->level_mask_regs[i]); 1001 } 1002 break; 1003 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1004 for (i = 0; i < 4; i++) { 1005 regmap_write(mvchip->regs, 1006 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1007 mvchip->edge_mask_regs[i]); 1008 regmap_write(mvchip->regs, 1009 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1010 mvchip->level_mask_regs[i]); 1011 } 1012 break; 1013 default: 1014 BUG(); 1015 } 1016 1017 if (IS_ENABLED(CONFIG_PWM)) 1018 mvebu_pwm_resume(mvchip); 1019 1020 return 0; 1021} 1022 1023static const struct regmap_config mvebu_gpio_regmap_config = { 1024 .reg_bits = 32, 1025 .reg_stride = 4, 1026 .val_bits = 32, 1027 .fast_io = true, 1028}; 1029 1030static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1031 struct mvebu_gpio_chip *mvchip) 1032{ 1033 void __iomem *base; 1034 1035 base = devm_platform_ioremap_resource(pdev, 0); 1036 if (IS_ERR(base)) 1037 return PTR_ERR(base); 1038 1039 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1040 &mvebu_gpio_regmap_config); 1041 if (IS_ERR(mvchip->regs)) 1042 return PTR_ERR(mvchip->regs); 1043 1044 /* 1045 * For the legacy SoCs, the regmap directly maps to the GPIO 1046 * registers, so no offset is needed. 1047 */ 1048 mvchip->offset = 0; 1049 1050 /* 1051 * The Armada XP has a second range of registers for the 1052 * per-CPU registers 1053 */ 1054 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1055 base = devm_platform_ioremap_resource(pdev, 1); 1056 if (IS_ERR(base)) 1057 return PTR_ERR(base); 1058 1059 mvchip->percpu_regs = 1060 devm_regmap_init_mmio(&pdev->dev, base, 1061 &mvebu_gpio_regmap_config); 1062 if (IS_ERR(mvchip->percpu_regs)) 1063 return PTR_ERR(mvchip->percpu_regs); 1064 } 1065 1066 return 0; 1067} 1068 1069static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1070 struct mvebu_gpio_chip *mvchip) 1071{ 1072 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1073 if (IS_ERR(mvchip->regs)) 1074 return PTR_ERR(mvchip->regs); 1075 1076 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1077 return -EINVAL; 1078 1079 return 0; 1080} 1081 1082static int mvebu_gpio_probe(struct platform_device *pdev) 1083{ 1084 struct mvebu_gpio_chip *mvchip; 1085 const struct of_device_id *match; 1086 struct device_node *np = pdev->dev.of_node; 1087 struct irq_chip_generic *gc; 1088 struct irq_chip_type *ct; 1089 unsigned int ngpios; 1090 bool have_irqs; 1091 int soc_variant; 1092 int i, cpu, id; 1093 int err; 1094 1095 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 1096 if (match) 1097 soc_variant = (unsigned long) match->data; 1098 else 1099 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 1100 1101 /* Some gpio controllers do not provide irq support */ 1102 err = platform_irq_count(pdev); 1103 if (err < 0) 1104 return err; 1105 1106 have_irqs = err != 0; 1107 1108 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1109 GFP_KERNEL); 1110 if (!mvchip) 1111 return -ENOMEM; 1112 1113 platform_set_drvdata(pdev, mvchip); 1114 1115 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1116 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1117 return -ENODEV; 1118 } 1119 1120 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1121 if (id < 0) { 1122 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1123 return id; 1124 } 1125 1126 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1127 /* Not all SoCs require a clock.*/ 1128 if (!IS_ERR(mvchip->clk)) 1129 clk_prepare_enable(mvchip->clk); 1130 1131 mvchip->soc_variant = soc_variant; 1132 mvchip->chip.label = dev_name(&pdev->dev); 1133 mvchip->chip.parent = &pdev->dev; 1134 mvchip->chip.request = gpiochip_generic_request; 1135 mvchip->chip.free = gpiochip_generic_free; 1136 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1137 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1138 mvchip->chip.get = mvebu_gpio_get; 1139 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1140 mvchip->chip.set = mvebu_gpio_set; 1141 if (have_irqs) 1142 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1143 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1144 mvchip->chip.ngpio = ngpios; 1145 mvchip->chip.can_sleep = false; 1146 mvchip->chip.of_node = np; 1147 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1148 1149 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1150 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1151 else 1152 err = mvebu_gpio_probe_raw(pdev, mvchip); 1153 1154 if (err) 1155 return err; 1156 1157 /* 1158 * Mask and clear GPIO interrupts. 1159 */ 1160 switch (soc_variant) { 1161 case MVEBU_GPIO_SOC_VARIANT_ORION: 1162 case MVEBU_GPIO_SOC_VARIANT_A8K: 1163 regmap_write(mvchip->regs, 1164 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1165 regmap_write(mvchip->regs, 1166 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1167 regmap_write(mvchip->regs, 1168 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1169 break; 1170 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1171 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1172 for (cpu = 0; cpu < 2; cpu++) { 1173 regmap_write(mvchip->regs, 1174 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1175 regmap_write(mvchip->regs, 1176 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1177 } 1178 break; 1179 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1180 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1181 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1182 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1183 for (cpu = 0; cpu < 4; cpu++) { 1184 regmap_write(mvchip->percpu_regs, 1185 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1186 regmap_write(mvchip->percpu_regs, 1187 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1188 regmap_write(mvchip->percpu_regs, 1189 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1190 } 1191 break; 1192 default: 1193 BUG(); 1194 } 1195 1196 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1197 1198 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1199 if (IS_ENABLED(CONFIG_PWM)) { 1200 err = mvebu_pwm_probe(pdev, mvchip, id); 1201 if (err) 1202 return err; 1203 } 1204 1205 /* Some gpio controllers do not provide irq support */ 1206 if (!have_irqs) 1207 return 0; 1208 1209 mvchip->domain = 1210 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1211 if (!mvchip->domain) { 1212 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1213 mvchip->chip.label); 1214 err = -ENODEV; 1215 goto err_pwm; 1216 } 1217 1218 err = irq_alloc_domain_generic_chips( 1219 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1220 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1221 if (err) { 1222 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1223 mvchip->chip.label); 1224 goto err_domain; 1225 } 1226 1227 /* 1228 * NOTE: The common accessors cannot be used because of the percpu 1229 * access to the mask registers 1230 */ 1231 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1232 gc->private = mvchip; 1233 ct = &gc->chip_types[0]; 1234 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1235 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1236 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1237 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1238 ct->chip.name = mvchip->chip.label; 1239 1240 ct = &gc->chip_types[1]; 1241 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1242 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1243 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1244 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1245 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1246 ct->handler = handle_edge_irq; 1247 ct->chip.name = mvchip->chip.label; 1248 1249 /* 1250 * Setup the interrupt handlers. Each chip can have up to 4 1251 * interrupt handlers, with each handler dealing with 8 GPIO 1252 * pins. 1253 */ 1254 for (i = 0; i < 4; i++) { 1255 int irq = platform_get_irq_optional(pdev, i); 1256 1257 if (irq < 0) 1258 continue; 1259 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1260 mvchip); 1261 } 1262 1263 return 0; 1264 1265err_domain: 1266 irq_domain_remove(mvchip->domain); 1267err_pwm: 1268 pwmchip_remove(&mvchip->mvpwm->chip); 1269 1270 return err; 1271} 1272 1273static struct platform_driver mvebu_gpio_driver = { 1274 .driver = { 1275 .name = "mvebu-gpio", 1276 .of_match_table = mvebu_gpio_of_match, 1277 }, 1278 .probe = mvebu_gpio_probe, 1279 .suspend = mvebu_gpio_suspend, 1280 .resume = mvebu_gpio_resume, 1281}; 1282builtin_platform_driver(mvebu_gpio_driver); 1283