18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * MC33880 high-side/low-side switch GPIO driver
48c2ecf20Sopenharmony_ci * Copyright (c) 2009 Intel Corporation
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci/* Supports:
88c2ecf20Sopenharmony_ci * Freescale MC33880 high-side/low-side switch
98c2ecf20Sopenharmony_ci */
108c2ecf20Sopenharmony_ci
118c2ecf20Sopenharmony_ci#include <linux/init.h>
128c2ecf20Sopenharmony_ci#include <linux/mutex.h>
138c2ecf20Sopenharmony_ci#include <linux/spi/spi.h>
148c2ecf20Sopenharmony_ci#include <linux/spi/mc33880.h>
158c2ecf20Sopenharmony_ci#include <linux/gpio/driver.h>
168c2ecf20Sopenharmony_ci#include <linux/slab.h>
178c2ecf20Sopenharmony_ci#include <linux/module.h>
188c2ecf20Sopenharmony_ci
198c2ecf20Sopenharmony_ci#define DRIVER_NAME "mc33880"
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ci/*
228c2ecf20Sopenharmony_ci * Pin configurations, see MAX7301 datasheet page 6
238c2ecf20Sopenharmony_ci */
248c2ecf20Sopenharmony_ci#define PIN_CONFIG_MASK 0x03
258c2ecf20Sopenharmony_ci#define PIN_CONFIG_IN_PULLUP 0x03
268c2ecf20Sopenharmony_ci#define PIN_CONFIG_IN_WO_PULLUP 0x02
278c2ecf20Sopenharmony_ci#define PIN_CONFIG_OUT 0x01
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_ci#define PIN_NUMBER 8
308c2ecf20Sopenharmony_ci
318c2ecf20Sopenharmony_ci
328c2ecf20Sopenharmony_ci/*
338c2ecf20Sopenharmony_ci * Some registers must be read back to modify.
348c2ecf20Sopenharmony_ci * To save time we cache them here in memory
358c2ecf20Sopenharmony_ci */
368c2ecf20Sopenharmony_cistruct mc33880 {
378c2ecf20Sopenharmony_ci	struct mutex	lock;	/* protect from simultaneous accesses */
388c2ecf20Sopenharmony_ci	u8		port_config;
398c2ecf20Sopenharmony_ci	struct gpio_chip chip;
408c2ecf20Sopenharmony_ci	struct spi_device *spi;
418c2ecf20Sopenharmony_ci};
428c2ecf20Sopenharmony_ci
438c2ecf20Sopenharmony_cistatic int mc33880_write_config(struct mc33880 *mc)
448c2ecf20Sopenharmony_ci{
458c2ecf20Sopenharmony_ci	return spi_write(mc->spi, &mc->port_config, sizeof(mc->port_config));
468c2ecf20Sopenharmony_ci}
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_cistatic int __mc33880_set(struct mc33880 *mc, unsigned offset, int value)
508c2ecf20Sopenharmony_ci{
518c2ecf20Sopenharmony_ci	if (value)
528c2ecf20Sopenharmony_ci		mc->port_config |= 1 << offset;
538c2ecf20Sopenharmony_ci	else
548c2ecf20Sopenharmony_ci		mc->port_config &= ~(1 << offset);
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	return mc33880_write_config(mc);
578c2ecf20Sopenharmony_ci}
588c2ecf20Sopenharmony_ci
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_cistatic void mc33880_set(struct gpio_chip *chip, unsigned offset, int value)
618c2ecf20Sopenharmony_ci{
628c2ecf20Sopenharmony_ci	struct mc33880 *mc = gpiochip_get_data(chip);
638c2ecf20Sopenharmony_ci
648c2ecf20Sopenharmony_ci	mutex_lock(&mc->lock);
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci	__mc33880_set(mc, offset, value);
678c2ecf20Sopenharmony_ci
688c2ecf20Sopenharmony_ci	mutex_unlock(&mc->lock);
698c2ecf20Sopenharmony_ci}
708c2ecf20Sopenharmony_ci
718c2ecf20Sopenharmony_cistatic int mc33880_probe(struct spi_device *spi)
728c2ecf20Sopenharmony_ci{
738c2ecf20Sopenharmony_ci	struct mc33880 *mc;
748c2ecf20Sopenharmony_ci	struct mc33880_platform_data *pdata;
758c2ecf20Sopenharmony_ci	int ret;
768c2ecf20Sopenharmony_ci
778c2ecf20Sopenharmony_ci	pdata = dev_get_platdata(&spi->dev);
788c2ecf20Sopenharmony_ci	if (!pdata || !pdata->base) {
798c2ecf20Sopenharmony_ci		dev_dbg(&spi->dev, "incorrect or missing platform data\n");
808c2ecf20Sopenharmony_ci		return -EINVAL;
818c2ecf20Sopenharmony_ci	}
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ci	/*
848c2ecf20Sopenharmony_ci	 * bits_per_word cannot be configured in platform data
858c2ecf20Sopenharmony_ci	 */
868c2ecf20Sopenharmony_ci	spi->bits_per_word = 8;
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci	ret = spi_setup(spi);
898c2ecf20Sopenharmony_ci	if (ret < 0)
908c2ecf20Sopenharmony_ci		return ret;
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci	mc = devm_kzalloc(&spi->dev, sizeof(struct mc33880), GFP_KERNEL);
938c2ecf20Sopenharmony_ci	if (!mc)
948c2ecf20Sopenharmony_ci		return -ENOMEM;
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_ci	mutex_init(&mc->lock);
978c2ecf20Sopenharmony_ci
988c2ecf20Sopenharmony_ci	spi_set_drvdata(spi, mc);
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci	mc->spi = spi;
1018c2ecf20Sopenharmony_ci
1028c2ecf20Sopenharmony_ci	mc->chip.label = DRIVER_NAME,
1038c2ecf20Sopenharmony_ci	mc->chip.set = mc33880_set;
1048c2ecf20Sopenharmony_ci	mc->chip.base = pdata->base;
1058c2ecf20Sopenharmony_ci	mc->chip.ngpio = PIN_NUMBER;
1068c2ecf20Sopenharmony_ci	mc->chip.can_sleep = true;
1078c2ecf20Sopenharmony_ci	mc->chip.parent = &spi->dev;
1088c2ecf20Sopenharmony_ci	mc->chip.owner = THIS_MODULE;
1098c2ecf20Sopenharmony_ci
1108c2ecf20Sopenharmony_ci	mc->port_config = 0x00;
1118c2ecf20Sopenharmony_ci	/* write twice, because during initialisation the first setting
1128c2ecf20Sopenharmony_ci	 * is just for testing SPI communication, and the second is the
1138c2ecf20Sopenharmony_ci	 * "real" configuration
1148c2ecf20Sopenharmony_ci	 */
1158c2ecf20Sopenharmony_ci	ret = mc33880_write_config(mc);
1168c2ecf20Sopenharmony_ci	mc->port_config = 0x00;
1178c2ecf20Sopenharmony_ci	if (!ret)
1188c2ecf20Sopenharmony_ci		ret = mc33880_write_config(mc);
1198c2ecf20Sopenharmony_ci
1208c2ecf20Sopenharmony_ci	if (ret) {
1218c2ecf20Sopenharmony_ci		dev_err(&spi->dev, "Failed writing to " DRIVER_NAME ": %d\n",
1228c2ecf20Sopenharmony_ci			ret);
1238c2ecf20Sopenharmony_ci		goto exit_destroy;
1248c2ecf20Sopenharmony_ci	}
1258c2ecf20Sopenharmony_ci
1268c2ecf20Sopenharmony_ci	ret = gpiochip_add_data(&mc->chip, mc);
1278c2ecf20Sopenharmony_ci	if (ret)
1288c2ecf20Sopenharmony_ci		goto exit_destroy;
1298c2ecf20Sopenharmony_ci
1308c2ecf20Sopenharmony_ci	return ret;
1318c2ecf20Sopenharmony_ci
1328c2ecf20Sopenharmony_ciexit_destroy:
1338c2ecf20Sopenharmony_ci	mutex_destroy(&mc->lock);
1348c2ecf20Sopenharmony_ci	return ret;
1358c2ecf20Sopenharmony_ci}
1368c2ecf20Sopenharmony_ci
1378c2ecf20Sopenharmony_cistatic int mc33880_remove(struct spi_device *spi)
1388c2ecf20Sopenharmony_ci{
1398c2ecf20Sopenharmony_ci	struct mc33880 *mc;
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ci	mc = spi_get_drvdata(spi);
1428c2ecf20Sopenharmony_ci	if (!mc)
1438c2ecf20Sopenharmony_ci		return -ENODEV;
1448c2ecf20Sopenharmony_ci
1458c2ecf20Sopenharmony_ci	gpiochip_remove(&mc->chip);
1468c2ecf20Sopenharmony_ci	mutex_destroy(&mc->lock);
1478c2ecf20Sopenharmony_ci
1488c2ecf20Sopenharmony_ci	return 0;
1498c2ecf20Sopenharmony_ci}
1508c2ecf20Sopenharmony_ci
1518c2ecf20Sopenharmony_cistatic struct spi_driver mc33880_driver = {
1528c2ecf20Sopenharmony_ci	.driver = {
1538c2ecf20Sopenharmony_ci		.name		= DRIVER_NAME,
1548c2ecf20Sopenharmony_ci	},
1558c2ecf20Sopenharmony_ci	.probe		= mc33880_probe,
1568c2ecf20Sopenharmony_ci	.remove		= mc33880_remove,
1578c2ecf20Sopenharmony_ci};
1588c2ecf20Sopenharmony_ci
1598c2ecf20Sopenharmony_cistatic int __init mc33880_init(void)
1608c2ecf20Sopenharmony_ci{
1618c2ecf20Sopenharmony_ci	return spi_register_driver(&mc33880_driver);
1628c2ecf20Sopenharmony_ci}
1638c2ecf20Sopenharmony_ci/* register after spi postcore initcall and before
1648c2ecf20Sopenharmony_ci * subsys initcalls that may rely on these GPIOs
1658c2ecf20Sopenharmony_ci */
1668c2ecf20Sopenharmony_cisubsys_initcall(mc33880_init);
1678c2ecf20Sopenharmony_ci
1688c2ecf20Sopenharmony_cistatic void __exit mc33880_exit(void)
1698c2ecf20Sopenharmony_ci{
1708c2ecf20Sopenharmony_ci	spi_unregister_driver(&mc33880_driver);
1718c2ecf20Sopenharmony_ci}
1728c2ecf20Sopenharmony_cimodule_exit(mc33880_exit);
1738c2ecf20Sopenharmony_ci
1748c2ecf20Sopenharmony_ciMODULE_AUTHOR("Mocean Laboratories <info@mocean-labs.com>");
1758c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2");
1768c2ecf20Sopenharmony_ci
177