1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 *  linux/arch/arm/mach-ep93xx/core.c
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/slab.h>
18#include <linux/gpio/driver.h>
19#include <linux/bitops.h>
20
21#define EP93XX_GPIO_F_INT_STATUS 0x5c
22#define EP93XX_GPIO_A_INT_STATUS 0xa0
23#define EP93XX_GPIO_B_INT_STATUS 0xbc
24
25/* Maximum value for gpio line identifiers */
26#define EP93XX_GPIO_LINE_MAX 63
27
28/* Number of GPIO chips in EP93XX */
29#define EP93XX_GPIO_CHIP_NUM 8
30
31/* Maximum value for irq capable line identifiers */
32#define EP93XX_GPIO_LINE_MAX_IRQ 23
33
34/*
35 * Static mapping of GPIO bank F IRQS:
36 * F0..F7 (16..24) to irq 80..87.
37 */
38#define EP93XX_GPIO_F_IRQ_BASE 80
39
40struct ep93xx_gpio_irq_chip {
41	struct irq_chip ic;
42	u8 irq_offset;
43	u8 int_unmasked;
44	u8 int_enabled;
45	u8 int_type1;
46	u8 int_type2;
47	u8 int_debounce;
48};
49
50struct ep93xx_gpio_chip {
51	struct gpio_chip		gc;
52	struct ep93xx_gpio_irq_chip	*eic;
53};
54
55struct ep93xx_gpio {
56	void __iomem		*base;
57	struct ep93xx_gpio_chip	gc[EP93XX_GPIO_CHIP_NUM];
58};
59
60#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
61
62static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
63{
64	struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
65
66	return egc->eic;
67}
68
69/*************************************************************************
70 * Interrupt handling for EP93xx on-chip GPIOs
71 *************************************************************************/
72#define EP93XX_INT_TYPE1_OFFSET		0x00
73#define EP93XX_INT_TYPE2_OFFSET		0x04
74#define EP93XX_INT_EOI_OFFSET		0x08
75#define EP93XX_INT_EN_OFFSET		0x0c
76#define EP93XX_INT_STATUS_OFFSET	0x10
77#define EP93XX_INT_RAW_STATUS_OFFSET	0x14
78#define EP93XX_INT_DEBOUNCE_OFFSET	0x18
79
80static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
81					  struct ep93xx_gpio_irq_chip *eic)
82{
83	writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
84
85	writeb_relaxed(eic->int_type2,
86		       epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
87
88	writeb_relaxed(eic->int_type1,
89		       epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
90
91	writeb_relaxed(eic->int_unmasked & eic->int_enabled,
92		       epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
93}
94
95static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
96				     unsigned int offset, bool enable)
97{
98	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
99	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
100	int port_mask = BIT(offset);
101
102	if (enable)
103		eic->int_debounce |= port_mask;
104	else
105		eic->int_debounce &= ~port_mask;
106
107	writeb(eic->int_debounce,
108	       epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
109}
110
111static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
112{
113	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
114	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
115	struct irq_chip *irqchip = irq_desc_get_chip(desc);
116	unsigned long stat;
117	int offset;
118
119	chained_irq_enter(irqchip, desc);
120
121	/*
122	 * Dispatch the IRQs to the irqdomain of each A and B
123	 * gpiochip irqdomains depending on what has fired.
124	 * The tricky part is that the IRQ line is shared
125	 * between bank A and B and each has their own gpiochip.
126	 */
127	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
128	for_each_set_bit(offset, &stat, 8)
129		generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
130						    offset));
131
132	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
133	for_each_set_bit(offset, &stat, 8)
134		generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
135						    offset));
136
137	chained_irq_exit(irqchip, desc);
138}
139
140static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
141{
142	/*
143	 * map discontiguous hw irq range to continuous sw irq range:
144	 *
145	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
146	 */
147	struct irq_chip *irqchip = irq_desc_get_chip(desc);
148	unsigned int irq = irq_desc_get_irq(desc);
149	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
150	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
151
152	chained_irq_enter(irqchip, desc);
153	generic_handle_irq(gpio_irq);
154	chained_irq_exit(irqchip, desc);
155}
156
157static void ep93xx_gpio_irq_ack(struct irq_data *d)
158{
159	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
160	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
161	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
162	int port_mask = BIT(d->irq & 7);
163
164	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
165		eic->int_type2 ^= port_mask; /* switch edge direction */
166		ep93xx_gpio_update_int_params(epg, eic);
167	}
168
169	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
170}
171
172static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
173{
174	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
176	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
177	int port_mask = BIT(d->irq & 7);
178
179	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
180		eic->int_type2 ^= port_mask; /* switch edge direction */
181
182	eic->int_unmasked &= ~port_mask;
183	ep93xx_gpio_update_int_params(epg, eic);
184
185	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
186}
187
188static void ep93xx_gpio_irq_mask(struct irq_data *d)
189{
190	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
191	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
192	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
193
194	eic->int_unmasked &= ~BIT(d->irq & 7);
195	ep93xx_gpio_update_int_params(epg, eic);
196}
197
198static void ep93xx_gpio_irq_unmask(struct irq_data *d)
199{
200	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
201	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
202	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
203
204	eic->int_unmasked |= BIT(d->irq & 7);
205	ep93xx_gpio_update_int_params(epg, eic);
206}
207
208/*
209 * gpio_int_type1 controls whether the interrupt is level (0) or
210 * edge (1) triggered, while gpio_int_type2 controls whether it
211 * triggers on low/falling (0) or high/rising (1).
212 */
213static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
214{
215	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
216	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
217	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
218	int offset = d->irq & 7;
219	int port_mask = BIT(offset);
220	irq_flow_handler_t handler;
221
222	gc->direction_input(gc, offset);
223
224	switch (type) {
225	case IRQ_TYPE_EDGE_RISING:
226		eic->int_type1 |= port_mask;
227		eic->int_type2 |= port_mask;
228		handler = handle_edge_irq;
229		break;
230	case IRQ_TYPE_EDGE_FALLING:
231		eic->int_type1 |= port_mask;
232		eic->int_type2 &= ~port_mask;
233		handler = handle_edge_irq;
234		break;
235	case IRQ_TYPE_LEVEL_HIGH:
236		eic->int_type1 &= ~port_mask;
237		eic->int_type2 |= port_mask;
238		handler = handle_level_irq;
239		break;
240	case IRQ_TYPE_LEVEL_LOW:
241		eic->int_type1 &= ~port_mask;
242		eic->int_type2 &= ~port_mask;
243		handler = handle_level_irq;
244		break;
245	case IRQ_TYPE_EDGE_BOTH:
246		eic->int_type1 |= port_mask;
247		/* set initial polarity based on current input level */
248		if (gc->get(gc, offset))
249			eic->int_type2 &= ~port_mask; /* falling */
250		else
251			eic->int_type2 |= port_mask; /* rising */
252		handler = handle_edge_irq;
253		break;
254	default:
255		return -EINVAL;
256	}
257
258	irq_set_handler_locked(d, handler);
259
260	eic->int_enabled |= port_mask;
261
262	ep93xx_gpio_update_int_params(epg, eic);
263
264	return 0;
265}
266
267/*************************************************************************
268 * gpiolib interface for EP93xx on-chip GPIOs
269 *************************************************************************/
270struct ep93xx_gpio_bank {
271	const char	*label;
272	int		data;
273	int		dir;
274	int		irq;
275	int		base;
276	bool		has_irq;
277	bool		has_hierarchical_irq;
278	unsigned int	irq_base;
279};
280
281#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
282	{							\
283		.label		= _label,			\
284		.data		= _data,			\
285		.dir		= _dir,				\
286		.irq		= _irq,				\
287		.base		= _base,			\
288		.has_irq	= _has_irq,			\
289		.has_hierarchical_irq = _has_hier,		\
290		.irq_base	= _irq_base,			\
291	}
292
293static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
294	/* Bank A has 8 IRQs */
295	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64),
296	/* Bank B has 8 IRQs */
297	EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72),
298	EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
299	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
300	EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
301	/* Bank F has 8 IRQs */
302	EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0),
303	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
304	EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
305};
306
307static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
308				  unsigned long config)
309{
310	u32 debounce;
311
312	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
313		return -ENOTSUPP;
314
315	debounce = pinconf_to_config_argument(config);
316	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
317
318	return 0;
319}
320
321static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
322{
323	return EP93XX_GPIO_F_IRQ_BASE + offset;
324}
325
326static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
327{
328	ic->irq_ack = ep93xx_gpio_irq_ack;
329	ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
330	ic->irq_mask = ep93xx_gpio_irq_mask;
331	ic->irq_unmask = ep93xx_gpio_irq_unmask;
332	ic->irq_set_type = ep93xx_gpio_irq_type;
333}
334
335static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
336				struct platform_device *pdev,
337				struct ep93xx_gpio *epg,
338				struct ep93xx_gpio_bank *bank)
339{
340	void __iomem *data = epg->base + bank->data;
341	void __iomem *dir = epg->base + bank->dir;
342	struct gpio_chip *gc = &egc->gc;
343	struct device *dev = &pdev->dev;
344	struct gpio_irq_chip *girq;
345	int err;
346
347	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
348	if (err)
349		return err;
350
351	gc->label = bank->label;
352	gc->base = bank->base;
353
354	girq = &gc->irq;
355	if (bank->has_irq || bank->has_hierarchical_irq) {
356		struct irq_chip *ic;
357
358		gc->set_config = ep93xx_gpio_set_config;
359		egc->eic = devm_kcalloc(dev, 1,
360					sizeof(*egc->eic),
361					GFP_KERNEL);
362		if (!egc->eic)
363			return -ENOMEM;
364		egc->eic->irq_offset = bank->irq;
365		ic = &egc->eic->ic;
366		ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
367		if (!ic->name)
368			return -ENOMEM;
369		ep93xx_init_irq_chip(dev, ic);
370		girq->chip = ic;
371	}
372
373	if (bank->has_irq) {
374		int ab_parent_irq = platform_get_irq(pdev, 0);
375
376		girq->parent_handler = ep93xx_gpio_ab_irq_handler;
377		girq->num_parents = 1;
378		girq->parents = devm_kcalloc(dev, 1,
379					     sizeof(*girq->parents),
380					     GFP_KERNEL);
381		if (!girq->parents)
382			return -ENOMEM;
383		girq->default_type = IRQ_TYPE_NONE;
384		girq->handler = handle_level_irq;
385		girq->parents[0] = ab_parent_irq;
386		girq->first = bank->irq_base;
387	}
388
389	/* Only bank F has especially funky IRQ handling */
390	if (bank->has_hierarchical_irq) {
391		int gpio_irq;
392		int i;
393
394		/*
395		 * FIXME: convert this to use hierarchical IRQ support!
396		 * this requires fixing the root irqchip to be hierarchial.
397		 */
398		girq->parent_handler = ep93xx_gpio_f_irq_handler;
399		girq->num_parents = 8;
400		girq->parents = devm_kcalloc(dev, 8,
401					     sizeof(*girq->parents),
402					     GFP_KERNEL);
403		if (!girq->parents)
404			return -ENOMEM;
405		/* Pick resources 1..8 for these IRQs */
406		for (i = 1; i <= 8; i++)
407			girq->parents[i - 1] = platform_get_irq(pdev, i);
408		for (i = 0; i < 8; i++) {
409			gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
410			irq_set_chip_data(gpio_irq, &epg->gc[5]);
411			irq_set_chip_and_handler(gpio_irq,
412						 girq->chip,
413						 handle_level_irq);
414			irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
415		}
416		girq->default_type = IRQ_TYPE_NONE;
417		girq->handler = handle_level_irq;
418		gc->to_irq = ep93xx_gpio_f_to_irq;
419	}
420
421	return devm_gpiochip_add_data(dev, gc, epg);
422}
423
424static int ep93xx_gpio_probe(struct platform_device *pdev)
425{
426	struct ep93xx_gpio *epg;
427	int i;
428
429	epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
430	if (!epg)
431		return -ENOMEM;
432
433	epg->base = devm_platform_ioremap_resource(pdev, 0);
434	if (IS_ERR(epg->base))
435		return PTR_ERR(epg->base);
436
437	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
438		struct ep93xx_gpio_chip *gc = &epg->gc[i];
439		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
440
441		if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
442			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
443				 bank->label);
444	}
445
446	return 0;
447}
448
449static struct platform_driver ep93xx_gpio_driver = {
450	.driver		= {
451		.name	= "gpio-ep93xx",
452	},
453	.probe		= ep93xx_gpio_probe,
454};
455
456static int __init ep93xx_gpio_init(void)
457{
458	return platform_driver_register(&ep93xx_gpio_driver);
459}
460postcore_initcall(ep93xx_gpio_init);
461
462MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
463		"H Hartley Sweeten <hsweeten@visionengravers.com>");
464MODULE_DESCRIPTION("EP93XX GPIO driver");
465MODULE_LICENSE("GPL");
466