1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7#include <linux/bitops.h> 8#include <linux/gpio/driver.h> 9#include <linux/interrupt.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/of_device.h> 13#include <linux/platform_device.h> 14#include <linux/spinlock.h> 15 16/* EIC registers definition */ 17#define SPRD_EIC_DBNC_DATA 0x0 18#define SPRD_EIC_DBNC_DMSK 0x4 19#define SPRD_EIC_DBNC_IEV 0x14 20#define SPRD_EIC_DBNC_IE 0x18 21#define SPRD_EIC_DBNC_RIS 0x1c 22#define SPRD_EIC_DBNC_MIS 0x20 23#define SPRD_EIC_DBNC_IC 0x24 24#define SPRD_EIC_DBNC_TRIG 0x28 25#define SPRD_EIC_DBNC_CTRL0 0x40 26 27#define SPRD_EIC_LATCH_INTEN 0x0 28#define SPRD_EIC_LATCH_INTRAW 0x4 29#define SPRD_EIC_LATCH_INTMSK 0x8 30#define SPRD_EIC_LATCH_INTCLR 0xc 31#define SPRD_EIC_LATCH_INTPOL 0x10 32#define SPRD_EIC_LATCH_INTMODE 0x14 33 34#define SPRD_EIC_ASYNC_INTIE 0x0 35#define SPRD_EIC_ASYNC_INTRAW 0x4 36#define SPRD_EIC_ASYNC_INTMSK 0x8 37#define SPRD_EIC_ASYNC_INTCLR 0xc 38#define SPRD_EIC_ASYNC_INTMODE 0x10 39#define SPRD_EIC_ASYNC_INTBOTH 0x14 40#define SPRD_EIC_ASYNC_INTPOL 0x18 41#define SPRD_EIC_ASYNC_DATA 0x1c 42 43#define SPRD_EIC_SYNC_INTIE 0x0 44#define SPRD_EIC_SYNC_INTRAW 0x4 45#define SPRD_EIC_SYNC_INTMSK 0x8 46#define SPRD_EIC_SYNC_INTCLR 0xc 47#define SPRD_EIC_SYNC_INTMODE 0x10 48#define SPRD_EIC_SYNC_INTBOTH 0x14 49#define SPRD_EIC_SYNC_INTPOL 0x18 50#define SPRD_EIC_SYNC_DATA 0x1c 51 52/* 53 * The digital-chip EIC controller can support maximum 3 banks, and each bank 54 * contains 8 EICs. 55 */ 56#define SPRD_EIC_MAX_BANK 3 57#define SPRD_EIC_PER_BANK_NR 8 58#define SPRD_EIC_DATA_MASK GENMASK(7, 0) 59#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) 60#define SPRD_EIC_DBNC_MASK GENMASK(11, 0) 61 62/* 63 * The Spreadtrum EIC (external interrupt controller) can be used only in 64 * input mode to generate interrupts if detecting input signals. 65 * 66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules: 67 * debounce EIC, latch EIC, async EIC and sync EIC, 68 * 69 * The debounce EIC is used to capture the input signals' stable status 70 * (millisecond resolution) and a single-trigger mechanism is introduced 71 * into this sub-module to enhance the input event detection reliability. 72 * The debounce range is from 1ms to 4s with a step size of 1ms. 73 * 74 * The latch EIC is used to latch some special power down signals and 75 * generate interrupts, since the latch EIC does not depend on the APB clock 76 * to capture signals. 77 * 78 * The async EIC uses a 32k clock to capture the short signals (microsecond 79 * resolution) to generate interrupts by level or edge trigger. 80 * 81 * The EIC-sync is similar with GPIO's input function, which is a synchronized 82 * signal input register. 83 */ 84enum sprd_eic_type { 85 SPRD_EIC_DEBOUNCE, 86 SPRD_EIC_LATCH, 87 SPRD_EIC_ASYNC, 88 SPRD_EIC_SYNC, 89 SPRD_EIC_MAX, 90}; 91 92struct sprd_eic { 93 struct gpio_chip chip; 94 struct irq_chip intc; 95 void __iomem *base[SPRD_EIC_MAX_BANK]; 96 enum sprd_eic_type type; 97 spinlock_t lock; 98 int irq; 99}; 100 101struct sprd_eic_variant_data { 102 enum sprd_eic_type type; 103 u32 num_eics; 104}; 105 106static const char *sprd_eic_label_name[SPRD_EIC_MAX] = { 107 "eic-debounce", "eic-latch", "eic-async", 108 "eic-sync", 109}; 110 111static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = { 112 .type = SPRD_EIC_DEBOUNCE, 113 .num_eics = 8, 114}; 115 116static const struct sprd_eic_variant_data sc9860_eic_latch_data = { 117 .type = SPRD_EIC_LATCH, 118 .num_eics = 8, 119}; 120 121static const struct sprd_eic_variant_data sc9860_eic_async_data = { 122 .type = SPRD_EIC_ASYNC, 123 .num_eics = 8, 124}; 125 126static const struct sprd_eic_variant_data sc9860_eic_sync_data = { 127 .type = SPRD_EIC_SYNC, 128 .num_eics = 8, 129}; 130 131static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic, 132 unsigned int bank) 133{ 134 if (bank >= SPRD_EIC_MAX_BANK) 135 return NULL; 136 137 return sprd_eic->base[bank]; 138} 139 140static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, 141 u16 reg, unsigned int val) 142{ 143 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 144 void __iomem *base = 145 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 146 unsigned long flags; 147 u32 tmp; 148 149 spin_lock_irqsave(&sprd_eic->lock, flags); 150 tmp = readl_relaxed(base + reg); 151 152 if (val) 153 tmp |= BIT(SPRD_EIC_BIT(offset)); 154 else 155 tmp &= ~BIT(SPRD_EIC_BIT(offset)); 156 157 writel_relaxed(tmp, base + reg); 158 spin_unlock_irqrestore(&sprd_eic->lock, flags); 159} 160 161static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) 162{ 163 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 164 void __iomem *base = 165 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 166 167 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); 168} 169 170static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) 171{ 172 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); 173 return 0; 174} 175 176static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) 177{ 178 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); 179} 180 181static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) 182{ 183 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 184 185 switch (sprd_eic->type) { 186 case SPRD_EIC_DEBOUNCE: 187 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); 188 case SPRD_EIC_ASYNC: 189 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); 190 case SPRD_EIC_SYNC: 191 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); 192 default: 193 return -ENOTSUPP; 194 } 195} 196 197static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) 198{ 199 /* EICs are always input, nothing need to do here. */ 200 return 0; 201} 202 203static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) 204{ 205 /* EICs are always input, nothing need to do here. */ 206} 207 208static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, 209 unsigned int debounce) 210{ 211 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 212 void __iomem *base = 213 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 214 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; 215 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; 216 217 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK; 218 writel_relaxed(value, base + reg); 219 220 return 0; 221} 222 223static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, 224 unsigned long config) 225{ 226 unsigned long param = pinconf_to_config_param(config); 227 u32 arg = pinconf_to_config_argument(config); 228 229 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 230 return sprd_eic_set_debounce(chip, offset, arg); 231 232 return -ENOTSUPP; 233} 234 235static void sprd_eic_irq_mask(struct irq_data *data) 236{ 237 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 238 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 239 u32 offset = irqd_to_hwirq(data); 240 241 switch (sprd_eic->type) { 242 case SPRD_EIC_DEBOUNCE: 243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); 244 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); 245 break; 246 case SPRD_EIC_LATCH: 247 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); 248 break; 249 case SPRD_EIC_ASYNC: 250 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); 251 break; 252 case SPRD_EIC_SYNC: 253 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); 254 break; 255 default: 256 dev_err(chip->parent, "Unsupported EIC type.\n"); 257 } 258} 259 260static void sprd_eic_irq_unmask(struct irq_data *data) 261{ 262 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 263 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 264 u32 offset = irqd_to_hwirq(data); 265 266 switch (sprd_eic->type) { 267 case SPRD_EIC_DEBOUNCE: 268 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); 269 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); 270 break; 271 case SPRD_EIC_LATCH: 272 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); 273 break; 274 case SPRD_EIC_ASYNC: 275 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); 276 break; 277 case SPRD_EIC_SYNC: 278 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); 279 break; 280 default: 281 dev_err(chip->parent, "Unsupported EIC type.\n"); 282 } 283} 284 285static void sprd_eic_irq_ack(struct irq_data *data) 286{ 287 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 288 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 289 u32 offset = irqd_to_hwirq(data); 290 291 switch (sprd_eic->type) { 292 case SPRD_EIC_DEBOUNCE: 293 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 294 break; 295 case SPRD_EIC_LATCH: 296 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 297 break; 298 case SPRD_EIC_ASYNC: 299 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 300 break; 301 case SPRD_EIC_SYNC: 302 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 303 break; 304 default: 305 dev_err(chip->parent, "Unsupported EIC type.\n"); 306 } 307} 308 309static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) 310{ 311 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 312 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 313 u32 offset = irqd_to_hwirq(data); 314 int state; 315 316 switch (sprd_eic->type) { 317 case SPRD_EIC_DEBOUNCE: 318 switch (flow_type) { 319 case IRQ_TYPE_LEVEL_HIGH: 320 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 321 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 322 break; 323 case IRQ_TYPE_LEVEL_LOW: 324 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 325 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 326 break; 327 case IRQ_TYPE_EDGE_RISING: 328 case IRQ_TYPE_EDGE_FALLING: 329 case IRQ_TYPE_EDGE_BOTH: 330 state = sprd_eic_get(chip, offset); 331 if (state) { 332 sprd_eic_update(chip, offset, 333 SPRD_EIC_DBNC_IEV, 0); 334 sprd_eic_update(chip, offset, 335 SPRD_EIC_DBNC_IC, 1); 336 } else { 337 sprd_eic_update(chip, offset, 338 SPRD_EIC_DBNC_IEV, 1); 339 sprd_eic_update(chip, offset, 340 SPRD_EIC_DBNC_IC, 1); 341 } 342 break; 343 default: 344 return -ENOTSUPP; 345 } 346 347 irq_set_handler_locked(data, handle_level_irq); 348 break; 349 case SPRD_EIC_LATCH: 350 switch (flow_type) { 351 case IRQ_TYPE_LEVEL_HIGH: 352 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 353 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 354 break; 355 case IRQ_TYPE_LEVEL_LOW: 356 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 357 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 358 break; 359 case IRQ_TYPE_EDGE_RISING: 360 case IRQ_TYPE_EDGE_FALLING: 361 case IRQ_TYPE_EDGE_BOTH: 362 state = sprd_eic_get(chip, offset); 363 if (state) { 364 sprd_eic_update(chip, offset, 365 SPRD_EIC_LATCH_INTPOL, 0); 366 sprd_eic_update(chip, offset, 367 SPRD_EIC_LATCH_INTCLR, 1); 368 } else { 369 sprd_eic_update(chip, offset, 370 SPRD_EIC_LATCH_INTPOL, 1); 371 sprd_eic_update(chip, offset, 372 SPRD_EIC_LATCH_INTCLR, 1); 373 } 374 break; 375 default: 376 return -ENOTSUPP; 377 } 378 379 irq_set_handler_locked(data, handle_level_irq); 380 break; 381 case SPRD_EIC_ASYNC: 382 switch (flow_type) { 383 case IRQ_TYPE_EDGE_RISING: 384 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 385 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 386 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 387 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 388 irq_set_handler_locked(data, handle_edge_irq); 389 break; 390 case IRQ_TYPE_EDGE_FALLING: 391 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 393 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 394 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 395 irq_set_handler_locked(data, handle_edge_irq); 396 break; 397 case IRQ_TYPE_EDGE_BOTH: 398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 399 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); 400 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 401 irq_set_handler_locked(data, handle_edge_irq); 402 break; 403 case IRQ_TYPE_LEVEL_HIGH: 404 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 405 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 406 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 407 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 408 irq_set_handler_locked(data, handle_level_irq); 409 break; 410 case IRQ_TYPE_LEVEL_LOW: 411 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 412 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 413 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 414 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 415 irq_set_handler_locked(data, handle_level_irq); 416 break; 417 default: 418 return -ENOTSUPP; 419 } 420 break; 421 case SPRD_EIC_SYNC: 422 switch (flow_type) { 423 case IRQ_TYPE_EDGE_RISING: 424 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 425 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 426 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 428 irq_set_handler_locked(data, handle_edge_irq); 429 break; 430 case IRQ_TYPE_EDGE_FALLING: 431 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 434 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 435 irq_set_handler_locked(data, handle_edge_irq); 436 break; 437 case IRQ_TYPE_EDGE_BOTH: 438 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 439 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); 440 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 441 irq_set_handler_locked(data, handle_edge_irq); 442 break; 443 case IRQ_TYPE_LEVEL_HIGH: 444 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 445 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 446 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 447 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 448 irq_set_handler_locked(data, handle_level_irq); 449 break; 450 case IRQ_TYPE_LEVEL_LOW: 451 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 452 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 453 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 454 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 455 irq_set_handler_locked(data, handle_level_irq); 456 break; 457 default: 458 return -ENOTSUPP; 459 } 460 break; 461 default: 462 dev_err(chip->parent, "Unsupported EIC type.\n"); 463 return -ENOTSUPP; 464 } 465 466 return 0; 467} 468 469static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, 470 unsigned int offset) 471{ 472 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 473 struct irq_data *data = irq_get_irq_data(irq); 474 u32 trigger = irqd_get_trigger_type(data); 475 int state, post_state; 476 477 /* 478 * The debounce EIC and latch EIC can only support level trigger, so we 479 * can toggle the level trigger to emulate the edge trigger. 480 */ 481 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && 482 sprd_eic->type != SPRD_EIC_LATCH) || 483 !(trigger & IRQ_TYPE_EDGE_BOTH)) 484 return; 485 486 sprd_eic_irq_mask(data); 487 state = sprd_eic_get(chip, offset); 488 489retry: 490 switch (sprd_eic->type) { 491 case SPRD_EIC_DEBOUNCE: 492 if (state) 493 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 494 else 495 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 496 break; 497 case SPRD_EIC_LATCH: 498 if (state) 499 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 500 else 501 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 502 break; 503 default: 504 sprd_eic_irq_unmask(data); 505 return; 506 } 507 508 post_state = sprd_eic_get(chip, offset); 509 if (state != post_state) { 510 dev_warn(chip->parent, "EIC level was changed.\n"); 511 state = post_state; 512 goto retry; 513 } 514 515 sprd_eic_irq_unmask(data); 516} 517 518static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data) 519{ 520 enum sprd_eic_type type = *(enum sprd_eic_type *)data; 521 522 return !strcmp(chip->label, sprd_eic_label_name[type]); 523} 524 525static void sprd_eic_handle_one_type(struct gpio_chip *chip) 526{ 527 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 528 u32 bank, n, girq; 529 530 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { 531 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); 532 unsigned long reg; 533 534 switch (sprd_eic->type) { 535 case SPRD_EIC_DEBOUNCE: 536 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & 537 SPRD_EIC_DATA_MASK; 538 break; 539 case SPRD_EIC_LATCH: 540 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & 541 SPRD_EIC_DATA_MASK; 542 break; 543 case SPRD_EIC_ASYNC: 544 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & 545 SPRD_EIC_DATA_MASK; 546 break; 547 case SPRD_EIC_SYNC: 548 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & 549 SPRD_EIC_DATA_MASK; 550 break; 551 default: 552 dev_err(chip->parent, "Unsupported EIC type.\n"); 553 return; 554 } 555 556 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { 557 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; 558 559 girq = irq_find_mapping(chip->irq.domain, offset); 560 561 generic_handle_irq(girq); 562 sprd_eic_toggle_trigger(chip, girq, offset); 563 } 564 } 565} 566 567static void sprd_eic_irq_handler(struct irq_desc *desc) 568{ 569 struct irq_chip *ic = irq_desc_get_chip(desc); 570 struct gpio_chip *chip; 571 enum sprd_eic_type type; 572 573 chained_irq_enter(ic, desc); 574 575 /* 576 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async 577 * and sync) share one same interrupt line, we should iterate each 578 * EIC module to check if there are EIC interrupts were triggered. 579 */ 580 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) { 581 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type); 582 if (!chip) 583 continue; 584 585 sprd_eic_handle_one_type(chip); 586 } 587 588 chained_irq_exit(ic, desc); 589} 590 591static int sprd_eic_probe(struct platform_device *pdev) 592{ 593 const struct sprd_eic_variant_data *pdata; 594 struct gpio_irq_chip *irq; 595 struct sprd_eic *sprd_eic; 596 struct resource *res; 597 int ret, i; 598 599 pdata = of_device_get_match_data(&pdev->dev); 600 if (!pdata) { 601 dev_err(&pdev->dev, "No matching driver data found.\n"); 602 return -EINVAL; 603 } 604 605 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL); 606 if (!sprd_eic) 607 return -ENOMEM; 608 609 spin_lock_init(&sprd_eic->lock); 610 sprd_eic->type = pdata->type; 611 612 sprd_eic->irq = platform_get_irq(pdev, 0); 613 if (sprd_eic->irq < 0) 614 return sprd_eic->irq; 615 616 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { 617 /* 618 * We can have maximum 3 banks EICs, and each EIC has 619 * its own base address. But some platform maybe only 620 * have one bank EIC, thus base[1] and base[2] can be 621 * optional. 622 */ 623 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 624 if (!res) 625 break; 626 627 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res); 628 if (IS_ERR(sprd_eic->base[i])) 629 return PTR_ERR(sprd_eic->base[i]); 630 } 631 632 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type]; 633 sprd_eic->chip.ngpio = pdata->num_eics; 634 sprd_eic->chip.base = -1; 635 sprd_eic->chip.parent = &pdev->dev; 636 sprd_eic->chip.of_node = pdev->dev.of_node; 637 sprd_eic->chip.direction_input = sprd_eic_direction_input; 638 switch (sprd_eic->type) { 639 case SPRD_EIC_DEBOUNCE: 640 sprd_eic->chip.request = sprd_eic_request; 641 sprd_eic->chip.free = sprd_eic_free; 642 sprd_eic->chip.set_config = sprd_eic_set_config; 643 sprd_eic->chip.set = sprd_eic_set; 644 fallthrough; 645 case SPRD_EIC_ASYNC: 646 case SPRD_EIC_SYNC: 647 sprd_eic->chip.get = sprd_eic_get; 648 break; 649 case SPRD_EIC_LATCH: 650 default: 651 break; 652 } 653 654 sprd_eic->intc.name = dev_name(&pdev->dev); 655 sprd_eic->intc.irq_ack = sprd_eic_irq_ack; 656 sprd_eic->intc.irq_mask = sprd_eic_irq_mask; 657 sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask; 658 sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type; 659 sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE; 660 661 irq = &sprd_eic->chip.irq; 662 irq->chip = &sprd_eic->intc; 663 irq->handler = handle_bad_irq; 664 irq->default_type = IRQ_TYPE_NONE; 665 irq->parent_handler = sprd_eic_irq_handler; 666 irq->parent_handler_data = sprd_eic; 667 irq->num_parents = 1; 668 irq->parents = &sprd_eic->irq; 669 670 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic); 671 if (ret < 0) { 672 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 673 return ret; 674 } 675 676 platform_set_drvdata(pdev, sprd_eic); 677 return 0; 678} 679 680static const struct of_device_id sprd_eic_of_match[] = { 681 { 682 .compatible = "sprd,sc9860-eic-debounce", 683 .data = &sc9860_eic_dbnc_data, 684 }, 685 { 686 .compatible = "sprd,sc9860-eic-latch", 687 .data = &sc9860_eic_latch_data, 688 }, 689 { 690 .compatible = "sprd,sc9860-eic-async", 691 .data = &sc9860_eic_async_data, 692 }, 693 { 694 .compatible = "sprd,sc9860-eic-sync", 695 .data = &sc9860_eic_sync_data, 696 }, 697 { 698 /* end of list */ 699 } 700}; 701MODULE_DEVICE_TABLE(of, sprd_eic_of_match); 702 703static struct platform_driver sprd_eic_driver = { 704 .probe = sprd_eic_probe, 705 .driver = { 706 .name = "sprd-eic", 707 .of_match_table = sprd_eic_of_match, 708 }, 709}; 710 711module_platform_driver(sprd_eic_driver); 712 713MODULE_DESCRIPTION("Spreadtrum EIC driver"); 714MODULE_LICENSE("GPL v2"); 715