1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Driver Header File for FPGA Device Feature List (DFL) Support 4 * 5 * Copyright (C) 2017-2018 Intel Corporation, Inc. 6 * 7 * Authors: 8 * Kang Luwei <luwei.kang@intel.com> 9 * Zhang Yi <yi.z.zhang@intel.com> 10 * Wu Hao <hao.wu@intel.com> 11 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 12 */ 13 14#ifndef __FPGA_DFL_H 15#define __FPGA_DFL_H 16 17#include <linux/bitfield.h> 18#include <linux/cdev.h> 19#include <linux/delay.h> 20#include <linux/eventfd.h> 21#include <linux/fs.h> 22#include <linux/interrupt.h> 23#include <linux/iopoll.h> 24#include <linux/io-64-nonatomic-lo-hi.h> 25#include <linux/platform_device.h> 26#include <linux/slab.h> 27#include <linux/uuid.h> 28#include <linux/fpga/fpga-region.h> 29 30/* maximum supported number of ports */ 31#define MAX_DFL_FPGA_PORT_NUM 4 32/* plus one for fme device */ 33#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1) 34 35/* Reserved 0xfe for Header Group Register and 0xff for AFU */ 36#define FEATURE_ID_FIU_HEADER 0xfe 37#define FEATURE_ID_AFU 0xff 38 39#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 40#define FME_FEATURE_ID_THERMAL_MGMT 0x1 41#define FME_FEATURE_ID_POWER_MGMT 0x2 42#define FME_FEATURE_ID_GLOBAL_IPERF 0x3 43#define FME_FEATURE_ID_GLOBAL_ERR 0x4 44#define FME_FEATURE_ID_PR_MGMT 0x5 45#define FME_FEATURE_ID_HSSI 0x6 46#define FME_FEATURE_ID_GLOBAL_DPERF 0x7 47 48#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER 49#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU 50#define PORT_FEATURE_ID_ERROR 0x10 51#define PORT_FEATURE_ID_UMSG 0x11 52#define PORT_FEATURE_ID_UINT 0x12 53#define PORT_FEATURE_ID_STP 0x13 54 55/* 56 * Device Feature Header Register Set 57 * 58 * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. 59 * For AFUs, they have DFH + GUID as common header registers. 60 * For private features, they only have DFH register as common header. 61 */ 62#define DFH 0x0 63#define GUID_L 0x8 64#define GUID_H 0x10 65#define NEXT_AFU 0x18 66 67#define DFH_SIZE 0x8 68 69/* Device Feature Header Register Bitfield */ 70#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ 71#define DFH_ID_FIU_FME 0 72#define DFH_ID_FIU_PORT 1 73#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ 74#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ 75#define DFH_EOL BIT_ULL(40) /* End of list */ 76#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ 77#define DFH_TYPE_AFU 1 78#define DFH_TYPE_PRIVATE 3 79#define DFH_TYPE_FIU 4 80 81/* Next AFU Register Bitfield */ 82#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ 83 84/* FME Header Register Set */ 85#define FME_HDR_DFH DFH 86#define FME_HDR_GUID_L GUID_L 87#define FME_HDR_GUID_H GUID_H 88#define FME_HDR_NEXT_AFU NEXT_AFU 89#define FME_HDR_CAP 0x30 90#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) 91#define FME_HDR_BITSTREAM_ID 0x60 92#define FME_HDR_BITSTREAM_MD 0x68 93 94/* FME Fab Capability Register Bitfield */ 95#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ 96#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */ 97#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */ 98#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */ 99#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */ 100#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */ 101#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */ 102#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */ 103#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */ 104#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */ 105 106/* FME Port Offset Register Bitfield */ 107/* Offset to port device feature header */ 108#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0) 109/* PCI Bar ID for this port */ 110#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32) 111/* AFU MMIO access permission. 1 - VF, 0 - PF. */ 112#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55) 113#define FME_PORT_OFST_ACC_PF 0 114#define FME_PORT_OFST_ACC_VF 1 115#define FME_PORT_OFST_IMP BIT_ULL(60) 116 117/* FME Error Capability Register */ 118#define FME_ERROR_CAP 0x70 119 120/* FME Error Capability Register Bitfield */ 121#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ 122#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ 123 124/* PORT Header Register Set */ 125#define PORT_HDR_DFH DFH 126#define PORT_HDR_GUID_L GUID_L 127#define PORT_HDR_GUID_H GUID_H 128#define PORT_HDR_NEXT_AFU NEXT_AFU 129#define PORT_HDR_CAP 0x30 130#define PORT_HDR_CTRL 0x38 131#define PORT_HDR_STS 0x40 132#define PORT_HDR_USRCLK_CMD0 0x50 133#define PORT_HDR_USRCLK_CMD1 0x58 134#define PORT_HDR_USRCLK_STS0 0x60 135#define PORT_HDR_USRCLK_STS1 0x68 136 137/* Port Capability Register Bitfield */ 138#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ 139#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */ 140#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */ 141 142/* Port Control Register Bitfield */ 143#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */ 144/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ 145#define PORT_CTRL_LATENCY BIT_ULL(2) 146#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ 147 148/* Port Status Register Bitfield */ 149#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */ 150#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */ 151#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */ 152#define PORT_STS_PWR_STATE_NORM 0 153#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */ 154#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */ 155#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */ 156 157/* Port Error Capability Register */ 158#define PORT_ERROR_CAP 0x38 159 160/* Port Error Capability Register Bitfield */ 161#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ 162#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ 163 164/* Port Uint Capability Register */ 165#define PORT_UINT_CAP 0x8 166 167/* Port Uint Capability Register Bitfield */ 168#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */ 169#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */ 170 171/** 172 * struct dfl_fpga_port_ops - port ops 173 * 174 * @name: name of this port ops, to match with port platform device. 175 * @owner: pointer to the module which owns this port ops. 176 * @node: node to link port ops to global list. 177 * @get_id: get port id from hardware. 178 * @enable_set: enable/disable the port. 179 */ 180struct dfl_fpga_port_ops { 181 const char *name; 182 struct module *owner; 183 struct list_head node; 184 int (*get_id)(struct platform_device *pdev); 185 int (*enable_set)(struct platform_device *pdev, bool enable); 186}; 187 188void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops); 189void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops); 190struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev); 191void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops); 192int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id); 193 194/** 195 * struct dfl_feature_id - dfl private feature id 196 * 197 * @id: unique dfl private feature id. 198 */ 199struct dfl_feature_id { 200 u16 id; 201}; 202 203/** 204 * struct dfl_feature_driver - dfl private feature driver 205 * 206 * @id_table: id_table for dfl private features supported by this driver. 207 * @ops: ops of this dfl private feature driver. 208 */ 209struct dfl_feature_driver { 210 const struct dfl_feature_id *id_table; 211 const struct dfl_feature_ops *ops; 212}; 213 214/** 215 * struct dfl_feature_irq_ctx - dfl private feature interrupt context 216 * 217 * @irq: Linux IRQ number of this interrupt. 218 * @trigger: eventfd context to signal when interrupt happens. 219 * @name: irq name needed when requesting irq. 220 */ 221struct dfl_feature_irq_ctx { 222 int irq; 223 struct eventfd_ctx *trigger; 224 char *name; 225}; 226 227/** 228 * struct dfl_feature - sub feature of the feature devices 229 * 230 * @dev: ptr to pdev of the feature device which has the sub feature. 231 * @id: sub feature id. 232 * @resource_index: each sub feature has one mmio resource for its registers. 233 * this index is used to find its mmio resource from the 234 * feature dev (platform device)'s reources. 235 * @ioaddr: mapped mmio resource address. 236 * @irq_ctx: interrupt context list. 237 * @nr_irqs: number of interrupt contexts. 238 * @ops: ops of this sub feature. 239 * @ddev: ptr to the dfl device of this sub feature. 240 * @priv: priv data of this feature. 241 */ 242struct dfl_feature { 243 struct platform_device *dev; 244 u16 id; 245 int resource_index; 246 void __iomem *ioaddr; 247 struct dfl_feature_irq_ctx *irq_ctx; 248 unsigned int nr_irqs; 249 const struct dfl_feature_ops *ops; 250 struct dfl_device *ddev; 251 void *priv; 252}; 253 254#define FEATURE_DEV_ID_UNUSED (-1) 255 256/** 257 * struct dfl_feature_platform_data - platform data for feature devices 258 * 259 * @node: node to link feature devs to container device's port_dev_list. 260 * @lock: mutex to protect platform data. 261 * @cdev: cdev of feature dev. 262 * @dev: ptr to platform device linked with this platform data. 263 * @dfl_cdev: ptr to container device. 264 * @id: id used for this feature device. 265 * @disable_count: count for port disable. 266 * @excl_open: set on feature device exclusive open. 267 * @open_count: count for feature device open. 268 * @num: number for sub features. 269 * @private: ptr to feature dev private data. 270 * @features: sub features of this feature dev. 271 */ 272struct dfl_feature_platform_data { 273 struct list_head node; 274 struct mutex lock; 275 struct cdev cdev; 276 struct platform_device *dev; 277 struct dfl_fpga_cdev *dfl_cdev; 278 int id; 279 unsigned int disable_count; 280 bool excl_open; 281 int open_count; 282 void *private; 283 int num; 284 struct dfl_feature features[]; 285}; 286 287static inline 288int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, 289 bool excl) 290{ 291 if (pdata->excl_open) 292 return -EBUSY; 293 294 if (excl) { 295 if (pdata->open_count) 296 return -EBUSY; 297 298 pdata->excl_open = true; 299 } 300 pdata->open_count++; 301 302 return 0; 303} 304 305static inline 306void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) 307{ 308 pdata->excl_open = false; 309 310 if (WARN_ON(pdata->open_count <= 0)) 311 return; 312 313 pdata->open_count--; 314} 315 316static inline 317int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) 318{ 319 return pdata->open_count; 320} 321 322static inline 323void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata, 324 void *private) 325{ 326 pdata->private = private; 327} 328 329static inline 330void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata) 331{ 332 return pdata->private; 333} 334 335struct dfl_feature_ops { 336 int (*init)(struct platform_device *pdev, struct dfl_feature *feature); 337 void (*uinit)(struct platform_device *pdev, 338 struct dfl_feature *feature); 339 long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature, 340 unsigned int cmd, unsigned long arg); 341}; 342 343#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme" 344#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port" 345 346void dfl_fpga_dev_feature_uinit(struct platform_device *pdev); 347int dfl_fpga_dev_feature_init(struct platform_device *pdev, 348 struct dfl_feature_driver *feature_drvs); 349 350int dfl_fpga_dev_ops_register(struct platform_device *pdev, 351 const struct file_operations *fops, 352 struct module *owner); 353void dfl_fpga_dev_ops_unregister(struct platform_device *pdev); 354 355static inline 356struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode) 357{ 358 struct dfl_feature_platform_data *pdata; 359 360 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data, 361 cdev); 362 return pdata->dev; 363} 364 365#define dfl_fpga_dev_for_each_feature(pdata, feature) \ 366 for ((feature) = (pdata)->features; \ 367 (feature) < (pdata)->features + (pdata)->num; (feature)++) 368 369static inline 370struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id) 371{ 372 struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); 373 struct dfl_feature *feature; 374 375 dfl_fpga_dev_for_each_feature(pdata, feature) 376 if (feature->id == id) 377 return feature; 378 379 return NULL; 380} 381 382static inline 383void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id) 384{ 385 struct dfl_feature *feature = dfl_get_feature_by_id(dev, id); 386 387 if (feature && feature->ioaddr) 388 return feature->ioaddr; 389 390 WARN_ON(1); 391 return NULL; 392} 393 394static inline bool is_dfl_feature_present(struct device *dev, u16 id) 395{ 396 return !!dfl_get_feature_ioaddr_by_id(dev, id); 397} 398 399static inline 400struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata) 401{ 402 return pdata->dev->dev.parent->parent; 403} 404 405static inline bool dfl_feature_is_fme(void __iomem *base) 406{ 407 u64 v = readq(base + DFH); 408 409 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && 410 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); 411} 412 413static inline bool dfl_feature_is_port(void __iomem *base) 414{ 415 u64 v = readq(base + DFH); 416 417 return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && 418 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); 419} 420 421static inline u8 dfl_feature_revision(void __iomem *base) 422{ 423 return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); 424} 425 426/** 427 * struct dfl_fpga_enum_info - DFL FPGA enumeration information 428 * 429 * @dev: parent device. 430 * @dfls: list of device feature lists. 431 * @nr_irqs: number of irqs for all feature devices. 432 * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers. 433 */ 434struct dfl_fpga_enum_info { 435 struct device *dev; 436 struct list_head dfls; 437 unsigned int nr_irqs; 438 int *irq_table; 439}; 440 441/** 442 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info 443 * 444 * @start: base address of this device feature list. 445 * @len: size of this device feature list. 446 * @node: node in list of device feature lists. 447 */ 448struct dfl_fpga_enum_dfl { 449 resource_size_t start; 450 resource_size_t len; 451 struct list_head node; 452}; 453 454struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev); 455int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, 456 resource_size_t start, resource_size_t len); 457int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, 458 unsigned int nr_irqs, int *irq_table); 459void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); 460 461/** 462 * struct dfl_fpga_cdev - container device of DFL based FPGA 463 * 464 * @parent: parent device of this container device. 465 * @region: base fpga region. 466 * @fme_dev: FME feature device under this container device. 467 * @lock: mutex lock to protect the port device list. 468 * @port_dev_list: list of all port feature devices under this container device. 469 * @released_port_num: released port number under this container device. 470 */ 471struct dfl_fpga_cdev { 472 struct device *parent; 473 struct fpga_region *region; 474 struct device *fme_dev; 475 struct mutex lock; 476 struct list_head port_dev_list; 477 int released_port_num; 478}; 479 480struct dfl_fpga_cdev * 481dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info); 482void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev); 483 484/* 485 * need to drop the device reference with put_device() after use port platform 486 * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port 487 * functions. 488 */ 489struct platform_device * 490__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, 491 int (*match)(struct platform_device *, void *)); 492 493static inline struct platform_device * 494dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, 495 int (*match)(struct platform_device *, void *)) 496{ 497 struct platform_device *pdev; 498 499 mutex_lock(&cdev->lock); 500 pdev = __dfl_fpga_cdev_find_port(cdev, data, match); 501 mutex_unlock(&cdev->lock); 502 503 return pdev; 504} 505 506int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id); 507int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id); 508void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev); 509int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf); 510int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start, 511 unsigned int count, int32_t *fds); 512long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev, 513 struct dfl_feature *feature, 514 unsigned long arg); 515long dfl_feature_ioctl_set_irq(struct platform_device *pdev, 516 struct dfl_feature *feature, 517 unsigned long arg); 518 519/** 520 * enum dfl_id_type - define the DFL FIU types 521 */ 522enum dfl_id_type { 523 FME_ID, 524 PORT_ID, 525 DFL_ID_MAX, 526}; 527 528/** 529 * struct dfl_device_id - dfl device identifier 530 * @type: contains 4 bits DFL FIU type of the device. See enum dfl_id_type. 531 * @feature_id: contains 12 bits feature identifier local to its DFL FIU type. 532 * @driver_data: driver specific data. 533 */ 534struct dfl_device_id { 535 u8 type; 536 u16 feature_id; 537 unsigned long driver_data; 538}; 539 540/** 541 * struct dfl_device - represent an dfl device on dfl bus 542 * 543 * @dev: generic device interface. 544 * @id: id of the dfl device. 545 * @type: type of DFL FIU of the device. See enum dfl_id_type. 546 * @feature_id: 16 bits feature identifier local to its DFL FIU type. 547 * @mmio_res: mmio resource of this dfl device. 548 * @irqs: list of Linux IRQ numbers of this dfl device. 549 * @num_irqs: number of IRQs supported by this dfl device. 550 * @cdev: pointer to DFL FPGA container device this dfl device belongs to. 551 * @id_entry: matched id entry in dfl driver's id table. 552 */ 553struct dfl_device { 554 struct device dev; 555 int id; 556 u8 type; 557 u16 feature_id; 558 struct resource mmio_res; 559 int *irqs; 560 unsigned int num_irqs; 561 struct dfl_fpga_cdev *cdev; 562 const struct dfl_device_id *id_entry; 563}; 564 565/** 566 * struct dfl_driver - represent an dfl device driver 567 * 568 * @drv: driver model structure. 569 * @id_table: pointer to table of device IDs the driver is interested in. 570 * { } member terminated. 571 * @probe: mandatory callback for device binding. 572 * @remove: callback for device unbinding. 573 */ 574struct dfl_driver { 575 struct device_driver drv; 576 const struct dfl_device_id *id_table; 577 578 int (*probe)(struct dfl_device *dfl_dev); 579 void (*remove)(struct dfl_device *dfl_dev); 580}; 581 582#define to_dfl_dev(d) container_of(d, struct dfl_device, dev) 583#define to_dfl_drv(d) container_of(d, struct dfl_driver, drv) 584 585/* 586 * use a macro to avoid include chaining to get THIS_MODULE. 587 */ 588#define dfl_driver_register(drv) \ 589 __dfl_driver_register(drv, THIS_MODULE) 590int __dfl_driver_register(struct dfl_driver *dfl_drv, struct module *owner); 591void dfl_driver_unregister(struct dfl_driver *dfl_drv); 592 593/* 594 * module_dfl_driver() - Helper macro for drivers that don't do 595 * anything special in module init/exit. This eliminates a lot of 596 * boilerplate. Each module may only use this macro once, and 597 * calling it replaces module_init() and module_exit(). 598 */ 599#define module_dfl_driver(__dfl_driver) \ 600 module_driver(__dfl_driver, dfl_driver_register, \ 601 dfl_driver_unregister) 602 603#endif /* __FPGA_DFL_H */ 604