18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * FPGA Region Driver for FPGA Management Engine (FME)
48c2ecf20Sopenharmony_ci *
58c2ecf20Sopenharmony_ci * Copyright (C) 2017-2018 Intel Corporation, Inc.
68c2ecf20Sopenharmony_ci *
78c2ecf20Sopenharmony_ci * Authors:
88c2ecf20Sopenharmony_ci *   Wu Hao <hao.wu@intel.com>
98c2ecf20Sopenharmony_ci *   Joseph Grecco <joe.grecco@intel.com>
108c2ecf20Sopenharmony_ci *   Enno Luebbers <enno.luebbers@intel.com>
118c2ecf20Sopenharmony_ci *   Tim Whisonant <tim.whisonant@intel.com>
128c2ecf20Sopenharmony_ci *   Ananda Ravuri <ananda.ravuri@intel.com>
138c2ecf20Sopenharmony_ci *   Henry Mitchel <henry.mitchel@intel.com>
148c2ecf20Sopenharmony_ci */
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_ci#include <linux/module.h>
178c2ecf20Sopenharmony_ci#include <linux/fpga/fpga-mgr.h>
188c2ecf20Sopenharmony_ci#include <linux/fpga/fpga-region.h>
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci#include "dfl-fme-pr.h"
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_cistatic int fme_region_get_bridges(struct fpga_region *region)
238c2ecf20Sopenharmony_ci{
248c2ecf20Sopenharmony_ci	struct dfl_fme_region_pdata *pdata = region->priv;
258c2ecf20Sopenharmony_ci	struct device *dev = &pdata->br->dev;
268c2ecf20Sopenharmony_ci
278c2ecf20Sopenharmony_ci	return fpga_bridge_get_to_list(dev, region->info, &region->bridge_list);
288c2ecf20Sopenharmony_ci}
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_cistatic int fme_region_probe(struct platform_device *pdev)
318c2ecf20Sopenharmony_ci{
328c2ecf20Sopenharmony_ci	struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev);
338c2ecf20Sopenharmony_ci	struct device *dev = &pdev->dev;
348c2ecf20Sopenharmony_ci	struct fpga_region *region;
358c2ecf20Sopenharmony_ci	struct fpga_manager *mgr;
368c2ecf20Sopenharmony_ci	int ret;
378c2ecf20Sopenharmony_ci
388c2ecf20Sopenharmony_ci	mgr = fpga_mgr_get(&pdata->mgr->dev);
398c2ecf20Sopenharmony_ci	if (IS_ERR(mgr))
408c2ecf20Sopenharmony_ci		return -EPROBE_DEFER;
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci	region = devm_fpga_region_create(dev, mgr, fme_region_get_bridges);
438c2ecf20Sopenharmony_ci	if (!region) {
448c2ecf20Sopenharmony_ci		ret = -ENOMEM;
458c2ecf20Sopenharmony_ci		goto eprobe_mgr_put;
468c2ecf20Sopenharmony_ci	}
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ci	region->priv = pdata;
498c2ecf20Sopenharmony_ci	region->compat_id = mgr->compat_id;
508c2ecf20Sopenharmony_ci	platform_set_drvdata(pdev, region);
518c2ecf20Sopenharmony_ci
528c2ecf20Sopenharmony_ci	ret = fpga_region_register(region);
538c2ecf20Sopenharmony_ci	if (ret)
548c2ecf20Sopenharmony_ci		goto eprobe_mgr_put;
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_ci	dev_dbg(dev, "DFL FME FPGA Region probed\n");
578c2ecf20Sopenharmony_ci
588c2ecf20Sopenharmony_ci	return 0;
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_cieprobe_mgr_put:
618c2ecf20Sopenharmony_ci	fpga_mgr_put(mgr);
628c2ecf20Sopenharmony_ci	return ret;
638c2ecf20Sopenharmony_ci}
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_cistatic int fme_region_remove(struct platform_device *pdev)
668c2ecf20Sopenharmony_ci{
678c2ecf20Sopenharmony_ci	struct fpga_region *region = platform_get_drvdata(pdev);
688c2ecf20Sopenharmony_ci	struct fpga_manager *mgr = region->mgr;
698c2ecf20Sopenharmony_ci
708c2ecf20Sopenharmony_ci	fpga_region_unregister(region);
718c2ecf20Sopenharmony_ci	fpga_mgr_put(mgr);
728c2ecf20Sopenharmony_ci
738c2ecf20Sopenharmony_ci	return 0;
748c2ecf20Sopenharmony_ci}
758c2ecf20Sopenharmony_ci
768c2ecf20Sopenharmony_cistatic struct platform_driver fme_region_driver = {
778c2ecf20Sopenharmony_ci	.driver	= {
788c2ecf20Sopenharmony_ci		.name    = DFL_FPGA_FME_REGION,
798c2ecf20Sopenharmony_ci	},
808c2ecf20Sopenharmony_ci	.probe   = fme_region_probe,
818c2ecf20Sopenharmony_ci	.remove  = fme_region_remove,
828c2ecf20Sopenharmony_ci};
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_cimodule_platform_driver(fme_region_driver);
858c2ecf20Sopenharmony_ci
868c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("FPGA Region for DFL FPGA Management Engine");
878c2ecf20Sopenharmony_ciMODULE_AUTHOR("Intel Corporation");
888c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2");
898c2ecf20Sopenharmony_ciMODULE_ALIAS("platform:dfl-fme-region");
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