18c2ecf20Sopenharmony_ci# SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci#
38c2ecf20Sopenharmony_ci# FPGA framework configuration
48c2ecf20Sopenharmony_ci#
58c2ecf20Sopenharmony_ci
68c2ecf20Sopenharmony_cimenuconfig FPGA
78c2ecf20Sopenharmony_ci	tristate "FPGA Configuration Framework"
88c2ecf20Sopenharmony_ci	help
98c2ecf20Sopenharmony_ci	  Say Y here if you want support for configuring FPGAs from the
108c2ecf20Sopenharmony_ci	  kernel.  The FPGA framework adds a FPGA manager class and FPGA
118c2ecf20Sopenharmony_ci	  manager drivers.
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ciif FPGA
148c2ecf20Sopenharmony_ci
158c2ecf20Sopenharmony_ciconfig FPGA_MGR_SOCFPGA
168c2ecf20Sopenharmony_ci	tristate "Altera SOCFPGA FPGA Manager"
178c2ecf20Sopenharmony_ci	depends on ARCH_SOCFPGA || COMPILE_TEST
188c2ecf20Sopenharmony_ci	help
198c2ecf20Sopenharmony_ci	  FPGA manager driver support for Altera SOCFPGA.
208c2ecf20Sopenharmony_ci
218c2ecf20Sopenharmony_ciconfig FPGA_MGR_SOCFPGA_A10
228c2ecf20Sopenharmony_ci	tristate "Altera SoCFPGA Arria10"
238c2ecf20Sopenharmony_ci	depends on ARCH_SOCFPGA || COMPILE_TEST
248c2ecf20Sopenharmony_ci	select REGMAP_MMIO
258c2ecf20Sopenharmony_ci	help
268c2ecf20Sopenharmony_ci	  FPGA manager driver support for Altera Arria10 SoCFPGA.
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ciconfig ALTERA_PR_IP_CORE
298c2ecf20Sopenharmony_ci	tristate "Altera Partial Reconfiguration IP Core"
308c2ecf20Sopenharmony_ci	help
318c2ecf20Sopenharmony_ci	  Core driver support for Altera Partial Reconfiguration IP component
328c2ecf20Sopenharmony_ci
338c2ecf20Sopenharmony_ciconfig ALTERA_PR_IP_CORE_PLAT
348c2ecf20Sopenharmony_ci	tristate "Platform support of Altera Partial Reconfiguration IP Core"
358c2ecf20Sopenharmony_ci	depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
368c2ecf20Sopenharmony_ci	help
378c2ecf20Sopenharmony_ci	  Platform driver support for Altera Partial Reconfiguration IP
388c2ecf20Sopenharmony_ci	  component
398c2ecf20Sopenharmony_ci
408c2ecf20Sopenharmony_ciconfig FPGA_MGR_ALTERA_PS_SPI
418c2ecf20Sopenharmony_ci	tristate "Altera FPGA Passive Serial over SPI"
428c2ecf20Sopenharmony_ci	depends on SPI
438c2ecf20Sopenharmony_ci	select BITREVERSE
448c2ecf20Sopenharmony_ci	help
458c2ecf20Sopenharmony_ci	  FPGA manager driver support for Altera Arria/Cyclone/Stratix
468c2ecf20Sopenharmony_ci	  using the passive serial interface over SPI.
478c2ecf20Sopenharmony_ci
488c2ecf20Sopenharmony_ciconfig FPGA_MGR_ALTERA_CVP
498c2ecf20Sopenharmony_ci	tristate "Altera CvP FPGA Manager"
508c2ecf20Sopenharmony_ci	depends on PCI
518c2ecf20Sopenharmony_ci	help
528c2ecf20Sopenharmony_ci	  FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
538c2ecf20Sopenharmony_ci	  Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
548c2ecf20Sopenharmony_ci
558c2ecf20Sopenharmony_ciconfig FPGA_MGR_ZYNQ_FPGA
568c2ecf20Sopenharmony_ci	tristate "Xilinx Zynq FPGA"
578c2ecf20Sopenharmony_ci	depends on ARCH_ZYNQ || COMPILE_TEST
588c2ecf20Sopenharmony_ci	help
598c2ecf20Sopenharmony_ci	  FPGA manager driver support for Xilinx Zynq FPGAs.
608c2ecf20Sopenharmony_ci
618c2ecf20Sopenharmony_ciconfig FPGA_MGR_STRATIX10_SOC
628c2ecf20Sopenharmony_ci	tristate "Intel Stratix10 SoC FPGA Manager"
638c2ecf20Sopenharmony_ci	depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
648c2ecf20Sopenharmony_ci	help
658c2ecf20Sopenharmony_ci	  FPGA manager driver support for the Intel Stratix10 SoC.
668c2ecf20Sopenharmony_ci
678c2ecf20Sopenharmony_ciconfig FPGA_MGR_XILINX_SPI
688c2ecf20Sopenharmony_ci	tristate "Xilinx Configuration over Slave Serial (SPI)"
698c2ecf20Sopenharmony_ci	depends on SPI
708c2ecf20Sopenharmony_ci	help
718c2ecf20Sopenharmony_ci	  FPGA manager driver support for Xilinx FPGA configuration
728c2ecf20Sopenharmony_ci	  over slave serial interface.
738c2ecf20Sopenharmony_ci
748c2ecf20Sopenharmony_ciconfig FPGA_MGR_ICE40_SPI
758c2ecf20Sopenharmony_ci	tristate "Lattice iCE40 SPI"
768c2ecf20Sopenharmony_ci	depends on OF && SPI
778c2ecf20Sopenharmony_ci	help
788c2ecf20Sopenharmony_ci	  FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
798c2ecf20Sopenharmony_ci
808c2ecf20Sopenharmony_ciconfig FPGA_MGR_MACHXO2_SPI
818c2ecf20Sopenharmony_ci	tristate "Lattice MachXO2 SPI"
828c2ecf20Sopenharmony_ci	depends on SPI
838c2ecf20Sopenharmony_ci	help
848c2ecf20Sopenharmony_ci	  FPGA manager driver support for Lattice MachXO2 configuration
858c2ecf20Sopenharmony_ci	  over slave SPI interface.
868c2ecf20Sopenharmony_ci
878c2ecf20Sopenharmony_ciconfig FPGA_MGR_TS73XX
888c2ecf20Sopenharmony_ci	tristate "Technologic Systems TS-73xx SBC FPGA Manager"
898c2ecf20Sopenharmony_ci	depends on ARCH_EP93XX && MACH_TS72XX
908c2ecf20Sopenharmony_ci	help
918c2ecf20Sopenharmony_ci	  FPGA manager driver support for the Altera Cyclone II FPGA
928c2ecf20Sopenharmony_ci	  present on the TS-73xx SBC boards.
938c2ecf20Sopenharmony_ci
948c2ecf20Sopenharmony_ciconfig FPGA_BRIDGE
958c2ecf20Sopenharmony_ci	tristate "FPGA Bridge Framework"
968c2ecf20Sopenharmony_ci	help
978c2ecf20Sopenharmony_ci	  Say Y here if you want to support bridges connected between host
988c2ecf20Sopenharmony_ci	  processors and FPGAs or between FPGAs.
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ciconfig SOCFPGA_FPGA_BRIDGE
1018c2ecf20Sopenharmony_ci	tristate "Altera SoCFPGA FPGA Bridges"
1028c2ecf20Sopenharmony_ci	depends on ARCH_SOCFPGA && FPGA_BRIDGE
1038c2ecf20Sopenharmony_ci	help
1048c2ecf20Sopenharmony_ci	  Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
1058c2ecf20Sopenharmony_ci	  devices.
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ciconfig ALTERA_FREEZE_BRIDGE
1088c2ecf20Sopenharmony_ci	tristate "Altera FPGA Freeze Bridge"
1098c2ecf20Sopenharmony_ci	depends on FPGA_BRIDGE && HAS_IOMEM
1108c2ecf20Sopenharmony_ci	help
1118c2ecf20Sopenharmony_ci	  Say Y to enable drivers for Altera FPGA Freeze bridges.  A
1128c2ecf20Sopenharmony_ci	  freeze bridge is a bridge that exists in the FPGA fabric to
1138c2ecf20Sopenharmony_ci	  isolate one region of the FPGA from the busses while that
1148c2ecf20Sopenharmony_ci	  region is being reprogrammed.
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ciconfig XILINX_PR_DECOUPLER
1178c2ecf20Sopenharmony_ci	tristate "Xilinx LogiCORE PR Decoupler"
1188c2ecf20Sopenharmony_ci	depends on FPGA_BRIDGE
1198c2ecf20Sopenharmony_ci	depends on HAS_IOMEM
1208c2ecf20Sopenharmony_ci	help
1218c2ecf20Sopenharmony_ci	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
1228c2ecf20Sopenharmony_ci	  The PR Decoupler exists in the FPGA fabric to isolate one
1238c2ecf20Sopenharmony_ci	  region of the FPGA from the busses while that region is
1248c2ecf20Sopenharmony_ci	  being reprogrammed during partial reconfig.
1258c2ecf20Sopenharmony_ci
1268c2ecf20Sopenharmony_ciconfig FPGA_REGION
1278c2ecf20Sopenharmony_ci	tristate "FPGA Region"
1288c2ecf20Sopenharmony_ci	depends on FPGA_BRIDGE
1298c2ecf20Sopenharmony_ci	help
1308c2ecf20Sopenharmony_ci	  FPGA Region common code.  A FPGA Region controls a FPGA Manager
1318c2ecf20Sopenharmony_ci	  and the FPGA Bridges associated with either a reconfigurable
1328c2ecf20Sopenharmony_ci	  region of an FPGA or a whole FPGA.
1338c2ecf20Sopenharmony_ci
1348c2ecf20Sopenharmony_ciconfig OF_FPGA_REGION
1358c2ecf20Sopenharmony_ci	tristate "FPGA Region Device Tree Overlay Support"
1368c2ecf20Sopenharmony_ci	depends on OF && FPGA_REGION
1378c2ecf20Sopenharmony_ci	help
1388c2ecf20Sopenharmony_ci	  Support for loading FPGA images by applying a Device Tree
1398c2ecf20Sopenharmony_ci	  overlay.
1408c2ecf20Sopenharmony_ci
1418c2ecf20Sopenharmony_ciconfig FPGA_DFL
1428c2ecf20Sopenharmony_ci	tristate "FPGA Device Feature List (DFL) support"
1438c2ecf20Sopenharmony_ci	select FPGA_BRIDGE
1448c2ecf20Sopenharmony_ci	select FPGA_REGION
1458c2ecf20Sopenharmony_ci	depends on HAS_IOMEM
1468c2ecf20Sopenharmony_ci	help
1478c2ecf20Sopenharmony_ci	  Device Feature List (DFL) defines a feature list structure that
1488c2ecf20Sopenharmony_ci	  creates a linked list of feature headers within the MMIO space
1498c2ecf20Sopenharmony_ci	  to provide an extensible way of adding features for FPGA.
1508c2ecf20Sopenharmony_ci	  Driver can walk through the feature headers to enumerate feature
1518c2ecf20Sopenharmony_ci	  devices (e.g. FPGA Management Engine, Port and Accelerator
1528c2ecf20Sopenharmony_ci	  Function Unit) and their private features for target FPGA devices.
1538c2ecf20Sopenharmony_ci
1548c2ecf20Sopenharmony_ci	  Select this option to enable common support for Field-Programmable
1558c2ecf20Sopenharmony_ci	  Gate Array (FPGA) solutions which implement Device Feature List.
1568c2ecf20Sopenharmony_ci	  It provides enumeration APIs and feature device infrastructure.
1578c2ecf20Sopenharmony_ci
1588c2ecf20Sopenharmony_ciconfig FPGA_DFL_FME
1598c2ecf20Sopenharmony_ci	tristate "FPGA DFL FME Driver"
1608c2ecf20Sopenharmony_ci	depends on FPGA_DFL && HWMON && PERF_EVENTS
1618c2ecf20Sopenharmony_ci	help
1628c2ecf20Sopenharmony_ci	  The FPGA Management Engine (FME) is a feature device implemented
1638c2ecf20Sopenharmony_ci	  under Device Feature List (DFL) framework. Select this option to
1648c2ecf20Sopenharmony_ci	  enable the platform device driver for FME which implements all
1658c2ecf20Sopenharmony_ci	  FPGA platform level management features. There shall be one FME
1668c2ecf20Sopenharmony_ci	  per DFL based FPGA device.
1678c2ecf20Sopenharmony_ci
1688c2ecf20Sopenharmony_ciconfig FPGA_DFL_FME_MGR
1698c2ecf20Sopenharmony_ci	tristate "FPGA DFL FME Manager Driver"
1708c2ecf20Sopenharmony_ci	depends on FPGA_DFL_FME && HAS_IOMEM
1718c2ecf20Sopenharmony_ci	help
1728c2ecf20Sopenharmony_ci	  Say Y to enable FPGA Manager driver for FPGA Management Engine.
1738c2ecf20Sopenharmony_ci
1748c2ecf20Sopenharmony_ciconfig FPGA_DFL_FME_BRIDGE
1758c2ecf20Sopenharmony_ci	tristate "FPGA DFL FME Bridge Driver"
1768c2ecf20Sopenharmony_ci	depends on FPGA_DFL_FME && HAS_IOMEM
1778c2ecf20Sopenharmony_ci	help
1788c2ecf20Sopenharmony_ci	  Say Y to enable FPGA Bridge driver for FPGA Management Engine.
1798c2ecf20Sopenharmony_ci
1808c2ecf20Sopenharmony_ciconfig FPGA_DFL_FME_REGION
1818c2ecf20Sopenharmony_ci	tristate "FPGA DFL FME Region Driver"
1828c2ecf20Sopenharmony_ci	depends on FPGA_DFL_FME && HAS_IOMEM
1838c2ecf20Sopenharmony_ci	help
1848c2ecf20Sopenharmony_ci	  Say Y to enable FPGA Region driver for FPGA Management Engine.
1858c2ecf20Sopenharmony_ci
1868c2ecf20Sopenharmony_ciconfig FPGA_DFL_AFU
1878c2ecf20Sopenharmony_ci	tristate "FPGA DFL AFU Driver"
1888c2ecf20Sopenharmony_ci	depends on FPGA_DFL
1898c2ecf20Sopenharmony_ci	help
1908c2ecf20Sopenharmony_ci	  This is the driver for FPGA Accelerated Function Unit (AFU) which
1918c2ecf20Sopenharmony_ci	  implements AFU and Port management features. A User AFU connects
1928c2ecf20Sopenharmony_ci	  to the FPGA infrastructure via a Port. There may be more than one
1938c2ecf20Sopenharmony_ci	  Port/AFU per DFL based FPGA device.
1948c2ecf20Sopenharmony_ci
1958c2ecf20Sopenharmony_ciconfig FPGA_DFL_PCI
1968c2ecf20Sopenharmony_ci	tristate "FPGA DFL PCIe Device Driver"
1978c2ecf20Sopenharmony_ci	depends on PCI && FPGA_DFL
1988c2ecf20Sopenharmony_ci	help
1998c2ecf20Sopenharmony_ci	  Select this option to enable PCIe driver for PCIe-based
2008c2ecf20Sopenharmony_ci	  Field-Programmable Gate Array (FPGA) solutions which implement
2018c2ecf20Sopenharmony_ci	  the Device Feature List (DFL). This driver provides interfaces
2028c2ecf20Sopenharmony_ci	  for userspace applications to configure, enumerate, open and access
2038c2ecf20Sopenharmony_ci	  FPGA accelerators on the FPGA DFL devices, enables system level
2048c2ecf20Sopenharmony_ci	  management functions such as FPGA partial reconfiguration, power
2058c2ecf20Sopenharmony_ci	  management and virtualization with DFL framework and DFL feature
2068c2ecf20Sopenharmony_ci	  device drivers.
2078c2ecf20Sopenharmony_ci
2088c2ecf20Sopenharmony_ci	  To compile this as a module, choose M here.
2098c2ecf20Sopenharmony_ci
2108c2ecf20Sopenharmony_ciconfig FPGA_MGR_ZYNQMP_FPGA
2118c2ecf20Sopenharmony_ci	tristate "Xilinx ZynqMP FPGA"
2128c2ecf20Sopenharmony_ci	depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
2138c2ecf20Sopenharmony_ci	help
2148c2ecf20Sopenharmony_ci	  FPGA manager driver support for Xilinx ZynqMP FPGAs.
2158c2ecf20Sopenharmony_ci	  This driver uses the processor configuration port(PCAP)
2168c2ecf20Sopenharmony_ci	  to configure the programmable logic(PL) through PS
2178c2ecf20Sopenharmony_ci	  on ZynqMP SoC.
2188c2ecf20Sopenharmony_ci
2198c2ecf20Sopenharmony_ciendif # FPGA
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