1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Driver for OHCI 1394 controllers 4 * 5 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> 6 */ 7 8#include <linux/bitops.h> 9#include <linux/bug.h> 10#include <linux/compiler.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/dma-mapping.h> 14#include <linux/firewire.h> 15#include <linux/firewire-constants.h> 16#include <linux/init.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/kernel.h> 20#include <linux/list.h> 21#include <linux/mm.h> 22#include <linux/module.h> 23#include <linux/moduleparam.h> 24#include <linux/mutex.h> 25#include <linux/pci.h> 26#include <linux/pci_ids.h> 27#include <linux/slab.h> 28#include <linux/spinlock.h> 29#include <linux/string.h> 30#include <linux/time.h> 31#include <linux/vmalloc.h> 32#include <linux/workqueue.h> 33 34#include <asm/byteorder.h> 35#include <asm/page.h> 36 37#ifdef CONFIG_PPC_PMAC 38#include <asm/pmac_feature.h> 39#endif 40 41#include "core.h" 42#include "ohci.h" 43 44#define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args) 45#define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) 46#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) 47 48#define DESCRIPTOR_OUTPUT_MORE 0 49#define DESCRIPTOR_OUTPUT_LAST (1 << 12) 50#define DESCRIPTOR_INPUT_MORE (2 << 12) 51#define DESCRIPTOR_INPUT_LAST (3 << 12) 52#define DESCRIPTOR_STATUS (1 << 11) 53#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) 54#define DESCRIPTOR_PING (1 << 7) 55#define DESCRIPTOR_YY (1 << 6) 56#define DESCRIPTOR_NO_IRQ (0 << 4) 57#define DESCRIPTOR_IRQ_ERROR (1 << 4) 58#define DESCRIPTOR_IRQ_ALWAYS (3 << 4) 59#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) 60#define DESCRIPTOR_WAIT (3 << 0) 61 62#define DESCRIPTOR_CMD (0xf << 12) 63 64struct descriptor { 65 __le16 req_count; 66 __le16 control; 67 __le32 data_address; 68 __le32 branch_address; 69 __le16 res_count; 70 __le16 transfer_status; 71} __attribute__((aligned(16))); 72 73#define CONTROL_SET(regs) (regs) 74#define CONTROL_CLEAR(regs) ((regs) + 4) 75#define COMMAND_PTR(regs) ((regs) + 12) 76#define CONTEXT_MATCH(regs) ((regs) + 16) 77 78#define AR_BUFFER_SIZE (32*1024) 79#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) 80/* we need at least two pages for proper list management */ 81#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) 82 83#define MAX_ASYNC_PAYLOAD 4096 84#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) 85#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) 86 87struct ar_context { 88 struct fw_ohci *ohci; 89 struct page *pages[AR_BUFFERS]; 90 void *buffer; 91 struct descriptor *descriptors; 92 dma_addr_t descriptors_bus; 93 void *pointer; 94 unsigned int last_buffer_index; 95 u32 regs; 96 struct tasklet_struct tasklet; 97}; 98 99struct context; 100 101typedef int (*descriptor_callback_t)(struct context *ctx, 102 struct descriptor *d, 103 struct descriptor *last); 104 105/* 106 * A buffer that contains a block of DMA-able coherent memory used for 107 * storing a portion of a DMA descriptor program. 108 */ 109struct descriptor_buffer { 110 struct list_head list; 111 dma_addr_t buffer_bus; 112 size_t buffer_size; 113 size_t used; 114 struct descriptor buffer[]; 115}; 116 117struct context { 118 struct fw_ohci *ohci; 119 u32 regs; 120 int total_allocation; 121 u32 current_bus; 122 bool running; 123 bool flushing; 124 125 /* 126 * List of page-sized buffers for storing DMA descriptors. 127 * Head of list contains buffers in use and tail of list contains 128 * free buffers. 129 */ 130 struct list_head buffer_list; 131 132 /* 133 * Pointer to a buffer inside buffer_list that contains the tail 134 * end of the current DMA program. 135 */ 136 struct descriptor_buffer *buffer_tail; 137 138 /* 139 * The descriptor containing the branch address of the first 140 * descriptor that has not yet been filled by the device. 141 */ 142 struct descriptor *last; 143 144 /* 145 * The last descriptor block in the DMA program. It contains the branch 146 * address that must be updated upon appending a new descriptor. 147 */ 148 struct descriptor *prev; 149 int prev_z; 150 151 descriptor_callback_t callback; 152 153 struct tasklet_struct tasklet; 154}; 155 156#define IT_HEADER_SY(v) ((v) << 0) 157#define IT_HEADER_TCODE(v) ((v) << 4) 158#define IT_HEADER_CHANNEL(v) ((v) << 8) 159#define IT_HEADER_TAG(v) ((v) << 14) 160#define IT_HEADER_SPEED(v) ((v) << 16) 161#define IT_HEADER_DATA_LENGTH(v) ((v) << 16) 162 163struct iso_context { 164 struct fw_iso_context base; 165 struct context context; 166 void *header; 167 size_t header_length; 168 unsigned long flushing_completions; 169 u32 mc_buffer_bus; 170 u16 mc_completed; 171 u16 last_timestamp; 172 u8 sync; 173 u8 tags; 174}; 175 176#define CONFIG_ROM_SIZE 1024 177 178struct fw_ohci { 179 struct fw_card card; 180 181 __iomem char *registers; 182 int node_id; 183 int generation; 184 int request_generation; /* for timestamping incoming requests */ 185 unsigned quirks; 186 unsigned int pri_req_max; 187 u32 bus_time; 188 bool bus_time_running; 189 bool is_root; 190 bool csr_state_setclear_abdicate; 191 int n_ir; 192 int n_it; 193 /* 194 * Spinlock for accessing fw_ohci data. Never call out of 195 * this driver with this lock held. 196 */ 197 spinlock_t lock; 198 199 struct mutex phy_reg_mutex; 200 201 void *misc_buffer; 202 dma_addr_t misc_buffer_bus; 203 204 struct ar_context ar_request_ctx; 205 struct ar_context ar_response_ctx; 206 struct context at_request_ctx; 207 struct context at_response_ctx; 208 209 u32 it_context_support; 210 u32 it_context_mask; /* unoccupied IT contexts */ 211 struct iso_context *it_context_list; 212 u64 ir_context_channels; /* unoccupied channels */ 213 u32 ir_context_support; 214 u32 ir_context_mask; /* unoccupied IR contexts */ 215 struct iso_context *ir_context_list; 216 u64 mc_channels; /* channels in use by the multichannel IR context */ 217 bool mc_allocated; 218 219 __be32 *config_rom; 220 dma_addr_t config_rom_bus; 221 __be32 *next_config_rom; 222 dma_addr_t next_config_rom_bus; 223 __be32 next_header; 224 225 __le32 *self_id; 226 dma_addr_t self_id_bus; 227 struct work_struct bus_reset_work; 228 229 u32 self_id_buffer[512]; 230}; 231 232static struct workqueue_struct *selfid_workqueue; 233 234static inline struct fw_ohci *fw_ohci(struct fw_card *card) 235{ 236 return container_of(card, struct fw_ohci, card); 237} 238 239#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 240#define IR_CONTEXT_BUFFER_FILL 0x80000000 241#define IR_CONTEXT_ISOCH_HEADER 0x40000000 242#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 243#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 244#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 245 246#define CONTEXT_RUN 0x8000 247#define CONTEXT_WAKE 0x1000 248#define CONTEXT_DEAD 0x0800 249#define CONTEXT_ACTIVE 0x0400 250 251#define OHCI1394_MAX_AT_REQ_RETRIES 0xf 252#define OHCI1394_MAX_AT_RESP_RETRIES 0x2 253#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 254 255#define OHCI1394_REGISTER_SIZE 0x800 256#define OHCI1394_PCI_HCI_Control 0x40 257#define SELF_ID_BUF_SIZE 0x800 258#define OHCI_TCODE_PHY_PACKET 0x0e 259#define OHCI_VERSION_1_1 0x010010 260 261static char ohci_driver_name[] = KBUILD_MODNAME; 262 263#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd 264#define PCI_DEVICE_ID_AGERE_FW643 0x5901 265#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001 266#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 267#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 268#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020 269#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025 270#define PCI_DEVICE_ID_VIA_VT630X 0x3044 271#define PCI_REV_ID_VIA_VT6306 0x46 272#define PCI_DEVICE_ID_VIA_VT6315 0x3403 273 274#define QUIRK_CYCLE_TIMER 0x1 275#define QUIRK_RESET_PACKET 0x2 276#define QUIRK_BE_HEADERS 0x4 277#define QUIRK_NO_1394A 0x8 278#define QUIRK_NO_MSI 0x10 279#define QUIRK_TI_SLLZ059 0x20 280#define QUIRK_IR_WAKE 0x40 281 282// On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia 283// ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register 284// (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not 285// clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register, 286// while it is probable due to detection of any type of PCIe error. 287#define QUIRK_REBOOT_BY_CYCLE_TIMER_READ 0x80000000 288 289#if IS_ENABLED(CONFIG_X86) 290 291static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) 292{ 293 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); 294} 295 296#define PCI_DEVICE_ID_ASMEDIA_ASM108X 0x1080 297 298static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev) 299{ 300 const struct pci_dev *pcie_to_pci_bridge; 301 302 // Detect any type of AMD Ryzen machine. 303 if (!static_cpu_has(X86_FEATURE_ZEN)) 304 return false; 305 306 // Detect VIA VT6306/6307/6308. 307 if (pdev->vendor != PCI_VENDOR_ID_VIA) 308 return false; 309 if (pdev->device != PCI_DEVICE_ID_VIA_VT630X) 310 return false; 311 312 // Detect Asmedia ASM1083/1085. 313 pcie_to_pci_bridge = pdev->bus->self; 314 if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA) 315 return false; 316 if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X) 317 return false; 318 319 return true; 320} 321 322#else 323#define has_reboot_by_cycle_timer_read_quirk(ohci) false 324#define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev) false 325#endif 326 327/* In case of multiple matches in ohci_quirks[], only the first one is used. */ 328static const struct { 329 unsigned short vendor, device, revision, flags; 330} ohci_quirks[] = { 331 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, 332 QUIRK_CYCLE_TIMER}, 333 334 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, 335 QUIRK_BE_HEADERS}, 336 337 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, 338 QUIRK_NO_MSI}, 339 340 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID, 341 QUIRK_RESET_PACKET}, 342 343 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, 344 QUIRK_NO_MSI}, 345 346 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, 347 QUIRK_CYCLE_TIMER}, 348 349 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID, 350 QUIRK_NO_MSI}, 351 352 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, 353 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 354 355 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, 356 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, 357 358 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID, 359 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 360 361 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID, 362 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059}, 363 364 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, 365 QUIRK_RESET_PACKET}, 366 367 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306, 368 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE}, 369 370 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0, 371 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI}, 372 373 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID, 374 QUIRK_NO_MSI}, 375 376 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, 377 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, 378}; 379 380/* This overrides anything that was found in ohci_quirks[]. */ 381static int param_quirks; 382module_param_named(quirks, param_quirks, int, 0644); 383MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" 384 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) 385 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) 386 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS) 387 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) 388 ", disable MSI = " __stringify(QUIRK_NO_MSI) 389 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059) 390 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE) 391 ")"); 392 393#define OHCI_PARAM_DEBUG_AT_AR 1 394#define OHCI_PARAM_DEBUG_SELFIDS 2 395#define OHCI_PARAM_DEBUG_IRQS 4 396#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ 397 398static int param_debug; 399module_param_named(debug, param_debug, int, 0644); 400MODULE_PARM_DESC(debug, "Verbose logging (default = 0" 401 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) 402 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) 403 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) 404 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) 405 ", or a combination, or all = -1)"); 406 407static bool param_remote_dma; 408module_param_named(remote_dma, param_remote_dma, bool, 0444); 409MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)"); 410 411static void log_irqs(struct fw_ohci *ohci, u32 evt) 412{ 413 if (likely(!(param_debug & 414 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) 415 return; 416 417 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && 418 !(evt & OHCI1394_busReset)) 419 return; 420 421 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, 422 evt & OHCI1394_selfIDComplete ? " selfID" : "", 423 evt & OHCI1394_RQPkt ? " AR_req" : "", 424 evt & OHCI1394_RSPkt ? " AR_resp" : "", 425 evt & OHCI1394_reqTxComplete ? " AT_req" : "", 426 evt & OHCI1394_respTxComplete ? " AT_resp" : "", 427 evt & OHCI1394_isochRx ? " IR" : "", 428 evt & OHCI1394_isochTx ? " IT" : "", 429 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", 430 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", 431 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", 432 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", 433 evt & OHCI1394_regAccessFail ? " regAccessFail" : "", 434 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "", 435 evt & OHCI1394_busReset ? " busReset" : "", 436 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | 437 OHCI1394_RSPkt | OHCI1394_reqTxComplete | 438 OHCI1394_respTxComplete | OHCI1394_isochRx | 439 OHCI1394_isochTx | OHCI1394_postedWriteErr | 440 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | 441 OHCI1394_cycleInconsistent | 442 OHCI1394_regAccessFail | OHCI1394_busReset) 443 ? " ?" : ""); 444} 445 446static const char *speed[] = { 447 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", 448}; 449static const char *power[] = { 450 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", 451 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", 452}; 453static const char port[] = { '.', '-', 'p', 'c', }; 454 455static char _p(u32 *s, int shift) 456{ 457 return port[*s >> shift & 3]; 458} 459 460static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count) 461{ 462 u32 *s; 463 464 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) 465 return; 466 467 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n", 468 self_id_count, generation, ohci->node_id); 469 470 for (s = ohci->self_id_buffer; self_id_count--; ++s) 471 if ((*s & 1 << 23) == 0) 472 ohci_notice(ohci, 473 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n", 474 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), 475 speed[*s >> 14 & 3], *s >> 16 & 63, 476 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", 477 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); 478 else 479 ohci_notice(ohci, 480 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", 481 *s, *s >> 24 & 63, 482 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), 483 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); 484} 485 486static const char *evts[] = { 487 [0x00] = "evt_no_status", [0x01] = "-reserved-", 488 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", 489 [0x04] = "evt_underrun", [0x05] = "evt_overrun", 490 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", 491 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", 492 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", 493 [0x0c] = "-reserved-", [0x0d] = "-reserved-", 494 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", 495 [0x10] = "-reserved-", [0x11] = "ack_complete", 496 [0x12] = "ack_pending ", [0x13] = "-reserved-", 497 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", 498 [0x16] = "ack_busy_B", [0x17] = "-reserved-", 499 [0x18] = "-reserved-", [0x19] = "-reserved-", 500 [0x1a] = "-reserved-", [0x1b] = "ack_tardy", 501 [0x1c] = "-reserved-", [0x1d] = "ack_data_error", 502 [0x1e] = "ack_type_error", [0x1f] = "-reserved-", 503 [0x20] = "pending/cancelled", 504}; 505static const char *tcodes[] = { 506 [0x0] = "QW req", [0x1] = "BW req", 507 [0x2] = "W resp", [0x3] = "-reserved-", 508 [0x4] = "QR req", [0x5] = "BR req", 509 [0x6] = "QR resp", [0x7] = "BR resp", 510 [0x8] = "cycle start", [0x9] = "Lk req", 511 [0xa] = "async stream packet", [0xb] = "Lk resp", 512 [0xc] = "-reserved-", [0xd] = "-reserved-", 513 [0xe] = "link internal", [0xf] = "-reserved-", 514}; 515 516static void log_ar_at_event(struct fw_ohci *ohci, 517 char dir, int speed, u32 *header, int evt) 518{ 519 int tcode = header[0] >> 4 & 0xf; 520 char specific[12]; 521 522 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) 523 return; 524 525 if (unlikely(evt >= ARRAY_SIZE(evts))) 526 evt = 0x1f; 527 528 if (evt == OHCI1394_evt_bus_reset) { 529 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n", 530 dir, (header[2] >> 16) & 0xff); 531 return; 532 } 533 534 switch (tcode) { 535 case 0x0: case 0x6: case 0x8: 536 snprintf(specific, sizeof(specific), " = %08x", 537 be32_to_cpu((__force __be32)header[3])); 538 break; 539 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: 540 snprintf(specific, sizeof(specific), " %x,%x", 541 header[3] >> 16, header[3] & 0xffff); 542 break; 543 default: 544 specific[0] = '\0'; 545 } 546 547 switch (tcode) { 548 case 0xa: 549 ohci_notice(ohci, "A%c %s, %s\n", 550 dir, evts[evt], tcodes[tcode]); 551 break; 552 case 0xe: 553 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n", 554 dir, evts[evt], header[1], header[2]); 555 break; 556 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: 557 ohci_notice(ohci, 558 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n", 559 dir, speed, header[0] >> 10 & 0x3f, 560 header[1] >> 16, header[0] >> 16, evts[evt], 561 tcodes[tcode], header[1] & 0xffff, header[2], specific); 562 break; 563 default: 564 ohci_notice(ohci, 565 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n", 566 dir, speed, header[0] >> 10 & 0x3f, 567 header[1] >> 16, header[0] >> 16, evts[evt], 568 tcodes[tcode], specific); 569 } 570} 571 572static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) 573{ 574 writel(data, ohci->registers + offset); 575} 576 577static inline u32 reg_read(const struct fw_ohci *ohci, int offset) 578{ 579 return readl(ohci->registers + offset); 580} 581 582static inline void flush_writes(const struct fw_ohci *ohci) 583{ 584 /* Do a dummy read to flush writes. */ 585 reg_read(ohci, OHCI1394_Version); 586} 587 588/* 589 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and 590 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex. 591 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg() 592 * directly. Exceptions are intrinsically serialized contexts like pci_probe. 593 */ 594static int read_phy_reg(struct fw_ohci *ohci, int addr) 595{ 596 u32 val; 597 int i; 598 599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 600 for (i = 0; i < 3 + 100; i++) { 601 val = reg_read(ohci, OHCI1394_PhyControl); 602 if (!~val) 603 return -ENODEV; /* Card was ejected. */ 604 605 if (val & OHCI1394_PhyControl_ReadDone) 606 return OHCI1394_PhyControl_ReadData(val); 607 608 /* 609 * Try a few times without waiting. Sleeping is necessary 610 * only when the link/PHY interface is busy. 611 */ 612 if (i >= 3) 613 msleep(1); 614 } 615 ohci_err(ohci, "failed to read phy reg %d\n", addr); 616 dump_stack(); 617 618 return -EBUSY; 619} 620 621static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) 622{ 623 int i; 624 625 reg_write(ohci, OHCI1394_PhyControl, 626 OHCI1394_PhyControl_Write(addr, val)); 627 for (i = 0; i < 3 + 100; i++) { 628 val = reg_read(ohci, OHCI1394_PhyControl); 629 if (!~val) 630 return -ENODEV; /* Card was ejected. */ 631 632 if (!(val & OHCI1394_PhyControl_WritePending)) 633 return 0; 634 635 if (i >= 3) 636 msleep(1); 637 } 638 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); 639 dump_stack(); 640 641 return -EBUSY; 642} 643 644static int update_phy_reg(struct fw_ohci *ohci, int addr, 645 int clear_bits, int set_bits) 646{ 647 int ret = read_phy_reg(ohci, addr); 648 if (ret < 0) 649 return ret; 650 651 /* 652 * The interrupt status bits are cleared by writing a one bit. 653 * Avoid clearing them unless explicitly requested in set_bits. 654 */ 655 if (addr == 5) 656 clear_bits |= PHY_INT_STATUS_BITS; 657 658 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); 659} 660 661static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) 662{ 663 int ret; 664 665 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); 666 if (ret < 0) 667 return ret; 668 669 return read_phy_reg(ohci, addr); 670} 671 672static int ohci_read_phy_reg(struct fw_card *card, int addr) 673{ 674 struct fw_ohci *ohci = fw_ohci(card); 675 int ret; 676 677 mutex_lock(&ohci->phy_reg_mutex); 678 ret = read_phy_reg(ohci, addr); 679 mutex_unlock(&ohci->phy_reg_mutex); 680 681 return ret; 682} 683 684static int ohci_update_phy_reg(struct fw_card *card, int addr, 685 int clear_bits, int set_bits) 686{ 687 struct fw_ohci *ohci = fw_ohci(card); 688 int ret; 689 690 mutex_lock(&ohci->phy_reg_mutex); 691 ret = update_phy_reg(ohci, addr, clear_bits, set_bits); 692 mutex_unlock(&ohci->phy_reg_mutex); 693 694 return ret; 695} 696 697static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) 698{ 699 return page_private(ctx->pages[i]); 700} 701 702static void ar_context_link_page(struct ar_context *ctx, unsigned int index) 703{ 704 struct descriptor *d; 705 706 d = &ctx->descriptors[index]; 707 d->branch_address &= cpu_to_le32(~0xf); 708 d->res_count = cpu_to_le16(PAGE_SIZE); 709 d->transfer_status = 0; 710 711 wmb(); /* finish init of new descriptors before branch_address update */ 712 d = &ctx->descriptors[ctx->last_buffer_index]; 713 d->branch_address |= cpu_to_le32(1); 714 715 ctx->last_buffer_index = index; 716 717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 718} 719 720static void ar_context_release(struct ar_context *ctx) 721{ 722 struct device *dev = ctx->ohci->card.device; 723 unsigned int i; 724 725 vunmap(ctx->buffer); 726 727 for (i = 0; i < AR_BUFFERS; i++) { 728 if (ctx->pages[i]) 729 dma_free_pages(dev, PAGE_SIZE, ctx->pages[i], 730 ar_buffer_bus(ctx, i), DMA_FROM_DEVICE); 731 } 732} 733 734static void ar_context_abort(struct ar_context *ctx, const char *error_msg) 735{ 736 struct fw_ohci *ohci = ctx->ohci; 737 738 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { 739 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 740 flush_writes(ohci); 741 742 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); 743 } 744 /* FIXME: restart? */ 745} 746 747static inline unsigned int ar_next_buffer_index(unsigned int index) 748{ 749 return (index + 1) % AR_BUFFERS; 750} 751 752static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) 753{ 754 return ar_next_buffer_index(ctx->last_buffer_index); 755} 756 757/* 758 * We search for the buffer that contains the last AR packet DMA data written 759 * by the controller. 760 */ 761static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, 762 unsigned int *buffer_offset) 763{ 764 unsigned int i, next_i, last = ctx->last_buffer_index; 765 __le16 res_count, next_res_count; 766 767 i = ar_first_buffer_index(ctx); 768 res_count = READ_ONCE(ctx->descriptors[i].res_count); 769 770 /* A buffer that is not yet completely filled must be the last one. */ 771 while (i != last && res_count == 0) { 772 773 /* Peek at the next descriptor. */ 774 next_i = ar_next_buffer_index(i); 775 rmb(); /* read descriptors in order */ 776 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 777 /* 778 * If the next descriptor is still empty, we must stop at this 779 * descriptor. 780 */ 781 if (next_res_count == cpu_to_le16(PAGE_SIZE)) { 782 /* 783 * The exception is when the DMA data for one packet is 784 * split over three buffers; in this case, the middle 785 * buffer's descriptor might be never updated by the 786 * controller and look still empty, and we have to peek 787 * at the third one. 788 */ 789 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { 790 next_i = ar_next_buffer_index(next_i); 791 rmb(); 792 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count); 793 if (next_res_count != cpu_to_le16(PAGE_SIZE)) 794 goto next_buffer_is_active; 795 } 796 797 break; 798 } 799 800next_buffer_is_active: 801 i = next_i; 802 res_count = next_res_count; 803 } 804 805 rmb(); /* read res_count before the DMA data */ 806 807 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); 808 if (*buffer_offset > PAGE_SIZE) { 809 *buffer_offset = 0; 810 ar_context_abort(ctx, "corrupted descriptor"); 811 } 812 813 return i; 814} 815 816static void ar_sync_buffers_for_cpu(struct ar_context *ctx, 817 unsigned int end_buffer_index, 818 unsigned int end_buffer_offset) 819{ 820 unsigned int i; 821 822 i = ar_first_buffer_index(ctx); 823 while (i != end_buffer_index) { 824 dma_sync_single_for_cpu(ctx->ohci->card.device, 825 ar_buffer_bus(ctx, i), 826 PAGE_SIZE, DMA_FROM_DEVICE); 827 i = ar_next_buffer_index(i); 828 } 829 if (end_buffer_offset > 0) 830 dma_sync_single_for_cpu(ctx->ohci->card.device, 831 ar_buffer_bus(ctx, i), 832 end_buffer_offset, DMA_FROM_DEVICE); 833} 834 835#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) 836#define cond_le32_to_cpu(v) \ 837 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) 838#else 839#define cond_le32_to_cpu(v) le32_to_cpu(v) 840#endif 841 842static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) 843{ 844 struct fw_ohci *ohci = ctx->ohci; 845 struct fw_packet p; 846 u32 status, length, tcode; 847 int evt; 848 849 p.header[0] = cond_le32_to_cpu(buffer[0]); 850 p.header[1] = cond_le32_to_cpu(buffer[1]); 851 p.header[2] = cond_le32_to_cpu(buffer[2]); 852 853 tcode = (p.header[0] >> 4) & 0x0f; 854 switch (tcode) { 855 case TCODE_WRITE_QUADLET_REQUEST: 856 case TCODE_READ_QUADLET_RESPONSE: 857 p.header[3] = (__force __u32) buffer[3]; 858 p.header_length = 16; 859 p.payload_length = 0; 860 break; 861 862 case TCODE_READ_BLOCK_REQUEST : 863 p.header[3] = cond_le32_to_cpu(buffer[3]); 864 p.header_length = 16; 865 p.payload_length = 0; 866 break; 867 868 case TCODE_WRITE_BLOCK_REQUEST: 869 case TCODE_READ_BLOCK_RESPONSE: 870 case TCODE_LOCK_REQUEST: 871 case TCODE_LOCK_RESPONSE: 872 p.header[3] = cond_le32_to_cpu(buffer[3]); 873 p.header_length = 16; 874 p.payload_length = p.header[3] >> 16; 875 if (p.payload_length > MAX_ASYNC_PAYLOAD) { 876 ar_context_abort(ctx, "invalid packet length"); 877 return NULL; 878 } 879 break; 880 881 case TCODE_WRITE_RESPONSE: 882 case TCODE_READ_QUADLET_REQUEST: 883 case OHCI_TCODE_PHY_PACKET: 884 p.header_length = 12; 885 p.payload_length = 0; 886 break; 887 888 default: 889 ar_context_abort(ctx, "invalid tcode"); 890 return NULL; 891 } 892 893 p.payload = (void *) buffer + p.header_length; 894 895 /* FIXME: What to do about evt_* errors? */ 896 length = (p.header_length + p.payload_length + 3) / 4; 897 status = cond_le32_to_cpu(buffer[length]); 898 evt = (status >> 16) & 0x1f; 899 900 p.ack = evt - 16; 901 p.speed = (status >> 21) & 0x7; 902 p.timestamp = status & 0xffff; 903 p.generation = ohci->request_generation; 904 905 log_ar_at_event(ohci, 'R', p.speed, p.header, evt); 906 907 /* 908 * Several controllers, notably from NEC and VIA, forget to 909 * write ack_complete status at PHY packet reception. 910 */ 911 if (evt == OHCI1394_evt_no_status && 912 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) 913 p.ack = ACK_COMPLETE; 914 915 /* 916 * The OHCI bus reset handler synthesizes a PHY packet with 917 * the new generation number when a bus reset happens (see 918 * section 8.4.2.3). This helps us determine when a request 919 * was received and make sure we send the response in the same 920 * generation. We only need this for requests; for responses 921 * we use the unique tlabel for finding the matching 922 * request. 923 * 924 * Alas some chips sometimes emit bus reset packets with a 925 * wrong generation. We set the correct generation for these 926 * at a slightly incorrect time (in bus_reset_work). 927 */ 928 if (evt == OHCI1394_evt_bus_reset) { 929 if (!(ohci->quirks & QUIRK_RESET_PACKET)) 930 ohci->request_generation = (p.header[2] >> 16) & 0xff; 931 } else if (ctx == &ohci->ar_request_ctx) { 932 fw_core_handle_request(&ohci->card, &p); 933 } else { 934 fw_core_handle_response(&ohci->card, &p); 935 } 936 937 return buffer + length + 1; 938} 939 940static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) 941{ 942 void *next; 943 944 while (p < end) { 945 next = handle_ar_packet(ctx, p); 946 if (!next) 947 return p; 948 p = next; 949 } 950 951 return p; 952} 953 954static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) 955{ 956 unsigned int i; 957 958 i = ar_first_buffer_index(ctx); 959 while (i != end_buffer) { 960 dma_sync_single_for_device(ctx->ohci->card.device, 961 ar_buffer_bus(ctx, i), 962 PAGE_SIZE, DMA_FROM_DEVICE); 963 ar_context_link_page(ctx, i); 964 i = ar_next_buffer_index(i); 965 } 966} 967 968static void ar_context_tasklet(unsigned long data) 969{ 970 struct ar_context *ctx = (struct ar_context *)data; 971 unsigned int end_buffer_index, end_buffer_offset; 972 void *p, *end; 973 974 p = ctx->pointer; 975 if (!p) 976 return; 977 978 end_buffer_index = ar_search_last_active_buffer(ctx, 979 &end_buffer_offset); 980 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); 981 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; 982 983 if (end_buffer_index < ar_first_buffer_index(ctx)) { 984 /* 985 * The filled part of the overall buffer wraps around; handle 986 * all packets up to the buffer end here. If the last packet 987 * wraps around, its tail will be visible after the buffer end 988 * because the buffer start pages are mapped there again. 989 */ 990 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; 991 p = handle_ar_packets(ctx, p, buffer_end); 992 if (p < buffer_end) 993 goto error; 994 /* adjust p to point back into the actual buffer */ 995 p -= AR_BUFFERS * PAGE_SIZE; 996 } 997 998 p = handle_ar_packets(ctx, p, end); 999 if (p != end) { 1000 if (p > end) 1001 ar_context_abort(ctx, "inconsistent descriptor"); 1002 goto error; 1003 } 1004 1005 ctx->pointer = p; 1006 ar_recycle_buffers(ctx, end_buffer_index); 1007 1008 return; 1009 1010error: 1011 ctx->pointer = NULL; 1012} 1013 1014static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, 1015 unsigned int descriptors_offset, u32 regs) 1016{ 1017 struct device *dev = ohci->card.device; 1018 unsigned int i; 1019 dma_addr_t dma_addr; 1020 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; 1021 struct descriptor *d; 1022 1023 ctx->regs = regs; 1024 ctx->ohci = ohci; 1025 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); 1026 1027 for (i = 0; i < AR_BUFFERS; i++) { 1028 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr, 1029 DMA_FROM_DEVICE, GFP_KERNEL); 1030 if (!ctx->pages[i]) 1031 goto out_of_memory; 1032 set_page_private(ctx->pages[i], dma_addr); 1033 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE, 1034 DMA_FROM_DEVICE); 1035 } 1036 1037 for (i = 0; i < AR_BUFFERS; i++) 1038 pages[i] = ctx->pages[i]; 1039 for (i = 0; i < AR_WRAPAROUND_PAGES; i++) 1040 pages[AR_BUFFERS + i] = ctx->pages[i]; 1041 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL); 1042 if (!ctx->buffer) 1043 goto out_of_memory; 1044 1045 ctx->descriptors = ohci->misc_buffer + descriptors_offset; 1046 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; 1047 1048 for (i = 0; i < AR_BUFFERS; i++) { 1049 d = &ctx->descriptors[i]; 1050 d->req_count = cpu_to_le16(PAGE_SIZE); 1051 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 1052 DESCRIPTOR_STATUS | 1053 DESCRIPTOR_BRANCH_ALWAYS); 1054 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); 1055 d->branch_address = cpu_to_le32(ctx->descriptors_bus + 1056 ar_next_buffer_index(i) * sizeof(struct descriptor)); 1057 } 1058 1059 return 0; 1060 1061out_of_memory: 1062 ar_context_release(ctx); 1063 1064 return -ENOMEM; 1065} 1066 1067static void ar_context_run(struct ar_context *ctx) 1068{ 1069 unsigned int i; 1070 1071 for (i = 0; i < AR_BUFFERS; i++) 1072 ar_context_link_page(ctx, i); 1073 1074 ctx->pointer = ctx->buffer; 1075 1076 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1077 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1078} 1079 1080static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) 1081{ 1082 __le16 branch; 1083 1084 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS); 1085 1086 /* figure out which descriptor the branch address goes in */ 1087 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 1088 return d; 1089 else 1090 return d + z - 1; 1091} 1092 1093static void context_tasklet(unsigned long data) 1094{ 1095 struct context *ctx = (struct context *) data; 1096 struct descriptor *d, *last; 1097 u32 address; 1098 int z; 1099 struct descriptor_buffer *desc; 1100 1101 desc = list_entry(ctx->buffer_list.next, 1102 struct descriptor_buffer, list); 1103 last = ctx->last; 1104 while (last->branch_address != 0) { 1105 struct descriptor_buffer *old_desc = desc; 1106 address = le32_to_cpu(last->branch_address); 1107 z = address & 0xf; 1108 address &= ~0xf; 1109 ctx->current_bus = address; 1110 1111 /* If the branch address points to a buffer outside of the 1112 * current buffer, advance to the next buffer. */ 1113 if (address < desc->buffer_bus || 1114 address >= desc->buffer_bus + desc->used) 1115 desc = list_entry(desc->list.next, 1116 struct descriptor_buffer, list); 1117 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); 1118 last = find_branch_descriptor(d, z); 1119 1120 if (!ctx->callback(ctx, d, last)) 1121 break; 1122 1123 if (old_desc != desc) { 1124 /* If we've advanced to the next buffer, move the 1125 * previous buffer to the free list. */ 1126 unsigned long flags; 1127 old_desc->used = 0; 1128 spin_lock_irqsave(&ctx->ohci->lock, flags); 1129 list_move_tail(&old_desc->list, &ctx->buffer_list); 1130 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1131 } 1132 ctx->last = last; 1133 } 1134} 1135 1136/* 1137 * Allocate a new buffer and add it to the list of free buffers for this 1138 * context. Must be called with ohci->lock held. 1139 */ 1140static int context_add_buffer(struct context *ctx) 1141{ 1142 struct descriptor_buffer *desc; 1143 dma_addr_t bus_addr; 1144 int offset; 1145 1146 /* 1147 * 16MB of descriptors should be far more than enough for any DMA 1148 * program. This will catch run-away userspace or DoS attacks. 1149 */ 1150 if (ctx->total_allocation >= 16*1024*1024) 1151 return -ENOMEM; 1152 1153 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, 1154 &bus_addr, GFP_ATOMIC); 1155 if (!desc) 1156 return -ENOMEM; 1157 1158 offset = (void *)&desc->buffer - (void *)desc; 1159 /* 1160 * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads 1161 * for descriptors, even 0x10-byte ones. This can cause page faults when 1162 * an IOMMU is in use and the oversized read crosses a page boundary. 1163 * Work around this by always leaving at least 0x10 bytes of padding. 1164 */ 1165 desc->buffer_size = PAGE_SIZE - offset - 0x10; 1166 desc->buffer_bus = bus_addr + offset; 1167 desc->used = 0; 1168 1169 list_add_tail(&desc->list, &ctx->buffer_list); 1170 ctx->total_allocation += PAGE_SIZE; 1171 1172 return 0; 1173} 1174 1175static int context_init(struct context *ctx, struct fw_ohci *ohci, 1176 u32 regs, descriptor_callback_t callback) 1177{ 1178 ctx->ohci = ohci; 1179 ctx->regs = regs; 1180 ctx->total_allocation = 0; 1181 1182 INIT_LIST_HEAD(&ctx->buffer_list); 1183 if (context_add_buffer(ctx) < 0) 1184 return -ENOMEM; 1185 1186 ctx->buffer_tail = list_entry(ctx->buffer_list.next, 1187 struct descriptor_buffer, list); 1188 1189 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); 1190 ctx->callback = callback; 1191 1192 /* 1193 * We put a dummy descriptor in the buffer that has a NULL 1194 * branch address and looks like it's been sent. That way we 1195 * have a descriptor to append DMA programs to. 1196 */ 1197 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); 1198 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); 1199 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); 1200 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); 1201 ctx->last = ctx->buffer_tail->buffer; 1202 ctx->prev = ctx->buffer_tail->buffer; 1203 ctx->prev_z = 1; 1204 1205 return 0; 1206} 1207 1208static void context_release(struct context *ctx) 1209{ 1210 struct fw_card *card = &ctx->ohci->card; 1211 struct descriptor_buffer *desc, *tmp; 1212 1213 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) 1214 dma_free_coherent(card->device, PAGE_SIZE, desc, 1215 desc->buffer_bus - 1216 ((void *)&desc->buffer - (void *)desc)); 1217} 1218 1219/* Must be called with ohci->lock held */ 1220static struct descriptor *context_get_descriptors(struct context *ctx, 1221 int z, dma_addr_t *d_bus) 1222{ 1223 struct descriptor *d = NULL; 1224 struct descriptor_buffer *desc = ctx->buffer_tail; 1225 1226 if (z * sizeof(*d) > desc->buffer_size) 1227 return NULL; 1228 1229 if (z * sizeof(*d) > desc->buffer_size - desc->used) { 1230 /* No room for the descriptor in this buffer, so advance to the 1231 * next one. */ 1232 1233 if (desc->list.next == &ctx->buffer_list) { 1234 /* If there is no free buffer next in the list, 1235 * allocate one. */ 1236 if (context_add_buffer(ctx) < 0) 1237 return NULL; 1238 } 1239 desc = list_entry(desc->list.next, 1240 struct descriptor_buffer, list); 1241 ctx->buffer_tail = desc; 1242 } 1243 1244 d = desc->buffer + desc->used / sizeof(*d); 1245 memset(d, 0, z * sizeof(*d)); 1246 *d_bus = desc->buffer_bus + desc->used; 1247 1248 return d; 1249} 1250 1251static void context_run(struct context *ctx, u32 extra) 1252{ 1253 struct fw_ohci *ohci = ctx->ohci; 1254 1255 reg_write(ohci, COMMAND_PTR(ctx->regs), 1256 le32_to_cpu(ctx->last->branch_address)); 1257 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1258 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); 1259 ctx->running = true; 1260 flush_writes(ohci); 1261} 1262 1263static void context_append(struct context *ctx, 1264 struct descriptor *d, int z, int extra) 1265{ 1266 dma_addr_t d_bus; 1267 struct descriptor_buffer *desc = ctx->buffer_tail; 1268 struct descriptor *d_branch; 1269 1270 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); 1271 1272 desc->used += (z + extra) * sizeof(*d); 1273 1274 wmb(); /* finish init of new descriptors before branch_address update */ 1275 1276 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z); 1277 d_branch->branch_address = cpu_to_le32(d_bus | z); 1278 1279 /* 1280 * VT6306 incorrectly checks only the single descriptor at the 1281 * CommandPtr when the wake bit is written, so if it's a 1282 * multi-descriptor block starting with an INPUT_MORE, put a copy of 1283 * the branch address in the first descriptor. 1284 * 1285 * Not doing this for transmit contexts since not sure how it interacts 1286 * with skip addresses. 1287 */ 1288 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && 1289 d_branch != ctx->prev && 1290 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) == 1291 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) { 1292 ctx->prev->branch_address = cpu_to_le32(d_bus | z); 1293 } 1294 1295 ctx->prev = d; 1296 ctx->prev_z = z; 1297} 1298 1299static void context_stop(struct context *ctx) 1300{ 1301 struct fw_ohci *ohci = ctx->ohci; 1302 u32 reg; 1303 int i; 1304 1305 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1306 ctx->running = false; 1307 1308 for (i = 0; i < 1000; i++) { 1309 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); 1310 if ((reg & CONTEXT_ACTIVE) == 0) 1311 return; 1312 1313 if (i) 1314 udelay(10); 1315 } 1316 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); 1317} 1318 1319struct driver_data { 1320 u8 inline_data[8]; 1321 struct fw_packet *packet; 1322}; 1323 1324/* 1325 * This function apppends a packet to the DMA queue for transmission. 1326 * Must always be called with the ochi->lock held to ensure proper 1327 * generation handling and locking around packet queue manipulation. 1328 */ 1329static int at_context_queue_packet(struct context *ctx, 1330 struct fw_packet *packet) 1331{ 1332 struct fw_ohci *ohci = ctx->ohci; 1333 dma_addr_t d_bus, payload_bus; 1334 struct driver_data *driver_data; 1335 struct descriptor *d, *last; 1336 __le32 *header; 1337 int z, tcode; 1338 1339 d = context_get_descriptors(ctx, 4, &d_bus); 1340 if (d == NULL) { 1341 packet->ack = RCODE_SEND_ERROR; 1342 return -1; 1343 } 1344 1345 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 1346 d[0].res_count = cpu_to_le16(packet->timestamp); 1347 1348 /* 1349 * The DMA format for asynchronous link packets is different 1350 * from the IEEE1394 layout, so shift the fields around 1351 * accordingly. 1352 */ 1353 1354 tcode = (packet->header[0] >> 4) & 0x0f; 1355 header = (__le32 *) &d[1]; 1356 switch (tcode) { 1357 case TCODE_WRITE_QUADLET_REQUEST: 1358 case TCODE_WRITE_BLOCK_REQUEST: 1359 case TCODE_WRITE_RESPONSE: 1360 case TCODE_READ_QUADLET_REQUEST: 1361 case TCODE_READ_BLOCK_REQUEST: 1362 case TCODE_READ_QUADLET_RESPONSE: 1363 case TCODE_READ_BLOCK_RESPONSE: 1364 case TCODE_LOCK_REQUEST: 1365 case TCODE_LOCK_RESPONSE: 1366 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1367 (packet->speed << 16)); 1368 header[1] = cpu_to_le32((packet->header[1] & 0xffff) | 1369 (packet->header[0] & 0xffff0000)); 1370 header[2] = cpu_to_le32(packet->header[2]); 1371 1372 if (TCODE_IS_BLOCK_PACKET(tcode)) 1373 header[3] = cpu_to_le32(packet->header[3]); 1374 else 1375 header[3] = (__force __le32) packet->header[3]; 1376 1377 d[0].req_count = cpu_to_le16(packet->header_length); 1378 break; 1379 1380 case TCODE_LINK_INTERNAL: 1381 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | 1382 (packet->speed << 16)); 1383 header[1] = cpu_to_le32(packet->header[1]); 1384 header[2] = cpu_to_le32(packet->header[2]); 1385 d[0].req_count = cpu_to_le16(12); 1386 1387 if (is_ping_packet(&packet->header[1])) 1388 d[0].control |= cpu_to_le16(DESCRIPTOR_PING); 1389 break; 1390 1391 case TCODE_STREAM_DATA: 1392 header[0] = cpu_to_le32((packet->header[0] & 0xffff) | 1393 (packet->speed << 16)); 1394 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); 1395 d[0].req_count = cpu_to_le16(8); 1396 break; 1397 1398 default: 1399 /* BUG(); */ 1400 packet->ack = RCODE_SEND_ERROR; 1401 return -1; 1402 } 1403 1404 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor)); 1405 driver_data = (struct driver_data *) &d[3]; 1406 driver_data->packet = packet; 1407 packet->driver_data = driver_data; 1408 1409 if (packet->payload_length > 0) { 1410 if (packet->payload_length > sizeof(driver_data->inline_data)) { 1411 payload_bus = dma_map_single(ohci->card.device, 1412 packet->payload, 1413 packet->payload_length, 1414 DMA_TO_DEVICE); 1415 if (dma_mapping_error(ohci->card.device, payload_bus)) { 1416 packet->ack = RCODE_SEND_ERROR; 1417 return -1; 1418 } 1419 packet->payload_bus = payload_bus; 1420 packet->payload_mapped = true; 1421 } else { 1422 memcpy(driver_data->inline_data, packet->payload, 1423 packet->payload_length); 1424 payload_bus = d_bus + 3 * sizeof(*d); 1425 } 1426 1427 d[2].req_count = cpu_to_le16(packet->payload_length); 1428 d[2].data_address = cpu_to_le32(payload_bus); 1429 last = &d[2]; 1430 z = 3; 1431 } else { 1432 last = &d[0]; 1433 z = 2; 1434 } 1435 1436 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 1437 DESCRIPTOR_IRQ_ALWAYS | 1438 DESCRIPTOR_BRANCH_ALWAYS); 1439 1440 /* FIXME: Document how the locking works. */ 1441 if (ohci->generation != packet->generation) { 1442 if (packet->payload_mapped) 1443 dma_unmap_single(ohci->card.device, payload_bus, 1444 packet->payload_length, DMA_TO_DEVICE); 1445 packet->ack = RCODE_GENERATION; 1446 return -1; 1447 } 1448 1449 context_append(ctx, d, z, 4 - z); 1450 1451 if (ctx->running) 1452 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 1453 else 1454 context_run(ctx, 0); 1455 1456 return 0; 1457} 1458 1459static void at_context_flush(struct context *ctx) 1460{ 1461 tasklet_disable(&ctx->tasklet); 1462 1463 ctx->flushing = true; 1464 context_tasklet((unsigned long)ctx); 1465 ctx->flushing = false; 1466 1467 tasklet_enable(&ctx->tasklet); 1468} 1469 1470static int handle_at_packet(struct context *context, 1471 struct descriptor *d, 1472 struct descriptor *last) 1473{ 1474 struct driver_data *driver_data; 1475 struct fw_packet *packet; 1476 struct fw_ohci *ohci = context->ohci; 1477 int evt; 1478 1479 if (last->transfer_status == 0 && !context->flushing) 1480 /* This descriptor isn't done yet, stop iteration. */ 1481 return 0; 1482 1483 driver_data = (struct driver_data *) &d[3]; 1484 packet = driver_data->packet; 1485 if (packet == NULL) 1486 /* This packet was cancelled, just continue. */ 1487 return 1; 1488 1489 if (packet->payload_mapped) 1490 dma_unmap_single(ohci->card.device, packet->payload_bus, 1491 packet->payload_length, DMA_TO_DEVICE); 1492 1493 evt = le16_to_cpu(last->transfer_status) & 0x1f; 1494 packet->timestamp = le16_to_cpu(last->res_count); 1495 1496 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt); 1497 1498 switch (evt) { 1499 case OHCI1394_evt_timeout: 1500 /* Async response transmit timed out. */ 1501 packet->ack = RCODE_CANCELLED; 1502 break; 1503 1504 case OHCI1394_evt_flushed: 1505 /* 1506 * The packet was flushed should give same error as 1507 * when we try to use a stale generation count. 1508 */ 1509 packet->ack = RCODE_GENERATION; 1510 break; 1511 1512 case OHCI1394_evt_missing_ack: 1513 if (context->flushing) 1514 packet->ack = RCODE_GENERATION; 1515 else { 1516 /* 1517 * Using a valid (current) generation count, but the 1518 * node is not on the bus or not sending acks. 1519 */ 1520 packet->ack = RCODE_NO_ACK; 1521 } 1522 break; 1523 1524 case ACK_COMPLETE + 0x10: 1525 case ACK_PENDING + 0x10: 1526 case ACK_BUSY_X + 0x10: 1527 case ACK_BUSY_A + 0x10: 1528 case ACK_BUSY_B + 0x10: 1529 case ACK_DATA_ERROR + 0x10: 1530 case ACK_TYPE_ERROR + 0x10: 1531 packet->ack = evt - 0x10; 1532 break; 1533 1534 case OHCI1394_evt_no_status: 1535 if (context->flushing) { 1536 packet->ack = RCODE_GENERATION; 1537 break; 1538 } 1539 fallthrough; 1540 1541 default: 1542 packet->ack = RCODE_SEND_ERROR; 1543 break; 1544 } 1545 1546 packet->callback(packet, &ohci->card, packet->ack); 1547 1548 return 1; 1549} 1550 1551#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) 1552#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) 1553#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) 1554#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) 1555#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) 1556 1557static void handle_local_rom(struct fw_ohci *ohci, 1558 struct fw_packet *packet, u32 csr) 1559{ 1560 struct fw_packet response; 1561 int tcode, length, i; 1562 1563 tcode = HEADER_GET_TCODE(packet->header[0]); 1564 if (TCODE_IS_BLOCK_PACKET(tcode)) 1565 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1566 else 1567 length = 4; 1568 1569 i = csr - CSR_CONFIG_ROM; 1570 if (i + length > CONFIG_ROM_SIZE) { 1571 fw_fill_response(&response, packet->header, 1572 RCODE_ADDRESS_ERROR, NULL, 0); 1573 } else if (!TCODE_IS_READ_REQUEST(tcode)) { 1574 fw_fill_response(&response, packet->header, 1575 RCODE_TYPE_ERROR, NULL, 0); 1576 } else { 1577 fw_fill_response(&response, packet->header, RCODE_COMPLETE, 1578 (void *) ohci->config_rom + i, length); 1579 } 1580 1581 fw_core_handle_response(&ohci->card, &response); 1582} 1583 1584static void handle_local_lock(struct fw_ohci *ohci, 1585 struct fw_packet *packet, u32 csr) 1586{ 1587 struct fw_packet response; 1588 int tcode, length, ext_tcode, sel, try; 1589 __be32 *payload, lock_old; 1590 u32 lock_arg, lock_data; 1591 1592 tcode = HEADER_GET_TCODE(packet->header[0]); 1593 length = HEADER_GET_DATA_LENGTH(packet->header[3]); 1594 payload = packet->payload; 1595 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); 1596 1597 if (tcode == TCODE_LOCK_REQUEST && 1598 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { 1599 lock_arg = be32_to_cpu(payload[0]); 1600 lock_data = be32_to_cpu(payload[1]); 1601 } else if (tcode == TCODE_READ_QUADLET_REQUEST) { 1602 lock_arg = 0; 1603 lock_data = 0; 1604 } else { 1605 fw_fill_response(&response, packet->header, 1606 RCODE_TYPE_ERROR, NULL, 0); 1607 goto out; 1608 } 1609 1610 sel = (csr - CSR_BUS_MANAGER_ID) / 4; 1611 reg_write(ohci, OHCI1394_CSRData, lock_data); 1612 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); 1613 reg_write(ohci, OHCI1394_CSRControl, sel); 1614 1615 for (try = 0; try < 20; try++) 1616 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { 1617 lock_old = cpu_to_be32(reg_read(ohci, 1618 OHCI1394_CSRData)); 1619 fw_fill_response(&response, packet->header, 1620 RCODE_COMPLETE, 1621 &lock_old, sizeof(lock_old)); 1622 goto out; 1623 } 1624 1625 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); 1626 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); 1627 1628 out: 1629 fw_core_handle_response(&ohci->card, &response); 1630} 1631 1632static void handle_local_request(struct context *ctx, struct fw_packet *packet) 1633{ 1634 u64 offset, csr; 1635 1636 if (ctx == &ctx->ohci->at_request_ctx) { 1637 packet->ack = ACK_PENDING; 1638 packet->callback(packet, &ctx->ohci->card, packet->ack); 1639 } 1640 1641 offset = 1642 ((unsigned long long) 1643 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | 1644 packet->header[2]; 1645 csr = offset - CSR_REGISTER_BASE; 1646 1647 /* Handle config rom reads. */ 1648 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) 1649 handle_local_rom(ctx->ohci, packet, csr); 1650 else switch (csr) { 1651 case CSR_BUS_MANAGER_ID: 1652 case CSR_BANDWIDTH_AVAILABLE: 1653 case CSR_CHANNELS_AVAILABLE_HI: 1654 case CSR_CHANNELS_AVAILABLE_LO: 1655 handle_local_lock(ctx->ohci, packet, csr); 1656 break; 1657 default: 1658 if (ctx == &ctx->ohci->at_request_ctx) 1659 fw_core_handle_request(&ctx->ohci->card, packet); 1660 else 1661 fw_core_handle_response(&ctx->ohci->card, packet); 1662 break; 1663 } 1664 1665 if (ctx == &ctx->ohci->at_response_ctx) { 1666 packet->ack = ACK_COMPLETE; 1667 packet->callback(packet, &ctx->ohci->card, packet->ack); 1668 } 1669} 1670 1671static void at_context_transmit(struct context *ctx, struct fw_packet *packet) 1672{ 1673 unsigned long flags; 1674 int ret; 1675 1676 spin_lock_irqsave(&ctx->ohci->lock, flags); 1677 1678 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && 1679 ctx->ohci->generation == packet->generation) { 1680 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1681 handle_local_request(ctx, packet); 1682 return; 1683 } 1684 1685 ret = at_context_queue_packet(ctx, packet); 1686 spin_unlock_irqrestore(&ctx->ohci->lock, flags); 1687 1688 if (ret < 0) 1689 packet->callback(packet, &ctx->ohci->card, packet->ack); 1690 1691} 1692 1693static void detect_dead_context(struct fw_ohci *ohci, 1694 const char *name, unsigned int regs) 1695{ 1696 u32 ctl; 1697 1698 ctl = reg_read(ohci, CONTROL_SET(regs)); 1699 if (ctl & CONTEXT_DEAD) 1700 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", 1701 name, evts[ctl & 0x1f]); 1702} 1703 1704static void handle_dead_contexts(struct fw_ohci *ohci) 1705{ 1706 unsigned int i; 1707 char name[8]; 1708 1709 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); 1710 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); 1711 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); 1712 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); 1713 for (i = 0; i < 32; ++i) { 1714 if (!(ohci->it_context_support & (1 << i))) 1715 continue; 1716 sprintf(name, "IT%u", i); 1717 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); 1718 } 1719 for (i = 0; i < 32; ++i) { 1720 if (!(ohci->ir_context_support & (1 << i))) 1721 continue; 1722 sprintf(name, "IR%u", i); 1723 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); 1724 } 1725 /* TODO: maybe try to flush and restart the dead contexts */ 1726} 1727 1728static u32 cycle_timer_ticks(u32 cycle_timer) 1729{ 1730 u32 ticks; 1731 1732 ticks = cycle_timer & 0xfff; 1733 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); 1734 ticks += (3072 * 8000) * (cycle_timer >> 25); 1735 1736 return ticks; 1737} 1738 1739/* 1740 * Some controllers exhibit one or more of the following bugs when updating the 1741 * iso cycle timer register: 1742 * - When the lowest six bits are wrapping around to zero, a read that happens 1743 * at the same time will return garbage in the lowest ten bits. 1744 * - When the cycleOffset field wraps around to zero, the cycleCount field is 1745 * not incremented for about 60 ns. 1746 * - Occasionally, the entire register reads zero. 1747 * 1748 * To catch these, we read the register three times and ensure that the 1749 * difference between each two consecutive reads is approximately the same, i.e. 1750 * less than twice the other. Furthermore, any negative difference indicates an 1751 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to 1752 * execute, so we have enough precision to compute the ratio of the differences.) 1753 */ 1754static u32 get_cycle_time(struct fw_ohci *ohci) 1755{ 1756 u32 c0, c1, c2; 1757 u32 t0, t1, t2; 1758 s32 diff01, diff12; 1759 int i; 1760 1761 if (has_reboot_by_cycle_timer_read_quirk(ohci)) 1762 return 0; 1763 1764 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1765 1766 if (ohci->quirks & QUIRK_CYCLE_TIMER) { 1767 i = 0; 1768 c1 = c2; 1769 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1770 do { 1771 c0 = c1; 1772 c1 = c2; 1773 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); 1774 t0 = cycle_timer_ticks(c0); 1775 t1 = cycle_timer_ticks(c1); 1776 t2 = cycle_timer_ticks(c2); 1777 diff01 = t1 - t0; 1778 diff12 = t2 - t1; 1779 } while ((diff01 <= 0 || diff12 <= 0 || 1780 diff01 / diff12 >= 2 || diff12 / diff01 >= 2) 1781 && i++ < 20); 1782 } 1783 1784 return c2; 1785} 1786 1787/* 1788 * This function has to be called at least every 64 seconds. The bus_time 1789 * field stores not only the upper 25 bits of the BUS_TIME register but also 1790 * the most significant bit of the cycle timer in bit 6 so that we can detect 1791 * changes in this bit. 1792 */ 1793static u32 update_bus_time(struct fw_ohci *ohci) 1794{ 1795 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; 1796 1797 if (unlikely(!ohci->bus_time_running)) { 1798 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); 1799 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | 1800 (cycle_time_seconds & 0x40); 1801 ohci->bus_time_running = true; 1802 } 1803 1804 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) 1805 ohci->bus_time += 0x40; 1806 1807 return ohci->bus_time | cycle_time_seconds; 1808} 1809 1810static int get_status_for_port(struct fw_ohci *ohci, int port_index) 1811{ 1812 int reg; 1813 1814 mutex_lock(&ohci->phy_reg_mutex); 1815 reg = write_phy_reg(ohci, 7, port_index); 1816 if (reg >= 0) 1817 reg = read_phy_reg(ohci, 8); 1818 mutex_unlock(&ohci->phy_reg_mutex); 1819 if (reg < 0) 1820 return reg; 1821 1822 switch (reg & 0x0f) { 1823 case 0x06: 1824 return 2; /* is child node (connected to parent node) */ 1825 case 0x0e: 1826 return 3; /* is parent node (connected to child node) */ 1827 } 1828 return 1; /* not connected */ 1829} 1830 1831static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, 1832 int self_id_count) 1833{ 1834 int i; 1835 u32 entry; 1836 1837 for (i = 0; i < self_id_count; i++) { 1838 entry = ohci->self_id_buffer[i]; 1839 if ((self_id & 0xff000000) == (entry & 0xff000000)) 1840 return -1; 1841 if ((self_id & 0xff000000) < (entry & 0xff000000)) 1842 return i; 1843 } 1844 return i; 1845} 1846 1847static int initiated_reset(struct fw_ohci *ohci) 1848{ 1849 int reg; 1850 int ret = 0; 1851 1852 mutex_lock(&ohci->phy_reg_mutex); 1853 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */ 1854 if (reg >= 0) { 1855 reg = read_phy_reg(ohci, 8); 1856 reg |= 0x40; 1857 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */ 1858 if (reg >= 0) { 1859 reg = read_phy_reg(ohci, 12); /* read register 12 */ 1860 if (reg >= 0) { 1861 if ((reg & 0x08) == 0x08) { 1862 /* bit 3 indicates "initiated reset" */ 1863 ret = 0x2; 1864 } 1865 } 1866 } 1867 } 1868 mutex_unlock(&ohci->phy_reg_mutex); 1869 return ret; 1870} 1871 1872/* 1873 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally 1874 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059. 1875 * Construct the selfID from phy register contents. 1876 */ 1877static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) 1878{ 1879 int reg, i, pos, status; 1880 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */ 1881 u32 self_id = 0x8040c800; 1882 1883 reg = reg_read(ohci, OHCI1394_NodeID); 1884 if (!(reg & OHCI1394_NodeID_idValid)) { 1885 ohci_notice(ohci, 1886 "node ID not valid, new bus reset in progress\n"); 1887 return -EBUSY; 1888 } 1889 self_id |= ((reg & 0x3f) << 24); /* phy ID */ 1890 1891 reg = ohci_read_phy_reg(&ohci->card, 4); 1892 if (reg < 0) 1893 return reg; 1894 self_id |= ((reg & 0x07) << 8); /* power class */ 1895 1896 reg = ohci_read_phy_reg(&ohci->card, 1); 1897 if (reg < 0) 1898 return reg; 1899 self_id |= ((reg & 0x3f) << 16); /* gap count */ 1900 1901 for (i = 0; i < 3; i++) { 1902 status = get_status_for_port(ohci, i); 1903 if (status < 0) 1904 return status; 1905 self_id |= ((status & 0x3) << (6 - (i * 2))); 1906 } 1907 1908 self_id |= initiated_reset(ohci); 1909 1910 pos = get_self_id_pos(ohci, self_id, self_id_count); 1911 if (pos >= 0) { 1912 memmove(&(ohci->self_id_buffer[pos+1]), 1913 &(ohci->self_id_buffer[pos]), 1914 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); 1915 ohci->self_id_buffer[pos] = self_id; 1916 self_id_count++; 1917 } 1918 return self_id_count; 1919} 1920 1921static void bus_reset_work(struct work_struct *work) 1922{ 1923 struct fw_ohci *ohci = 1924 container_of(work, struct fw_ohci, bus_reset_work); 1925 int self_id_count, generation, new_generation, i, j; 1926 u32 reg; 1927 void *free_rom = NULL; 1928 dma_addr_t free_rom_bus = 0; 1929 bool is_new_root; 1930 1931 reg = reg_read(ohci, OHCI1394_NodeID); 1932 if (!(reg & OHCI1394_NodeID_idValid)) { 1933 ohci_notice(ohci, 1934 "node ID not valid, new bus reset in progress\n"); 1935 return; 1936 } 1937 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { 1938 ohci_notice(ohci, "malconfigured bus\n"); 1939 return; 1940 } 1941 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | 1942 OHCI1394_NodeID_nodeNumber); 1943 1944 is_new_root = (reg & OHCI1394_NodeID_root) != 0; 1945 if (!(ohci->is_root && is_new_root)) 1946 reg_write(ohci, OHCI1394_LinkControlSet, 1947 OHCI1394_LinkControl_cycleMaster); 1948 ohci->is_root = is_new_root; 1949 1950 reg = reg_read(ohci, OHCI1394_SelfIDCount); 1951 if (reg & OHCI1394_SelfIDCount_selfIDError) { 1952 ohci_notice(ohci, "self ID receive error\n"); 1953 return; 1954 } 1955 /* 1956 * The count in the SelfIDCount register is the number of 1957 * bytes in the self ID receive buffer. Since we also receive 1958 * the inverted quadlets and a header quadlet, we shift one 1959 * bit extra to get the actual number of self IDs. 1960 */ 1961 self_id_count = (reg >> 3) & 0xff; 1962 1963 if (self_id_count > 252) { 1964 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); 1965 return; 1966 } 1967 1968 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff; 1969 rmb(); 1970 1971 for (i = 1, j = 0; j < self_id_count; i += 2, j++) { 1972 u32 id = cond_le32_to_cpu(ohci->self_id[i]); 1973 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]); 1974 1975 if (id != ~id2) { 1976 /* 1977 * If the invalid data looks like a cycle start packet, 1978 * it's likely to be the result of the cycle master 1979 * having a wrong gap count. In this case, the self IDs 1980 * so far are valid and should be processed so that the 1981 * bus manager can then correct the gap count. 1982 */ 1983 if (id == 0xffff008f) { 1984 ohci_notice(ohci, "ignoring spurious self IDs\n"); 1985 self_id_count = j; 1986 break; 1987 } 1988 1989 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", 1990 j, self_id_count, id, id2); 1991 return; 1992 } 1993 ohci->self_id_buffer[j] = id; 1994 } 1995 1996 if (ohci->quirks & QUIRK_TI_SLLZ059) { 1997 self_id_count = find_and_insert_self_id(ohci, self_id_count); 1998 if (self_id_count < 0) { 1999 ohci_notice(ohci, 2000 "could not construct local self ID\n"); 2001 return; 2002 } 2003 } 2004 2005 if (self_id_count == 0) { 2006 ohci_notice(ohci, "no self IDs\n"); 2007 return; 2008 } 2009 rmb(); 2010 2011 /* 2012 * Check the consistency of the self IDs we just read. The 2013 * problem we face is that a new bus reset can start while we 2014 * read out the self IDs from the DMA buffer. If this happens, 2015 * the DMA buffer will be overwritten with new self IDs and we 2016 * will read out inconsistent data. The OHCI specification 2017 * (section 11.2) recommends a technique similar to 2018 * linux/seqlock.h, where we remember the generation of the 2019 * self IDs in the buffer before reading them out and compare 2020 * it to the current generation after reading them out. If 2021 * the two generations match we know we have a consistent set 2022 * of self IDs. 2023 */ 2024 2025 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; 2026 if (new_generation != generation) { 2027 ohci_notice(ohci, "new bus reset, discarding self ids\n"); 2028 return; 2029 } 2030 2031 /* FIXME: Document how the locking works. */ 2032 spin_lock_irq(&ohci->lock); 2033 2034 ohci->generation = -1; /* prevent AT packet queueing */ 2035 context_stop(&ohci->at_request_ctx); 2036 context_stop(&ohci->at_response_ctx); 2037 2038 spin_unlock_irq(&ohci->lock); 2039 2040 /* 2041 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent 2042 * packets in the AT queues and software needs to drain them. 2043 * Some OHCI 1.1 controllers (JMicron) apparently require this too. 2044 */ 2045 at_context_flush(&ohci->at_request_ctx); 2046 at_context_flush(&ohci->at_response_ctx); 2047 2048 spin_lock_irq(&ohci->lock); 2049 2050 ohci->generation = generation; 2051 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); 2052 2053 if (ohci->quirks & QUIRK_RESET_PACKET) 2054 ohci->request_generation = generation; 2055 2056 /* 2057 * This next bit is unrelated to the AT context stuff but we 2058 * have to do it under the spinlock also. If a new config rom 2059 * was set up before this reset, the old one is now no longer 2060 * in use and we can free it. Update the config rom pointers 2061 * to point to the current config rom and clear the 2062 * next_config_rom pointer so a new update can take place. 2063 */ 2064 2065 if (ohci->next_config_rom != NULL) { 2066 if (ohci->next_config_rom != ohci->config_rom) { 2067 free_rom = ohci->config_rom; 2068 free_rom_bus = ohci->config_rom_bus; 2069 } 2070 ohci->config_rom = ohci->next_config_rom; 2071 ohci->config_rom_bus = ohci->next_config_rom_bus; 2072 ohci->next_config_rom = NULL; 2073 2074 /* 2075 * Restore config_rom image and manually update 2076 * config_rom registers. Writing the header quadlet 2077 * will indicate that the config rom is ready, so we 2078 * do that last. 2079 */ 2080 reg_write(ohci, OHCI1394_BusOptions, 2081 be32_to_cpu(ohci->config_rom[2])); 2082 ohci->config_rom[0] = ohci->next_header; 2083 reg_write(ohci, OHCI1394_ConfigROMhdr, 2084 be32_to_cpu(ohci->next_header)); 2085 } 2086 2087 if (param_remote_dma) { 2088 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); 2089 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); 2090 } 2091 2092 spin_unlock_irq(&ohci->lock); 2093 2094 if (free_rom) 2095 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2096 free_rom, free_rom_bus); 2097 2098 log_selfids(ohci, generation, self_id_count); 2099 2100 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, 2101 self_id_count, ohci->self_id_buffer, 2102 ohci->csr_state_setclear_abdicate); 2103 ohci->csr_state_setclear_abdicate = false; 2104} 2105 2106static irqreturn_t irq_handler(int irq, void *data) 2107{ 2108 struct fw_ohci *ohci = data; 2109 u32 event, iso_event; 2110 int i; 2111 2112 event = reg_read(ohci, OHCI1394_IntEventClear); 2113 2114 if (!event || !~event) 2115 return IRQ_NONE; 2116 2117 /* 2118 * busReset and postedWriteErr must not be cleared yet 2119 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) 2120 */ 2121 reg_write(ohci, OHCI1394_IntEventClear, 2122 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); 2123 log_irqs(ohci, event); 2124 2125 if (event & OHCI1394_selfIDComplete) 2126 queue_work(selfid_workqueue, &ohci->bus_reset_work); 2127 2128 if (event & OHCI1394_RQPkt) 2129 tasklet_schedule(&ohci->ar_request_ctx.tasklet); 2130 2131 if (event & OHCI1394_RSPkt) 2132 tasklet_schedule(&ohci->ar_response_ctx.tasklet); 2133 2134 if (event & OHCI1394_reqTxComplete) 2135 tasklet_schedule(&ohci->at_request_ctx.tasklet); 2136 2137 if (event & OHCI1394_respTxComplete) 2138 tasklet_schedule(&ohci->at_response_ctx.tasklet); 2139 2140 if (event & OHCI1394_isochRx) { 2141 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); 2142 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); 2143 2144 while (iso_event) { 2145 i = ffs(iso_event) - 1; 2146 tasklet_schedule( 2147 &ohci->ir_context_list[i].context.tasklet); 2148 iso_event &= ~(1 << i); 2149 } 2150 } 2151 2152 if (event & OHCI1394_isochTx) { 2153 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); 2154 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); 2155 2156 while (iso_event) { 2157 i = ffs(iso_event) - 1; 2158 tasklet_schedule( 2159 &ohci->it_context_list[i].context.tasklet); 2160 iso_event &= ~(1 << i); 2161 } 2162 } 2163 2164 if (unlikely(event & OHCI1394_regAccessFail)) 2165 ohci_err(ohci, "register access failure\n"); 2166 2167 if (unlikely(event & OHCI1394_postedWriteErr)) { 2168 reg_read(ohci, OHCI1394_PostedWriteAddressHi); 2169 reg_read(ohci, OHCI1394_PostedWriteAddressLo); 2170 reg_write(ohci, OHCI1394_IntEventClear, 2171 OHCI1394_postedWriteErr); 2172 if (printk_ratelimit()) 2173 ohci_err(ohci, "PCI posted write error\n"); 2174 } 2175 2176 if (unlikely(event & OHCI1394_cycleTooLong)) { 2177 if (printk_ratelimit()) 2178 ohci_notice(ohci, "isochronous cycle too long\n"); 2179 reg_write(ohci, OHCI1394_LinkControlSet, 2180 OHCI1394_LinkControl_cycleMaster); 2181 } 2182 2183 if (unlikely(event & OHCI1394_cycleInconsistent)) { 2184 /* 2185 * We need to clear this event bit in order to make 2186 * cycleMatch isochronous I/O work. In theory we should 2187 * stop active cycleMatch iso contexts now and restart 2188 * them at least two cycles later. (FIXME?) 2189 */ 2190 if (printk_ratelimit()) 2191 ohci_notice(ohci, "isochronous cycle inconsistent\n"); 2192 } 2193 2194 if (unlikely(event & OHCI1394_unrecoverableError)) 2195 handle_dead_contexts(ohci); 2196 2197 if (event & OHCI1394_cycle64Seconds) { 2198 spin_lock(&ohci->lock); 2199 update_bus_time(ohci); 2200 spin_unlock(&ohci->lock); 2201 } else 2202 flush_writes(ohci); 2203 2204 return IRQ_HANDLED; 2205} 2206 2207static int software_reset(struct fw_ohci *ohci) 2208{ 2209 u32 val; 2210 int i; 2211 2212 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 2213 for (i = 0; i < 500; i++) { 2214 val = reg_read(ohci, OHCI1394_HCControlSet); 2215 if (!~val) 2216 return -ENODEV; /* Card was ejected. */ 2217 2218 if (!(val & OHCI1394_HCControl_softReset)) 2219 return 0; 2220 2221 msleep(1); 2222 } 2223 2224 return -EBUSY; 2225} 2226 2227static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) 2228{ 2229 size_t size = length * 4; 2230 2231 memcpy(dest, src, size); 2232 if (size < CONFIG_ROM_SIZE) 2233 memset(&dest[length], 0, CONFIG_ROM_SIZE - size); 2234} 2235 2236static int configure_1394a_enhancements(struct fw_ohci *ohci) 2237{ 2238 bool enable_1394a; 2239 int ret, clear, set, offset; 2240 2241 /* Check if the driver should configure link and PHY. */ 2242 if (!(reg_read(ohci, OHCI1394_HCControlSet) & 2243 OHCI1394_HCControl_programPhyEnable)) 2244 return 0; 2245 2246 /* Paranoia: check whether the PHY supports 1394a, too. */ 2247 enable_1394a = false; 2248 ret = read_phy_reg(ohci, 2); 2249 if (ret < 0) 2250 return ret; 2251 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { 2252 ret = read_paged_phy_reg(ohci, 1, 8); 2253 if (ret < 0) 2254 return ret; 2255 if (ret >= 1) 2256 enable_1394a = true; 2257 } 2258 2259 if (ohci->quirks & QUIRK_NO_1394A) 2260 enable_1394a = false; 2261 2262 /* Configure PHY and link consistently. */ 2263 if (enable_1394a) { 2264 clear = 0; 2265 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2266 } else { 2267 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; 2268 set = 0; 2269 } 2270 ret = update_phy_reg(ohci, 5, clear, set); 2271 if (ret < 0) 2272 return ret; 2273 2274 if (enable_1394a) 2275 offset = OHCI1394_HCControlSet; 2276 else 2277 offset = OHCI1394_HCControlClear; 2278 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); 2279 2280 /* Clean up: configuration has been taken care of. */ 2281 reg_write(ohci, OHCI1394_HCControlClear, 2282 OHCI1394_HCControl_programPhyEnable); 2283 2284 return 0; 2285} 2286 2287static int probe_tsb41ba3d(struct fw_ohci *ohci) 2288{ 2289 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */ 2290 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, }; 2291 int reg, i; 2292 2293 reg = read_phy_reg(ohci, 2); 2294 if (reg < 0) 2295 return reg; 2296 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS) 2297 return 0; 2298 2299 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) { 2300 reg = read_paged_phy_reg(ohci, 1, i + 10); 2301 if (reg < 0) 2302 return reg; 2303 if (reg != id[i]) 2304 return 0; 2305 } 2306 return 1; 2307} 2308 2309static int ohci_enable(struct fw_card *card, 2310 const __be32 *config_rom, size_t length) 2311{ 2312 struct fw_ohci *ohci = fw_ohci(card); 2313 u32 lps, version, irqs; 2314 int i, ret; 2315 2316 ret = software_reset(ohci); 2317 if (ret < 0) { 2318 ohci_err(ohci, "failed to reset ohci card\n"); 2319 return ret; 2320 } 2321 2322 /* 2323 * Now enable LPS, which we need in order to start accessing 2324 * most of the registers. In fact, on some cards (ALI M5251), 2325 * accessing registers in the SClk domain without LPS enabled 2326 * will lock up the machine. Wait 50msec to make sure we have 2327 * full link enabled. However, with some cards (well, at least 2328 * a JMicron PCIe card), we have to try again sometimes. 2329 * 2330 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but 2331 * cannot actually use the phy at that time. These need tens of 2332 * millisecods pause between LPS write and first phy access too. 2333 */ 2334 2335 reg_write(ohci, OHCI1394_HCControlSet, 2336 OHCI1394_HCControl_LPS | 2337 OHCI1394_HCControl_postedWriteEnable); 2338 flush_writes(ohci); 2339 2340 for (lps = 0, i = 0; !lps && i < 3; i++) { 2341 msleep(50); 2342 lps = reg_read(ohci, OHCI1394_HCControlSet) & 2343 OHCI1394_HCControl_LPS; 2344 } 2345 2346 if (!lps) { 2347 ohci_err(ohci, "failed to set Link Power Status\n"); 2348 return -EIO; 2349 } 2350 2351 if (ohci->quirks & QUIRK_TI_SLLZ059) { 2352 ret = probe_tsb41ba3d(ohci); 2353 if (ret < 0) 2354 return ret; 2355 if (ret) 2356 ohci_notice(ohci, "local TSB41BA3D phy\n"); 2357 else 2358 ohci->quirks &= ~QUIRK_TI_SLLZ059; 2359 } 2360 2361 reg_write(ohci, OHCI1394_HCControlClear, 2362 OHCI1394_HCControl_noByteSwapData); 2363 2364 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); 2365 reg_write(ohci, OHCI1394_LinkControlSet, 2366 OHCI1394_LinkControl_cycleTimerEnable | 2367 OHCI1394_LinkControl_cycleMaster); 2368 2369 reg_write(ohci, OHCI1394_ATRetries, 2370 OHCI1394_MAX_AT_REQ_RETRIES | 2371 (OHCI1394_MAX_AT_RESP_RETRIES << 4) | 2372 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | 2373 (200 << 16)); 2374 2375 ohci->bus_time_running = false; 2376 2377 for (i = 0; i < 32; i++) 2378 if (ohci->ir_context_support & (1 << i)) 2379 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), 2380 IR_CONTEXT_MULTI_CHANNEL_MODE); 2381 2382 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 2383 if (version >= OHCI_VERSION_1_1) { 2384 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, 2385 0xfffffffe); 2386 card->broadcast_channel_auto_allocated = true; 2387 } 2388 2389 /* Get implemented bits of the priority arbitration request counter. */ 2390 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); 2391 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; 2392 reg_write(ohci, OHCI1394_FairnessControl, 0); 2393 card->priority_budget_implemented = ohci->pri_req_max != 0; 2394 2395 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); 2396 reg_write(ohci, OHCI1394_IntEventClear, ~0); 2397 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 2398 2399 ret = configure_1394a_enhancements(ohci); 2400 if (ret < 0) 2401 return ret; 2402 2403 /* Activate link_on bit and contender bit in our self ID packets.*/ 2404 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); 2405 if (ret < 0) 2406 return ret; 2407 2408 /* 2409 * When the link is not yet enabled, the atomic config rom 2410 * update mechanism described below in ohci_set_config_rom() 2411 * is not active. We have to update ConfigRomHeader and 2412 * BusOptions manually, and the write to ConfigROMmap takes 2413 * effect immediately. We tie this to the enabling of the 2414 * link, so we have a valid config rom before enabling - the 2415 * OHCI requires that ConfigROMhdr and BusOptions have valid 2416 * values before enabling. 2417 * 2418 * However, when the ConfigROMmap is written, some controllers 2419 * always read back quadlets 0 and 2 from the config rom to 2420 * the ConfigRomHeader and BusOptions registers on bus reset. 2421 * They shouldn't do that in this initial case where the link 2422 * isn't enabled. This means we have to use the same 2423 * workaround here, setting the bus header to 0 and then write 2424 * the right values in the bus reset tasklet. 2425 */ 2426 2427 if (config_rom) { 2428 ohci->next_config_rom = 2429 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2430 &ohci->next_config_rom_bus, 2431 GFP_KERNEL); 2432 if (ohci->next_config_rom == NULL) 2433 return -ENOMEM; 2434 2435 copy_config_rom(ohci->next_config_rom, config_rom, length); 2436 } else { 2437 /* 2438 * In the suspend case, config_rom is NULL, which 2439 * means that we just reuse the old config rom. 2440 */ 2441 ohci->next_config_rom = ohci->config_rom; 2442 ohci->next_config_rom_bus = ohci->config_rom_bus; 2443 } 2444 2445 ohci->next_header = ohci->next_config_rom[0]; 2446 ohci->next_config_rom[0] = 0; 2447 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); 2448 reg_write(ohci, OHCI1394_BusOptions, 2449 be32_to_cpu(ohci->next_config_rom[2])); 2450 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2451 2452 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); 2453 2454 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | 2455 OHCI1394_RQPkt | OHCI1394_RSPkt | 2456 OHCI1394_isochTx | OHCI1394_isochRx | 2457 OHCI1394_postedWriteErr | 2458 OHCI1394_selfIDComplete | 2459 OHCI1394_regAccessFail | 2460 OHCI1394_cycleInconsistent | 2461 OHCI1394_unrecoverableError | 2462 OHCI1394_cycleTooLong | 2463 OHCI1394_masterIntEnable; 2464 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) 2465 irqs |= OHCI1394_busReset; 2466 reg_write(ohci, OHCI1394_IntMaskSet, irqs); 2467 2468 reg_write(ohci, OHCI1394_HCControlSet, 2469 OHCI1394_HCControl_linkEnable | 2470 OHCI1394_HCControl_BIBimageValid); 2471 2472 reg_write(ohci, OHCI1394_LinkControlSet, 2473 OHCI1394_LinkControl_rcvSelfID | 2474 OHCI1394_LinkControl_rcvPhyPkt); 2475 2476 ar_context_run(&ohci->ar_request_ctx); 2477 ar_context_run(&ohci->ar_response_ctx); 2478 2479 flush_writes(ohci); 2480 2481 /* We are ready to go, reset bus to finish initialization. */ 2482 fw_schedule_bus_reset(&ohci->card, false, true); 2483 2484 return 0; 2485} 2486 2487static int ohci_set_config_rom(struct fw_card *card, 2488 const __be32 *config_rom, size_t length) 2489{ 2490 struct fw_ohci *ohci; 2491 __be32 *next_config_rom; 2492 dma_addr_t next_config_rom_bus; 2493 2494 ohci = fw_ohci(card); 2495 2496 /* 2497 * When the OHCI controller is enabled, the config rom update 2498 * mechanism is a bit tricky, but easy enough to use. See 2499 * section 5.5.6 in the OHCI specification. 2500 * 2501 * The OHCI controller caches the new config rom address in a 2502 * shadow register (ConfigROMmapNext) and needs a bus reset 2503 * for the changes to take place. When the bus reset is 2504 * detected, the controller loads the new values for the 2505 * ConfigRomHeader and BusOptions registers from the specified 2506 * config rom and loads ConfigROMmap from the ConfigROMmapNext 2507 * shadow register. All automatically and atomically. 2508 * 2509 * Now, there's a twist to this story. The automatic load of 2510 * ConfigRomHeader and BusOptions doesn't honor the 2511 * noByteSwapData bit, so with a be32 config rom, the 2512 * controller will load be32 values in to these registers 2513 * during the atomic update, even on litte endian 2514 * architectures. The workaround we use is to put a 0 in the 2515 * header quadlet; 0 is endian agnostic and means that the 2516 * config rom isn't ready yet. In the bus reset tasklet we 2517 * then set up the real values for the two registers. 2518 * 2519 * We use ohci->lock to avoid racing with the code that sets 2520 * ohci->next_config_rom to NULL (see bus_reset_work). 2521 */ 2522 2523 next_config_rom = 2524 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2525 &next_config_rom_bus, GFP_KERNEL); 2526 if (next_config_rom == NULL) 2527 return -ENOMEM; 2528 2529 spin_lock_irq(&ohci->lock); 2530 2531 /* 2532 * If there is not an already pending config_rom update, 2533 * push our new allocation into the ohci->next_config_rom 2534 * and then mark the local variable as null so that we 2535 * won't deallocate the new buffer. 2536 * 2537 * OTOH, if there is a pending config_rom update, just 2538 * use that buffer with the new config_rom data, and 2539 * let this routine free the unused DMA allocation. 2540 */ 2541 2542 if (ohci->next_config_rom == NULL) { 2543 ohci->next_config_rom = next_config_rom; 2544 ohci->next_config_rom_bus = next_config_rom_bus; 2545 next_config_rom = NULL; 2546 } 2547 2548 copy_config_rom(ohci->next_config_rom, config_rom, length); 2549 2550 ohci->next_header = config_rom[0]; 2551 ohci->next_config_rom[0] = 0; 2552 2553 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); 2554 2555 spin_unlock_irq(&ohci->lock); 2556 2557 /* If we didn't use the DMA allocation, delete it. */ 2558 if (next_config_rom != NULL) 2559 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 2560 next_config_rom, next_config_rom_bus); 2561 2562 /* 2563 * Now initiate a bus reset to have the changes take 2564 * effect. We clean up the old config rom memory and DMA 2565 * mappings in the bus reset tasklet, since the OHCI 2566 * controller could need to access it before the bus reset 2567 * takes effect. 2568 */ 2569 2570 fw_schedule_bus_reset(&ohci->card, true, true); 2571 2572 return 0; 2573} 2574 2575static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) 2576{ 2577 struct fw_ohci *ohci = fw_ohci(card); 2578 2579 at_context_transmit(&ohci->at_request_ctx, packet); 2580} 2581 2582static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) 2583{ 2584 struct fw_ohci *ohci = fw_ohci(card); 2585 2586 at_context_transmit(&ohci->at_response_ctx, packet); 2587} 2588 2589static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) 2590{ 2591 struct fw_ohci *ohci = fw_ohci(card); 2592 struct context *ctx = &ohci->at_request_ctx; 2593 struct driver_data *driver_data = packet->driver_data; 2594 int ret = -ENOENT; 2595 2596 tasklet_disable(&ctx->tasklet); 2597 2598 if (packet->ack != 0) 2599 goto out; 2600 2601 if (packet->payload_mapped) 2602 dma_unmap_single(ohci->card.device, packet->payload_bus, 2603 packet->payload_length, DMA_TO_DEVICE); 2604 2605 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20); 2606 driver_data->packet = NULL; 2607 packet->ack = RCODE_CANCELLED; 2608 packet->callback(packet, &ohci->card, packet->ack); 2609 ret = 0; 2610 out: 2611 tasklet_enable(&ctx->tasklet); 2612 2613 return ret; 2614} 2615 2616static int ohci_enable_phys_dma(struct fw_card *card, 2617 int node_id, int generation) 2618{ 2619 struct fw_ohci *ohci = fw_ohci(card); 2620 unsigned long flags; 2621 int n, ret = 0; 2622 2623 if (param_remote_dma) 2624 return 0; 2625 2626 /* 2627 * FIXME: Make sure this bitmask is cleared when we clear the busReset 2628 * interrupt bit. Clear physReqResourceAllBuses on bus reset. 2629 */ 2630 2631 spin_lock_irqsave(&ohci->lock, flags); 2632 2633 if (ohci->generation != generation) { 2634 ret = -ESTALE; 2635 goto out; 2636 } 2637 2638 /* 2639 * Note, if the node ID contains a non-local bus ID, physical DMA is 2640 * enabled for _all_ nodes on remote buses. 2641 */ 2642 2643 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; 2644 if (n < 32) 2645 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); 2646 else 2647 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); 2648 2649 flush_writes(ohci); 2650 out: 2651 spin_unlock_irqrestore(&ohci->lock, flags); 2652 2653 return ret; 2654} 2655 2656static u32 ohci_read_csr(struct fw_card *card, int csr_offset) 2657{ 2658 struct fw_ohci *ohci = fw_ohci(card); 2659 unsigned long flags; 2660 u32 value; 2661 2662 switch (csr_offset) { 2663 case CSR_STATE_CLEAR: 2664 case CSR_STATE_SET: 2665 if (ohci->is_root && 2666 (reg_read(ohci, OHCI1394_LinkControlSet) & 2667 OHCI1394_LinkControl_cycleMaster)) 2668 value = CSR_STATE_BIT_CMSTR; 2669 else 2670 value = 0; 2671 if (ohci->csr_state_setclear_abdicate) 2672 value |= CSR_STATE_BIT_ABDICATE; 2673 2674 return value; 2675 2676 case CSR_NODE_IDS: 2677 return reg_read(ohci, OHCI1394_NodeID) << 16; 2678 2679 case CSR_CYCLE_TIME: 2680 return get_cycle_time(ohci); 2681 2682 case CSR_BUS_TIME: 2683 /* 2684 * We might be called just after the cycle timer has wrapped 2685 * around but just before the cycle64Seconds handler, so we 2686 * better check here, too, if the bus time needs to be updated. 2687 */ 2688 spin_lock_irqsave(&ohci->lock, flags); 2689 value = update_bus_time(ohci); 2690 spin_unlock_irqrestore(&ohci->lock, flags); 2691 return value; 2692 2693 case CSR_BUSY_TIMEOUT: 2694 value = reg_read(ohci, OHCI1394_ATRetries); 2695 return (value >> 4) & 0x0ffff00f; 2696 2697 case CSR_PRIORITY_BUDGET: 2698 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | 2699 (ohci->pri_req_max << 8); 2700 2701 default: 2702 WARN_ON(1); 2703 return 0; 2704 } 2705} 2706 2707static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) 2708{ 2709 struct fw_ohci *ohci = fw_ohci(card); 2710 unsigned long flags; 2711 2712 switch (csr_offset) { 2713 case CSR_STATE_CLEAR: 2714 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2715 reg_write(ohci, OHCI1394_LinkControlClear, 2716 OHCI1394_LinkControl_cycleMaster); 2717 flush_writes(ohci); 2718 } 2719 if (value & CSR_STATE_BIT_ABDICATE) 2720 ohci->csr_state_setclear_abdicate = false; 2721 break; 2722 2723 case CSR_STATE_SET: 2724 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { 2725 reg_write(ohci, OHCI1394_LinkControlSet, 2726 OHCI1394_LinkControl_cycleMaster); 2727 flush_writes(ohci); 2728 } 2729 if (value & CSR_STATE_BIT_ABDICATE) 2730 ohci->csr_state_setclear_abdicate = true; 2731 break; 2732 2733 case CSR_NODE_IDS: 2734 reg_write(ohci, OHCI1394_NodeID, value >> 16); 2735 flush_writes(ohci); 2736 break; 2737 2738 case CSR_CYCLE_TIME: 2739 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); 2740 reg_write(ohci, OHCI1394_IntEventSet, 2741 OHCI1394_cycleInconsistent); 2742 flush_writes(ohci); 2743 break; 2744 2745 case CSR_BUS_TIME: 2746 spin_lock_irqsave(&ohci->lock, flags); 2747 ohci->bus_time = (update_bus_time(ohci) & 0x40) | 2748 (value & ~0x7f); 2749 spin_unlock_irqrestore(&ohci->lock, flags); 2750 break; 2751 2752 case CSR_BUSY_TIMEOUT: 2753 value = (value & 0xf) | ((value & 0xf) << 4) | 2754 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); 2755 reg_write(ohci, OHCI1394_ATRetries, value); 2756 flush_writes(ohci); 2757 break; 2758 2759 case CSR_PRIORITY_BUDGET: 2760 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); 2761 flush_writes(ohci); 2762 break; 2763 2764 default: 2765 WARN_ON(1); 2766 break; 2767 } 2768} 2769 2770static void flush_iso_completions(struct iso_context *ctx) 2771{ 2772 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp, 2773 ctx->header_length, ctx->header, 2774 ctx->base.callback_data); 2775 ctx->header_length = 0; 2776} 2777 2778static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr) 2779{ 2780 u32 *ctx_hdr; 2781 2782 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) { 2783 if (ctx->base.drop_overflow_headers) 2784 return; 2785 flush_iso_completions(ctx); 2786 } 2787 2788 ctx_hdr = ctx->header + ctx->header_length; 2789 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]); 2790 2791 /* 2792 * The two iso header quadlets are byteswapped to little 2793 * endian by the controller, but we want to present them 2794 * as big endian for consistency with the bus endianness. 2795 */ 2796 if (ctx->base.header_size > 0) 2797 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */ 2798 if (ctx->base.header_size > 4) 2799 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */ 2800 if (ctx->base.header_size > 8) 2801 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8); 2802 ctx->header_length += ctx->base.header_size; 2803} 2804 2805static int handle_ir_packet_per_buffer(struct context *context, 2806 struct descriptor *d, 2807 struct descriptor *last) 2808{ 2809 struct iso_context *ctx = 2810 container_of(context, struct iso_context, context); 2811 struct descriptor *pd; 2812 u32 buffer_dma; 2813 2814 for (pd = d; pd <= last; pd++) 2815 if (pd->transfer_status) 2816 break; 2817 if (pd > last) 2818 /* Descriptor(s) not done yet, stop iteration */ 2819 return 0; 2820 2821 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) { 2822 d++; 2823 buffer_dma = le32_to_cpu(d->data_address); 2824 dma_sync_single_range_for_cpu(context->ohci->card.device, 2825 buffer_dma & PAGE_MASK, 2826 buffer_dma & ~PAGE_MASK, 2827 le16_to_cpu(d->req_count), 2828 DMA_FROM_DEVICE); 2829 } 2830 2831 copy_iso_headers(ctx, (u32 *) (last + 1)); 2832 2833 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2834 flush_iso_completions(ctx); 2835 2836 return 1; 2837} 2838 2839/* d == last because each descriptor block is only a single descriptor. */ 2840static int handle_ir_buffer_fill(struct context *context, 2841 struct descriptor *d, 2842 struct descriptor *last) 2843{ 2844 struct iso_context *ctx = 2845 container_of(context, struct iso_context, context); 2846 unsigned int req_count, res_count, completed; 2847 u32 buffer_dma; 2848 2849 req_count = le16_to_cpu(last->req_count); 2850 res_count = le16_to_cpu(READ_ONCE(last->res_count)); 2851 completed = req_count - res_count; 2852 buffer_dma = le32_to_cpu(last->data_address); 2853 2854 if (completed > 0) { 2855 ctx->mc_buffer_bus = buffer_dma; 2856 ctx->mc_completed = completed; 2857 } 2858 2859 if (res_count != 0) 2860 /* Descriptor(s) not done yet, stop iteration */ 2861 return 0; 2862 2863 dma_sync_single_range_for_cpu(context->ohci->card.device, 2864 buffer_dma & PAGE_MASK, 2865 buffer_dma & ~PAGE_MASK, 2866 completed, DMA_FROM_DEVICE); 2867 2868 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) { 2869 ctx->base.callback.mc(&ctx->base, 2870 buffer_dma + completed, 2871 ctx->base.callback_data); 2872 ctx->mc_completed = 0; 2873 } 2874 2875 return 1; 2876} 2877 2878static void flush_ir_buffer_fill(struct iso_context *ctx) 2879{ 2880 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, 2881 ctx->mc_buffer_bus & PAGE_MASK, 2882 ctx->mc_buffer_bus & ~PAGE_MASK, 2883 ctx->mc_completed, DMA_FROM_DEVICE); 2884 2885 ctx->base.callback.mc(&ctx->base, 2886 ctx->mc_buffer_bus + ctx->mc_completed, 2887 ctx->base.callback_data); 2888 ctx->mc_completed = 0; 2889} 2890 2891static inline void sync_it_packet_for_cpu(struct context *context, 2892 struct descriptor *pd) 2893{ 2894 __le16 control; 2895 u32 buffer_dma; 2896 2897 /* only packets beginning with OUTPUT_MORE* have data buffers */ 2898 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2899 return; 2900 2901 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */ 2902 pd += 2; 2903 2904 /* 2905 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's 2906 * data buffer is in the context program's coherent page and must not 2907 * be synced. 2908 */ 2909 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) == 2910 (context->current_bus & PAGE_MASK)) { 2911 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)) 2912 return; 2913 pd++; 2914 } 2915 2916 do { 2917 buffer_dma = le32_to_cpu(pd->data_address); 2918 dma_sync_single_range_for_cpu(context->ohci->card.device, 2919 buffer_dma & PAGE_MASK, 2920 buffer_dma & ~PAGE_MASK, 2921 le16_to_cpu(pd->req_count), 2922 DMA_TO_DEVICE); 2923 control = pd->control; 2924 pd++; 2925 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))); 2926} 2927 2928static int handle_it_packet(struct context *context, 2929 struct descriptor *d, 2930 struct descriptor *last) 2931{ 2932 struct iso_context *ctx = 2933 container_of(context, struct iso_context, context); 2934 struct descriptor *pd; 2935 __be32 *ctx_hdr; 2936 2937 for (pd = d; pd <= last; pd++) 2938 if (pd->transfer_status) 2939 break; 2940 if (pd > last) 2941 /* Descriptor(s) not done yet, stop iteration */ 2942 return 0; 2943 2944 sync_it_packet_for_cpu(context, d); 2945 2946 if (ctx->header_length + 4 > PAGE_SIZE) { 2947 if (ctx->base.drop_overflow_headers) 2948 return 1; 2949 flush_iso_completions(ctx); 2950 } 2951 2952 ctx_hdr = ctx->header + ctx->header_length; 2953 ctx->last_timestamp = le16_to_cpu(last->res_count); 2954 /* Present this value as big-endian to match the receive code */ 2955 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) | 2956 le16_to_cpu(pd->res_count)); 2957 ctx->header_length += 4; 2958 2959 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) 2960 flush_iso_completions(ctx); 2961 2962 return 1; 2963} 2964 2965static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) 2966{ 2967 u32 hi = channels >> 32, lo = channels; 2968 2969 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); 2970 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); 2971 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); 2972 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); 2973 ohci->mc_channels = channels; 2974} 2975 2976static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, 2977 int type, int channel, size_t header_size) 2978{ 2979 struct fw_ohci *ohci = fw_ohci(card); 2980 struct iso_context *ctx; 2981 descriptor_callback_t callback; 2982 u64 *channels; 2983 u32 *mask, regs; 2984 int index, ret = -EBUSY; 2985 2986 spin_lock_irq(&ohci->lock); 2987 2988 switch (type) { 2989 case FW_ISO_CONTEXT_TRANSMIT: 2990 mask = &ohci->it_context_mask; 2991 callback = handle_it_packet; 2992 index = ffs(*mask) - 1; 2993 if (index >= 0) { 2994 *mask &= ~(1 << index); 2995 regs = OHCI1394_IsoXmitContextBase(index); 2996 ctx = &ohci->it_context_list[index]; 2997 } 2998 break; 2999 3000 case FW_ISO_CONTEXT_RECEIVE: 3001 channels = &ohci->ir_context_channels; 3002 mask = &ohci->ir_context_mask; 3003 callback = handle_ir_packet_per_buffer; 3004 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; 3005 if (index >= 0) { 3006 *channels &= ~(1ULL << channel); 3007 *mask &= ~(1 << index); 3008 regs = OHCI1394_IsoRcvContextBase(index); 3009 ctx = &ohci->ir_context_list[index]; 3010 } 3011 break; 3012 3013 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3014 mask = &ohci->ir_context_mask; 3015 callback = handle_ir_buffer_fill; 3016 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; 3017 if (index >= 0) { 3018 ohci->mc_allocated = true; 3019 *mask &= ~(1 << index); 3020 regs = OHCI1394_IsoRcvContextBase(index); 3021 ctx = &ohci->ir_context_list[index]; 3022 } 3023 break; 3024 3025 default: 3026 index = -1; 3027 ret = -ENOSYS; 3028 } 3029 3030 spin_unlock_irq(&ohci->lock); 3031 3032 if (index < 0) 3033 return ERR_PTR(ret); 3034 3035 memset(ctx, 0, sizeof(*ctx)); 3036 ctx->header_length = 0; 3037 ctx->header = (void *) __get_free_page(GFP_KERNEL); 3038 if (ctx->header == NULL) { 3039 ret = -ENOMEM; 3040 goto out; 3041 } 3042 ret = context_init(&ctx->context, ohci, regs, callback); 3043 if (ret < 0) 3044 goto out_with_header; 3045 3046 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) { 3047 set_multichannel_mask(ohci, 0); 3048 ctx->mc_completed = 0; 3049 } 3050 3051 return &ctx->base; 3052 3053 out_with_header: 3054 free_page((unsigned long)ctx->header); 3055 out: 3056 spin_lock_irq(&ohci->lock); 3057 3058 switch (type) { 3059 case FW_ISO_CONTEXT_RECEIVE: 3060 *channels |= 1ULL << channel; 3061 break; 3062 3063 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3064 ohci->mc_allocated = false; 3065 break; 3066 } 3067 *mask |= 1 << index; 3068 3069 spin_unlock_irq(&ohci->lock); 3070 3071 return ERR_PTR(ret); 3072} 3073 3074static int ohci_start_iso(struct fw_iso_context *base, 3075 s32 cycle, u32 sync, u32 tags) 3076{ 3077 struct iso_context *ctx = container_of(base, struct iso_context, base); 3078 struct fw_ohci *ohci = ctx->context.ohci; 3079 u32 control = IR_CONTEXT_ISOCH_HEADER, match; 3080 int index; 3081 3082 /* the controller cannot start without any queued packets */ 3083 if (ctx->context.last->branch_address == 0) 3084 return -ENODATA; 3085 3086 switch (ctx->base.type) { 3087 case FW_ISO_CONTEXT_TRANSMIT: 3088 index = ctx - ohci->it_context_list; 3089 match = 0; 3090 if (cycle >= 0) 3091 match = IT_CONTEXT_CYCLE_MATCH_ENABLE | 3092 (cycle & 0x7fff) << 16; 3093 3094 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); 3095 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); 3096 context_run(&ctx->context, match); 3097 break; 3098 3099 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3100 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; 3101 fallthrough; 3102 case FW_ISO_CONTEXT_RECEIVE: 3103 index = ctx - ohci->ir_context_list; 3104 match = (tags << 28) | (sync << 8) | ctx->base.channel; 3105 if (cycle >= 0) { 3106 match |= (cycle & 0x07fff) << 12; 3107 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; 3108 } 3109 3110 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); 3111 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); 3112 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); 3113 context_run(&ctx->context, control); 3114 3115 ctx->sync = sync; 3116 ctx->tags = tags; 3117 3118 break; 3119 } 3120 3121 return 0; 3122} 3123 3124static int ohci_stop_iso(struct fw_iso_context *base) 3125{ 3126 struct fw_ohci *ohci = fw_ohci(base->card); 3127 struct iso_context *ctx = container_of(base, struct iso_context, base); 3128 int index; 3129 3130 switch (ctx->base.type) { 3131 case FW_ISO_CONTEXT_TRANSMIT: 3132 index = ctx - ohci->it_context_list; 3133 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); 3134 break; 3135 3136 case FW_ISO_CONTEXT_RECEIVE: 3137 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3138 index = ctx - ohci->ir_context_list; 3139 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); 3140 break; 3141 } 3142 flush_writes(ohci); 3143 context_stop(&ctx->context); 3144 tasklet_kill(&ctx->context.tasklet); 3145 3146 return 0; 3147} 3148 3149static void ohci_free_iso_context(struct fw_iso_context *base) 3150{ 3151 struct fw_ohci *ohci = fw_ohci(base->card); 3152 struct iso_context *ctx = container_of(base, struct iso_context, base); 3153 unsigned long flags; 3154 int index; 3155 3156 ohci_stop_iso(base); 3157 context_release(&ctx->context); 3158 free_page((unsigned long)ctx->header); 3159 3160 spin_lock_irqsave(&ohci->lock, flags); 3161 3162 switch (base->type) { 3163 case FW_ISO_CONTEXT_TRANSMIT: 3164 index = ctx - ohci->it_context_list; 3165 ohci->it_context_mask |= 1 << index; 3166 break; 3167 3168 case FW_ISO_CONTEXT_RECEIVE: 3169 index = ctx - ohci->ir_context_list; 3170 ohci->ir_context_mask |= 1 << index; 3171 ohci->ir_context_channels |= 1ULL << base->channel; 3172 break; 3173 3174 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3175 index = ctx - ohci->ir_context_list; 3176 ohci->ir_context_mask |= 1 << index; 3177 ohci->ir_context_channels |= ohci->mc_channels; 3178 ohci->mc_channels = 0; 3179 ohci->mc_allocated = false; 3180 break; 3181 } 3182 3183 spin_unlock_irqrestore(&ohci->lock, flags); 3184} 3185 3186static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) 3187{ 3188 struct fw_ohci *ohci = fw_ohci(base->card); 3189 unsigned long flags; 3190 int ret; 3191 3192 switch (base->type) { 3193 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3194 3195 spin_lock_irqsave(&ohci->lock, flags); 3196 3197 /* Don't allow multichannel to grab other contexts' channels. */ 3198 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { 3199 *channels = ohci->ir_context_channels; 3200 ret = -EBUSY; 3201 } else { 3202 set_multichannel_mask(ohci, *channels); 3203 ret = 0; 3204 } 3205 3206 spin_unlock_irqrestore(&ohci->lock, flags); 3207 3208 break; 3209 default: 3210 ret = -EINVAL; 3211 } 3212 3213 return ret; 3214} 3215 3216#ifdef CONFIG_PM 3217static void ohci_resume_iso_dma(struct fw_ohci *ohci) 3218{ 3219 int i; 3220 struct iso_context *ctx; 3221 3222 for (i = 0 ; i < ohci->n_ir ; i++) { 3223 ctx = &ohci->ir_context_list[i]; 3224 if (ctx->context.running) 3225 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3226 } 3227 3228 for (i = 0 ; i < ohci->n_it ; i++) { 3229 ctx = &ohci->it_context_list[i]; 3230 if (ctx->context.running) 3231 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); 3232 } 3233} 3234#endif 3235 3236static int queue_iso_transmit(struct iso_context *ctx, 3237 struct fw_iso_packet *packet, 3238 struct fw_iso_buffer *buffer, 3239 unsigned long payload) 3240{ 3241 struct descriptor *d, *last, *pd; 3242 struct fw_iso_packet *p; 3243 __le32 *header; 3244 dma_addr_t d_bus, page_bus; 3245 u32 z, header_z, payload_z, irq; 3246 u32 payload_index, payload_end_index, next_page_index; 3247 int page, end_page, i, length, offset; 3248 3249 p = packet; 3250 payload_index = payload; 3251 3252 if (p->skip) 3253 z = 1; 3254 else 3255 z = 2; 3256 if (p->header_length > 0) 3257 z++; 3258 3259 /* Determine the first page the payload isn't contained in. */ 3260 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; 3261 if (p->payload_length > 0) 3262 payload_z = end_page - (payload_index >> PAGE_SHIFT); 3263 else 3264 payload_z = 0; 3265 3266 z += payload_z; 3267 3268 /* Get header size in number of descriptors. */ 3269 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); 3270 3271 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); 3272 if (d == NULL) 3273 return -ENOMEM; 3274 3275 if (!p->skip) { 3276 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); 3277 d[0].req_count = cpu_to_le16(8); 3278 /* 3279 * Link the skip address to this descriptor itself. This causes 3280 * a context to skip a cycle whenever lost cycles or FIFO 3281 * overruns occur, without dropping the data. The application 3282 * should then decide whether this is an error condition or not. 3283 * FIXME: Make the context's cycle-lost behaviour configurable? 3284 */ 3285 d[0].branch_address = cpu_to_le32(d_bus | z); 3286 3287 header = (__le32 *) &d[1]; 3288 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | 3289 IT_HEADER_TAG(p->tag) | 3290 IT_HEADER_TCODE(TCODE_STREAM_DATA) | 3291 IT_HEADER_CHANNEL(ctx->base.channel) | 3292 IT_HEADER_SPEED(ctx->base.speed)); 3293 header[1] = 3294 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + 3295 p->payload_length)); 3296 } 3297 3298 if (p->header_length > 0) { 3299 d[2].req_count = cpu_to_le16(p->header_length); 3300 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); 3301 memcpy(&d[z], p->header, p->header_length); 3302 } 3303 3304 pd = d + z - payload_z; 3305 payload_end_index = payload_index + p->payload_length; 3306 for (i = 0; i < payload_z; i++) { 3307 page = payload_index >> PAGE_SHIFT; 3308 offset = payload_index & ~PAGE_MASK; 3309 next_page_index = (page + 1) << PAGE_SHIFT; 3310 length = 3311 min(next_page_index, payload_end_index) - payload_index; 3312 pd[i].req_count = cpu_to_le16(length); 3313 3314 page_bus = page_private(buffer->pages[page]); 3315 pd[i].data_address = cpu_to_le32(page_bus + offset); 3316 3317 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3318 page_bus, offset, length, 3319 DMA_TO_DEVICE); 3320 3321 payload_index += length; 3322 } 3323 3324 if (p->interrupt) 3325 irq = DESCRIPTOR_IRQ_ALWAYS; 3326 else 3327 irq = DESCRIPTOR_NO_IRQ; 3328 3329 last = z == 2 ? d : d + z - 1; 3330 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | 3331 DESCRIPTOR_STATUS | 3332 DESCRIPTOR_BRANCH_ALWAYS | 3333 irq); 3334 3335 context_append(&ctx->context, d, z, header_z); 3336 3337 return 0; 3338} 3339 3340static int queue_iso_packet_per_buffer(struct iso_context *ctx, 3341 struct fw_iso_packet *packet, 3342 struct fw_iso_buffer *buffer, 3343 unsigned long payload) 3344{ 3345 struct device *device = ctx->context.ohci->card.device; 3346 struct descriptor *d, *pd; 3347 dma_addr_t d_bus, page_bus; 3348 u32 z, header_z, rest; 3349 int i, j, length; 3350 int page, offset, packet_count, header_size, payload_per_buffer; 3351 3352 /* 3353 * The OHCI controller puts the isochronous header and trailer in the 3354 * buffer, so we need at least 8 bytes. 3355 */ 3356 packet_count = packet->header_length / ctx->base.header_size; 3357 header_size = max(ctx->base.header_size, (size_t)8); 3358 3359 /* Get header size in number of descriptors. */ 3360 header_z = DIV_ROUND_UP(header_size, sizeof(*d)); 3361 page = payload >> PAGE_SHIFT; 3362 offset = payload & ~PAGE_MASK; 3363 payload_per_buffer = packet->payload_length / packet_count; 3364 3365 for (i = 0; i < packet_count; i++) { 3366 /* d points to the header descriptor */ 3367 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; 3368 d = context_get_descriptors(&ctx->context, 3369 z + header_z, &d_bus); 3370 if (d == NULL) 3371 return -ENOMEM; 3372 3373 d->control = cpu_to_le16(DESCRIPTOR_STATUS | 3374 DESCRIPTOR_INPUT_MORE); 3375 if (packet->skip && i == 0) 3376 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3377 d->req_count = cpu_to_le16(header_size); 3378 d->res_count = d->req_count; 3379 d->transfer_status = 0; 3380 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); 3381 3382 rest = payload_per_buffer; 3383 pd = d; 3384 for (j = 1; j < z; j++) { 3385 pd++; 3386 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3387 DESCRIPTOR_INPUT_MORE); 3388 3389 if (offset + rest < PAGE_SIZE) 3390 length = rest; 3391 else 3392 length = PAGE_SIZE - offset; 3393 pd->req_count = cpu_to_le16(length); 3394 pd->res_count = pd->req_count; 3395 pd->transfer_status = 0; 3396 3397 page_bus = page_private(buffer->pages[page]); 3398 pd->data_address = cpu_to_le32(page_bus + offset); 3399 3400 dma_sync_single_range_for_device(device, page_bus, 3401 offset, length, 3402 DMA_FROM_DEVICE); 3403 3404 offset = (offset + length) & ~PAGE_MASK; 3405 rest -= length; 3406 if (offset == 0) 3407 page++; 3408 } 3409 pd->control = cpu_to_le16(DESCRIPTOR_STATUS | 3410 DESCRIPTOR_INPUT_LAST | 3411 DESCRIPTOR_BRANCH_ALWAYS); 3412 if (packet->interrupt && i == packet_count - 1) 3413 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3414 3415 context_append(&ctx->context, d, z, header_z); 3416 } 3417 3418 return 0; 3419} 3420 3421static int queue_iso_buffer_fill(struct iso_context *ctx, 3422 struct fw_iso_packet *packet, 3423 struct fw_iso_buffer *buffer, 3424 unsigned long payload) 3425{ 3426 struct descriptor *d; 3427 dma_addr_t d_bus, page_bus; 3428 int page, offset, rest, z, i, length; 3429 3430 page = payload >> PAGE_SHIFT; 3431 offset = payload & ~PAGE_MASK; 3432 rest = packet->payload_length; 3433 3434 /* We need one descriptor for each page in the buffer. */ 3435 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); 3436 3437 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) 3438 return -EFAULT; 3439 3440 for (i = 0; i < z; i++) { 3441 d = context_get_descriptors(&ctx->context, 1, &d_bus); 3442 if (d == NULL) 3443 return -ENOMEM; 3444 3445 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | 3446 DESCRIPTOR_BRANCH_ALWAYS); 3447 if (packet->skip && i == 0) 3448 d->control |= cpu_to_le16(DESCRIPTOR_WAIT); 3449 if (packet->interrupt && i == z - 1) 3450 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); 3451 3452 if (offset + rest < PAGE_SIZE) 3453 length = rest; 3454 else 3455 length = PAGE_SIZE - offset; 3456 d->req_count = cpu_to_le16(length); 3457 d->res_count = d->req_count; 3458 d->transfer_status = 0; 3459 3460 page_bus = page_private(buffer->pages[page]); 3461 d->data_address = cpu_to_le32(page_bus + offset); 3462 3463 dma_sync_single_range_for_device(ctx->context.ohci->card.device, 3464 page_bus, offset, length, 3465 DMA_FROM_DEVICE); 3466 3467 rest -= length; 3468 offset = 0; 3469 page++; 3470 3471 context_append(&ctx->context, d, 1, 0); 3472 } 3473 3474 return 0; 3475} 3476 3477static int ohci_queue_iso(struct fw_iso_context *base, 3478 struct fw_iso_packet *packet, 3479 struct fw_iso_buffer *buffer, 3480 unsigned long payload) 3481{ 3482 struct iso_context *ctx = container_of(base, struct iso_context, base); 3483 unsigned long flags; 3484 int ret = -ENOSYS; 3485 3486 spin_lock_irqsave(&ctx->context.ohci->lock, flags); 3487 switch (base->type) { 3488 case FW_ISO_CONTEXT_TRANSMIT: 3489 ret = queue_iso_transmit(ctx, packet, buffer, payload); 3490 break; 3491 case FW_ISO_CONTEXT_RECEIVE: 3492 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); 3493 break; 3494 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3495 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); 3496 break; 3497 } 3498 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); 3499 3500 return ret; 3501} 3502 3503static void ohci_flush_queue_iso(struct fw_iso_context *base) 3504{ 3505 struct context *ctx = 3506 &container_of(base, struct iso_context, base)->context; 3507 3508 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 3509} 3510 3511static int ohci_flush_iso_completions(struct fw_iso_context *base) 3512{ 3513 struct iso_context *ctx = container_of(base, struct iso_context, base); 3514 int ret = 0; 3515 3516 tasklet_disable(&ctx->context.tasklet); 3517 3518 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) { 3519 context_tasklet((unsigned long)&ctx->context); 3520 3521 switch (base->type) { 3522 case FW_ISO_CONTEXT_TRANSMIT: 3523 case FW_ISO_CONTEXT_RECEIVE: 3524 if (ctx->header_length != 0) 3525 flush_iso_completions(ctx); 3526 break; 3527 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: 3528 if (ctx->mc_completed != 0) 3529 flush_ir_buffer_fill(ctx); 3530 break; 3531 default: 3532 ret = -ENOSYS; 3533 } 3534 3535 clear_bit_unlock(0, &ctx->flushing_completions); 3536 smp_mb__after_atomic(); 3537 } 3538 3539 tasklet_enable(&ctx->context.tasklet); 3540 3541 return ret; 3542} 3543 3544static const struct fw_card_driver ohci_driver = { 3545 .enable = ohci_enable, 3546 .read_phy_reg = ohci_read_phy_reg, 3547 .update_phy_reg = ohci_update_phy_reg, 3548 .set_config_rom = ohci_set_config_rom, 3549 .send_request = ohci_send_request, 3550 .send_response = ohci_send_response, 3551 .cancel_packet = ohci_cancel_packet, 3552 .enable_phys_dma = ohci_enable_phys_dma, 3553 .read_csr = ohci_read_csr, 3554 .write_csr = ohci_write_csr, 3555 3556 .allocate_iso_context = ohci_allocate_iso_context, 3557 .free_iso_context = ohci_free_iso_context, 3558 .set_iso_channels = ohci_set_iso_channels, 3559 .queue_iso = ohci_queue_iso, 3560 .flush_queue_iso = ohci_flush_queue_iso, 3561 .flush_iso_completions = ohci_flush_iso_completions, 3562 .start_iso = ohci_start_iso, 3563 .stop_iso = ohci_stop_iso, 3564}; 3565 3566#ifdef CONFIG_PPC_PMAC 3567static void pmac_ohci_on(struct pci_dev *dev) 3568{ 3569 if (machine_is(powermac)) { 3570 struct device_node *ofn = pci_device_to_OF_node(dev); 3571 3572 if (ofn) { 3573 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); 3574 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); 3575 } 3576 } 3577} 3578 3579static void pmac_ohci_off(struct pci_dev *dev) 3580{ 3581 if (machine_is(powermac)) { 3582 struct device_node *ofn = pci_device_to_OF_node(dev); 3583 3584 if (ofn) { 3585 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); 3586 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); 3587 } 3588 } 3589} 3590#else 3591static inline void pmac_ohci_on(struct pci_dev *dev) {} 3592static inline void pmac_ohci_off(struct pci_dev *dev) {} 3593#endif /* CONFIG_PPC_PMAC */ 3594 3595static int pci_probe(struct pci_dev *dev, 3596 const struct pci_device_id *ent) 3597{ 3598 struct fw_ohci *ohci; 3599 u32 bus_options, max_receive, link_speed, version; 3600 u64 guid; 3601 int i, err; 3602 size_t size; 3603 3604 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) { 3605 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n"); 3606 return -ENOSYS; 3607 } 3608 3609 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); 3610 if (ohci == NULL) { 3611 err = -ENOMEM; 3612 goto fail; 3613 } 3614 3615 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); 3616 3617 pmac_ohci_on(dev); 3618 3619 err = pci_enable_device(dev); 3620 if (err) { 3621 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); 3622 goto fail_free; 3623 } 3624 3625 pci_set_master(dev); 3626 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); 3627 pci_set_drvdata(dev, ohci); 3628 3629 spin_lock_init(&ohci->lock); 3630 mutex_init(&ohci->phy_reg_mutex); 3631 3632 INIT_WORK(&ohci->bus_reset_work, bus_reset_work); 3633 3634 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) || 3635 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) { 3636 ohci_err(ohci, "invalid MMIO resource\n"); 3637 err = -ENXIO; 3638 goto fail_disable; 3639 } 3640 3641 err = pci_request_region(dev, 0, ohci_driver_name); 3642 if (err) { 3643 ohci_err(ohci, "MMIO resource unavailable\n"); 3644 goto fail_disable; 3645 } 3646 3647 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); 3648 if (ohci->registers == NULL) { 3649 ohci_err(ohci, "failed to remap registers\n"); 3650 err = -ENXIO; 3651 goto fail_iomem; 3652 } 3653 3654 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) 3655 if ((ohci_quirks[i].vendor == dev->vendor) && 3656 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || 3657 ohci_quirks[i].device == dev->device) && 3658 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || 3659 ohci_quirks[i].revision >= dev->revision)) { 3660 ohci->quirks = ohci_quirks[i].flags; 3661 break; 3662 } 3663 if (param_quirks) 3664 ohci->quirks = param_quirks; 3665 3666 if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev)) 3667 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; 3668 3669 /* 3670 * Because dma_alloc_coherent() allocates at least one page, 3671 * we save space by using a common buffer for the AR request/ 3672 * response descriptors and the self IDs buffer. 3673 */ 3674 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); 3675 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); 3676 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, 3677 PAGE_SIZE, 3678 &ohci->misc_buffer_bus, 3679 GFP_KERNEL); 3680 if (!ohci->misc_buffer) { 3681 err = -ENOMEM; 3682 goto fail_iounmap; 3683 } 3684 3685 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, 3686 OHCI1394_AsReqRcvContextControlSet); 3687 if (err < 0) 3688 goto fail_misc_buf; 3689 3690 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, 3691 OHCI1394_AsRspRcvContextControlSet); 3692 if (err < 0) 3693 goto fail_arreq_ctx; 3694 3695 err = context_init(&ohci->at_request_ctx, ohci, 3696 OHCI1394_AsReqTrContextControlSet, handle_at_packet); 3697 if (err < 0) 3698 goto fail_arrsp_ctx; 3699 3700 err = context_init(&ohci->at_response_ctx, ohci, 3701 OHCI1394_AsRspTrContextControlSet, handle_at_packet); 3702 if (err < 0) 3703 goto fail_atreq_ctx; 3704 3705 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); 3706 ohci->ir_context_channels = ~0ULL; 3707 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); 3708 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); 3709 ohci->ir_context_mask = ohci->ir_context_support; 3710 ohci->n_ir = hweight32(ohci->ir_context_mask); 3711 size = sizeof(struct iso_context) * ohci->n_ir; 3712 ohci->ir_context_list = kzalloc(size, GFP_KERNEL); 3713 3714 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); 3715 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); 3716 /* JMicron JMB38x often shows 0 at first read, just ignore it */ 3717 if (!ohci->it_context_support) { 3718 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); 3719 ohci->it_context_support = 0xf; 3720 } 3721 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); 3722 ohci->it_context_mask = ohci->it_context_support; 3723 ohci->n_it = hweight32(ohci->it_context_mask); 3724 size = sizeof(struct iso_context) * ohci->n_it; 3725 ohci->it_context_list = kzalloc(size, GFP_KERNEL); 3726 3727 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { 3728 err = -ENOMEM; 3729 goto fail_contexts; 3730 } 3731 3732 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; 3733 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; 3734 3735 bus_options = reg_read(ohci, OHCI1394_BusOptions); 3736 max_receive = (bus_options >> 12) & 0xf; 3737 link_speed = bus_options & 0x7; 3738 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | 3739 reg_read(ohci, OHCI1394_GUIDLo); 3740 3741 if (!(ohci->quirks & QUIRK_NO_MSI)) 3742 pci_enable_msi(dev); 3743 if (request_irq(dev->irq, irq_handler, 3744 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, 3745 ohci_driver_name, ohci)) { 3746 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq); 3747 err = -EIO; 3748 goto fail_msi; 3749 } 3750 3751 err = fw_card_add(&ohci->card, max_receive, link_speed, guid); 3752 if (err) 3753 goto fail_irq; 3754 3755 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; 3756 ohci_notice(ohci, 3757 "added OHCI v%x.%x device as card %d, " 3758 "%d IR + %d IT contexts, quirks 0x%x%s\n", 3759 version >> 16, version & 0xff, ohci->card.index, 3760 ohci->n_ir, ohci->n_it, ohci->quirks, 3761 reg_read(ohci, OHCI1394_PhyUpperBound) ? 3762 ", physUB" : ""); 3763 3764 return 0; 3765 3766 fail_irq: 3767 free_irq(dev->irq, ohci); 3768 fail_msi: 3769 pci_disable_msi(dev); 3770 fail_contexts: 3771 kfree(ohci->ir_context_list); 3772 kfree(ohci->it_context_list); 3773 context_release(&ohci->at_response_ctx); 3774 fail_atreq_ctx: 3775 context_release(&ohci->at_request_ctx); 3776 fail_arrsp_ctx: 3777 ar_context_release(&ohci->ar_response_ctx); 3778 fail_arreq_ctx: 3779 ar_context_release(&ohci->ar_request_ctx); 3780 fail_misc_buf: 3781 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3782 ohci->misc_buffer, ohci->misc_buffer_bus); 3783 fail_iounmap: 3784 pci_iounmap(dev, ohci->registers); 3785 fail_iomem: 3786 pci_release_region(dev, 0); 3787 fail_disable: 3788 pci_disable_device(dev); 3789 fail_free: 3790 kfree(ohci); 3791 pmac_ohci_off(dev); 3792 fail: 3793 return err; 3794} 3795 3796static void pci_remove(struct pci_dev *dev) 3797{ 3798 struct fw_ohci *ohci = pci_get_drvdata(dev); 3799 3800 /* 3801 * If the removal is happening from the suspend state, LPS won't be 3802 * enabled and host registers (eg., IntMaskClear) won't be accessible. 3803 */ 3804 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) { 3805 reg_write(ohci, OHCI1394_IntMaskClear, ~0); 3806 flush_writes(ohci); 3807 } 3808 cancel_work_sync(&ohci->bus_reset_work); 3809 fw_core_remove_card(&ohci->card); 3810 3811 /* 3812 * FIXME: Fail all pending packets here, now that the upper 3813 * layers can't queue any more. 3814 */ 3815 3816 software_reset(ohci); 3817 free_irq(dev->irq, ohci); 3818 3819 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) 3820 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3821 ohci->next_config_rom, ohci->next_config_rom_bus); 3822 if (ohci->config_rom) 3823 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, 3824 ohci->config_rom, ohci->config_rom_bus); 3825 ar_context_release(&ohci->ar_request_ctx); 3826 ar_context_release(&ohci->ar_response_ctx); 3827 dma_free_coherent(ohci->card.device, PAGE_SIZE, 3828 ohci->misc_buffer, ohci->misc_buffer_bus); 3829 context_release(&ohci->at_request_ctx); 3830 context_release(&ohci->at_response_ctx); 3831 kfree(ohci->it_context_list); 3832 kfree(ohci->ir_context_list); 3833 pci_disable_msi(dev); 3834 pci_iounmap(dev, ohci->registers); 3835 pci_release_region(dev, 0); 3836 pci_disable_device(dev); 3837 kfree(ohci); 3838 pmac_ohci_off(dev); 3839 3840 dev_notice(&dev->dev, "removed fw-ohci device\n"); 3841} 3842 3843#ifdef CONFIG_PM 3844static int pci_suspend(struct pci_dev *dev, pm_message_t state) 3845{ 3846 struct fw_ohci *ohci = pci_get_drvdata(dev); 3847 int err; 3848 3849 software_reset(ohci); 3850 err = pci_save_state(dev); 3851 if (err) { 3852 ohci_err(ohci, "pci_save_state failed\n"); 3853 return err; 3854 } 3855 err = pci_set_power_state(dev, pci_choose_state(dev, state)); 3856 if (err) 3857 ohci_err(ohci, "pci_set_power_state failed with %d\n", err); 3858 pmac_ohci_off(dev); 3859 3860 return 0; 3861} 3862 3863static int pci_resume(struct pci_dev *dev) 3864{ 3865 struct fw_ohci *ohci = pci_get_drvdata(dev); 3866 int err; 3867 3868 pmac_ohci_on(dev); 3869 pci_set_power_state(dev, PCI_D0); 3870 pci_restore_state(dev); 3871 err = pci_enable_device(dev); 3872 if (err) { 3873 ohci_err(ohci, "pci_enable_device failed\n"); 3874 return err; 3875 } 3876 3877 /* Some systems don't setup GUID register on resume from ram */ 3878 if (!reg_read(ohci, OHCI1394_GUIDLo) && 3879 !reg_read(ohci, OHCI1394_GUIDHi)) { 3880 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); 3881 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); 3882 } 3883 3884 err = ohci_enable(&ohci->card, NULL, 0); 3885 if (err) 3886 return err; 3887 3888 ohci_resume_iso_dma(ohci); 3889 3890 return 0; 3891} 3892#endif 3893 3894static const struct pci_device_id pci_table[] = { 3895 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, 3896 { } 3897}; 3898 3899MODULE_DEVICE_TABLE(pci, pci_table); 3900 3901static struct pci_driver fw_ohci_pci_driver = { 3902 .name = ohci_driver_name, 3903 .id_table = pci_table, 3904 .probe = pci_probe, 3905 .remove = pci_remove, 3906#ifdef CONFIG_PM 3907 .resume = pci_resume, 3908 .suspend = pci_suspend, 3909#endif 3910}; 3911 3912static int __init fw_ohci_init(void) 3913{ 3914 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0); 3915 if (!selfid_workqueue) 3916 return -ENOMEM; 3917 3918 return pci_register_driver(&fw_ohci_pci_driver); 3919} 3920 3921static void __exit fw_ohci_cleanup(void) 3922{ 3923 pci_unregister_driver(&fw_ohci_pci_driver); 3924 destroy_workqueue(selfid_workqueue); 3925} 3926 3927module_init(fw_ohci_init); 3928module_exit(fw_ohci_cleanup); 3929 3930MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); 3931MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); 3932MODULE_LICENSE("GPL"); 3933 3934/* Provide a module alias so root-on-sbp2 initrds don't break. */ 3935MODULE_ALIAS("ohci1394"); 3936