1/*
2 * Freescale MPC85xx Memory Controller kernel module
3 * Author: Dave Jiang <djiang@mvista.com>
4 *
5 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
6 * the terms of the GNU General Public License version 2. This program
7 * is licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 */
11#ifndef _MPC85XX_EDAC_H_
12#define _MPC85XX_EDAC_H_
13
14#define MPC85XX_REVISION " Ver: 2.0.0"
15#define EDAC_MOD_STR	"MPC85xx_edac"
16
17#define mpc85xx_printk(level, fmt, arg...) \
18	edac_printk(level, "MPC85xx", fmt, ##arg)
19
20/*
21 * L2 Err defines
22 */
23#define MPC85XX_L2_ERRINJHI	0x0000
24#define MPC85XX_L2_ERRINJLO	0x0004
25#define MPC85XX_L2_ERRINJCTL	0x0008
26#define MPC85XX_L2_CAPTDATAHI	0x0020
27#define MPC85XX_L2_CAPTDATALO	0x0024
28#define MPC85XX_L2_CAPTECC	0x0028
29#define MPC85XX_L2_ERRDET	0x0040
30#define MPC85XX_L2_ERRDIS	0x0044
31#define MPC85XX_L2_ERRINTEN	0x0048
32#define MPC85XX_L2_ERRATTR	0x004c
33#define MPC85XX_L2_ERRADDR	0x0050
34#define MPC85XX_L2_ERRCTL	0x0058
35
36/* Error Interrupt Enable */
37#define L2_EIE_L2CFGINTEN	0x1
38#define L2_EIE_SBECCINTEN	0x4
39#define L2_EIE_MBECCINTEN	0x8
40#define L2_EIE_TPARINTEN	0x10
41#define L2_EIE_MASK	(L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
42			L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
43
44/* Error Detect */
45#define L2_EDE_L2CFGERR		0x1
46#define L2_EDE_SBECCERR		0x4
47#define L2_EDE_MBECCERR		0x8
48#define L2_EDE_TPARERR		0x10
49#define L2_EDE_MULL2ERR		0x80000000
50
51#define L2_EDE_CE_MASK	L2_EDE_SBECCERR
52#define L2_EDE_UE_MASK	(L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
53			L2_EDE_TPARERR)
54#define L2_EDE_MASK	(L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
55			L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
56
57/*
58 * PCI Err defines
59 */
60#define PCI_EDE_TOE			0x00000001
61#define PCI_EDE_SCM			0x00000002
62#define PCI_EDE_IRMSV			0x00000004
63#define PCI_EDE_ORMSV			0x00000008
64#define PCI_EDE_OWMSV			0x00000010
65#define PCI_EDE_TGT_ABRT		0x00000020
66#define PCI_EDE_MST_ABRT		0x00000040
67#define PCI_EDE_TGT_PERR		0x00000080
68#define PCI_EDE_MST_PERR		0x00000100
69#define PCI_EDE_RCVD_SERR		0x00000200
70#define PCI_EDE_ADDR_PERR		0x00000400
71#define PCI_EDE_MULTI_ERR		0x80000000
72
73#define PCI_EDE_PERR_MASK	(PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
74				PCI_EDE_ADDR_PERR)
75
76#define MPC85XX_PCI_ERR_DR		0x0000
77#define MPC85XX_PCI_ERR_CAP_DR		0x0004
78#define MPC85XX_PCI_ERR_EN		0x0008
79#define   PEX_ERR_ICCAIE_EN_BIT		0x00020000
80#define MPC85XX_PCI_ERR_ATTRIB		0x000c
81#define MPC85XX_PCI_ERR_ADDR		0x0010
82#define   PEX_ERR_ICCAD_DISR_BIT	0x00020000
83#define MPC85XX_PCI_ERR_EXT_ADDR	0x0014
84#define MPC85XX_PCI_ERR_DL		0x0018
85#define MPC85XX_PCI_ERR_DH		0x001c
86#define MPC85XX_PCI_GAS_TIMR		0x0020
87#define MPC85XX_PCI_PCIX_TIMR		0x0024
88#define MPC85XX_PCIE_ERR_CAP_R0		0x0028
89#define MPC85XX_PCIE_ERR_CAP_R1		0x002c
90#define MPC85XX_PCIE_ERR_CAP_R2		0x0030
91#define MPC85XX_PCIE_ERR_CAP_R3		0x0034
92
93struct mpc85xx_l2_pdata {
94	char *name;
95	int edac_idx;
96	void __iomem *l2_vbase;
97	int irq;
98};
99
100struct mpc85xx_pci_pdata {
101	char *name;
102	bool is_pcie;
103	int edac_idx;
104	void __iomem *pci_vbase;
105	int irq;
106};
107
108#endif
109