1/*
2 * Intel 82860 Memory Controller kernel module
3 * (C) 2005 Red Hat (http://www.redhat.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Ben Woodard <woodard@redhat.com>
8 * shamelessly copied from and based upon the edac_i82875 driver
9 * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/edac.h>
17#include "edac_module.h"
18
19#define EDAC_MOD_STR	"i82860_edac"
20
21#define i82860_printk(level, fmt, arg...) \
22	edac_printk(level, "i82860", fmt, ##arg)
23
24#define i82860_mc_printk(mci, level, fmt, arg...) \
25	edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
26
27#ifndef PCI_DEVICE_ID_INTEL_82860_0
28#define PCI_DEVICE_ID_INTEL_82860_0	0x2531
29#endif				/* PCI_DEVICE_ID_INTEL_82860_0 */
30
31#define I82860_MCHCFG 0x50
32#define I82860_GBA 0x60
33#define I82860_GBA_MASK 0x7FF
34#define I82860_GBA_SHIFT 24
35#define I82860_ERRSTS 0xC8
36#define I82860_EAP 0xE4
37#define I82860_DERRCTL_STS 0xE2
38
39enum i82860_chips {
40	I82860 = 0,
41};
42
43struct i82860_dev_info {
44	const char *ctl_name;
45};
46
47struct i82860_error_info {
48	u16 errsts;
49	u32 eap;
50	u16 derrsyn;
51	u16 errsts2;
52};
53
54static const struct i82860_dev_info i82860_devs[] = {
55	[I82860] = {
56		.ctl_name = "i82860"},
57};
58
59static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code
60					 * has already registered driver
61					 */
62static struct edac_pci_ctl_info *i82860_pci;
63
64static void i82860_get_error_info(struct mem_ctl_info *mci,
65				struct i82860_error_info *info)
66{
67	struct pci_dev *pdev;
68
69	pdev = to_pci_dev(mci->pdev);
70
71	/*
72	 * This is a mess because there is no atomic way to read all the
73	 * registers at once and the registers can transition from CE being
74	 * overwritten by UE.
75	 */
76	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
77	pci_read_config_dword(pdev, I82860_EAP, &info->eap);
78	pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
79	pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
80
81	pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
82
83	/*
84	 * If the error is the same for both reads then the first set of reads
85	 * is valid.  If there is a change then there is a CE no info and the
86	 * second set of reads is valid and should be UE info.
87	 */
88	if (!(info->errsts2 & 0x0003))
89		return;
90
91	if ((info->errsts ^ info->errsts2) & 0x0003) {
92		pci_read_config_dword(pdev, I82860_EAP, &info->eap);
93		pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
94	}
95}
96
97static int i82860_process_error_info(struct mem_ctl_info *mci,
98				struct i82860_error_info *info,
99				int handle_errors)
100{
101	struct dimm_info *dimm;
102	int row;
103
104	if (!(info->errsts2 & 0x0003))
105		return 0;
106
107	if (!handle_errors)
108		return 1;
109
110	if ((info->errsts ^ info->errsts2) & 0x0003) {
111		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
112				     -1, -1, -1, "UE overwrote CE", "");
113		info->errsts = info->errsts2;
114	}
115
116	info->eap >>= PAGE_SHIFT;
117	row = edac_mc_find_csrow_by_page(mci, info->eap);
118	dimm = mci->csrows[row]->channels[0]->dimm;
119
120	if (info->errsts & 0x0002)
121		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
122				     info->eap, 0, 0,
123				     dimm->location[0], dimm->location[1], -1,
124				     "i82860 UE", "");
125	else
126		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
127				     info->eap, 0, info->derrsyn,
128				     dimm->location[0], dimm->location[1], -1,
129				     "i82860 CE", "");
130
131	return 1;
132}
133
134static void i82860_check(struct mem_ctl_info *mci)
135{
136	struct i82860_error_info info;
137
138	edac_dbg(1, "MC%d\n", mci->mc_idx);
139	i82860_get_error_info(mci, &info);
140	i82860_process_error_info(mci, &info, 1);
141}
142
143static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
144{
145	unsigned long last_cumul_size;
146	u16 mchcfg_ddim;	/* DRAM Data Integrity Mode 0=none, 2=edac */
147	u16 value;
148	u32 cumul_size;
149	struct csrow_info *csrow;
150	struct dimm_info *dimm;
151	int index;
152
153	pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
154	mchcfg_ddim = mchcfg_ddim & 0x180;
155	last_cumul_size = 0;
156
157	/* The group row boundary (GRA) reg values are boundary address
158	 * for each DRAM row with a granularity of 16MB.  GRA regs are
159	 * cumulative; therefore GRA15 will contain the total memory contained
160	 * in all eight rows.
161	 */
162	for (index = 0; index < mci->nr_csrows; index++) {
163		csrow = mci->csrows[index];
164		dimm = csrow->channels[0]->dimm;
165
166		pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
167		cumul_size = (value & I82860_GBA_MASK) <<
168			(I82860_GBA_SHIFT - PAGE_SHIFT);
169		edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
170
171		if (cumul_size == last_cumul_size)
172			continue;	/* not populated */
173
174		csrow->first_page = last_cumul_size;
175		csrow->last_page = cumul_size - 1;
176		dimm->nr_pages = cumul_size - last_cumul_size;
177		last_cumul_size = cumul_size;
178		dimm->grain = 1 << 12;	/* I82860_EAP has 4KiB reolution */
179		dimm->mtype = MEM_RMBS;
180		dimm->dtype = DEV_UNKNOWN;
181		dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
182	}
183}
184
185static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
186{
187	struct mem_ctl_info *mci;
188	struct edac_mc_layer layers[2];
189	struct i82860_error_info discard;
190
191	/*
192	 * RDRAM has channels but these don't map onto the csrow abstraction.
193	 * According with the datasheet, there are 2 Rambus channels, supporting
194	 * up to 16 direct RDRAM devices.
195	 * The device groups from the GRA registers seem to map reasonably
196	 * well onto the notion of a chip select row.
197	 * There are 16 GRA registers and since the name is associated with
198	 * the channel and the GRA registers map to physical devices so we are
199	 * going to make 1 channel for group.
200	 */
201	layers[0].type = EDAC_MC_LAYER_CHANNEL;
202	layers[0].size = 2;
203	layers[0].is_virt_csrow = true;
204	layers[1].type = EDAC_MC_LAYER_SLOT;
205	layers[1].size = 8;
206	layers[1].is_virt_csrow = true;
207	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
208	if (!mci)
209		return -ENOMEM;
210
211	edac_dbg(3, "init mci\n");
212	mci->pdev = &pdev->dev;
213	mci->mtype_cap = MEM_FLAG_DDR;
214	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
215	/* I"m not sure about this but I think that all RDRAM is SECDED */
216	mci->edac_cap = EDAC_FLAG_SECDED;
217	mci->mod_name = EDAC_MOD_STR;
218	mci->ctl_name = i82860_devs[dev_idx].ctl_name;
219	mci->dev_name = pci_name(pdev);
220	mci->edac_check = i82860_check;
221	mci->ctl_page_to_phys = NULL;
222	i82860_init_csrows(mci, pdev);
223	i82860_get_error_info(mci, &discard);	/* clear counters */
224
225	/* Here we assume that we will never see multiple instances of this
226	 * type of memory controller.  The ID is therefore hardcoded to 0.
227	 */
228	if (edac_mc_add_mc(mci)) {
229		edac_dbg(3, "failed edac_mc_add_mc()\n");
230		goto fail;
231	}
232
233	/* allocating generic PCI control info */
234	i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
235	if (!i82860_pci) {
236		printk(KERN_WARNING
237			"%s(): Unable to create PCI control\n",
238			__func__);
239		printk(KERN_WARNING
240			"%s(): PCI error report via EDAC not setup\n",
241			__func__);
242	}
243
244	/* get this far and it's successful */
245	edac_dbg(3, "success\n");
246
247	return 0;
248
249fail:
250	edac_mc_free(mci);
251	return -ENODEV;
252}
253
254/* returns count (>= 0), or negative on error */
255static int i82860_init_one(struct pci_dev *pdev,
256			   const struct pci_device_id *ent)
257{
258	int rc;
259
260	edac_dbg(0, "\n");
261	i82860_printk(KERN_INFO, "i82860 init one\n");
262
263	if (pci_enable_device(pdev) < 0)
264		return -EIO;
265
266	rc = i82860_probe1(pdev, ent->driver_data);
267
268	if (rc == 0)
269		mci_pdev = pci_dev_get(pdev);
270
271	return rc;
272}
273
274static void i82860_remove_one(struct pci_dev *pdev)
275{
276	struct mem_ctl_info *mci;
277
278	edac_dbg(0, "\n");
279
280	if (i82860_pci)
281		edac_pci_release_generic_ctl(i82860_pci);
282
283	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
284		return;
285
286	edac_mc_free(mci);
287}
288
289static const struct pci_device_id i82860_pci_tbl[] = {
290	{
291	 PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
292	 I82860},
293	{
294	 0,
295	 }			/* 0 terminated list. */
296};
297
298MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
299
300static struct pci_driver i82860_driver = {
301	.name = EDAC_MOD_STR,
302	.probe = i82860_init_one,
303	.remove = i82860_remove_one,
304	.id_table = i82860_pci_tbl,
305};
306
307static int __init i82860_init(void)
308{
309	int pci_rc;
310
311	edac_dbg(3, "\n");
312
313       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
314       opstate_init();
315
316	if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
317		goto fail0;
318
319	if (!mci_pdev) {
320		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
321					PCI_DEVICE_ID_INTEL_82860_0, NULL);
322
323		if (mci_pdev == NULL) {
324			edac_dbg(0, "860 pci_get_device fail\n");
325			pci_rc = -ENODEV;
326			goto fail1;
327		}
328
329		pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
330
331		if (pci_rc < 0) {
332			edac_dbg(0, "860 init fail\n");
333			pci_rc = -ENODEV;
334			goto fail1;
335		}
336	}
337
338	return 0;
339
340fail1:
341	pci_unregister_driver(&i82860_driver);
342
343fail0:
344	pci_dev_put(mci_pdev);
345	return pci_rc;
346}
347
348static void __exit i82860_exit(void)
349{
350	edac_dbg(3, "\n");
351	pci_unregister_driver(&i82860_driver);
352	pci_dev_put(mci_pdev);
353}
354
355module_init(i82860_init);
356module_exit(i82860_exit);
357
358MODULE_LICENSE("GPL");
359MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
360		"Ben Woodard <woodard@redhat.com>");
361MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
362
363module_param(edac_op_state, int, 0444);
364MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
365