18c2ecf20Sopenharmony_ci# 28c2ecf20Sopenharmony_ci# EDAC Kconfig 38c2ecf20Sopenharmony_ci# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 48c2ecf20Sopenharmony_ci# Licensed and distributed under the GPL 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ciconfig EDAC_ATOMIC_SCRUB 78c2ecf20Sopenharmony_ci bool 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ciconfig EDAC_SUPPORT 108c2ecf20Sopenharmony_ci bool 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_cimenuconfig EDAC 138c2ecf20Sopenharmony_ci tristate "EDAC (Error Detection And Correction) reporting" 148c2ecf20Sopenharmony_ci depends on HAS_IOMEM && EDAC_SUPPORT && RAS 158c2ecf20Sopenharmony_ci help 168c2ecf20Sopenharmony_ci EDAC is a subsystem along with hardware-specific drivers designed to 178c2ecf20Sopenharmony_ci report hardware errors. These are low-level errors that are reported 188c2ecf20Sopenharmony_ci in the CPU or supporting chipset or other subsystems: 198c2ecf20Sopenharmony_ci memory errors, cache errors, PCI errors, thermal throttling, etc.. 208c2ecf20Sopenharmony_ci If unsure, select 'Y'. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci The mailing list for the EDAC project is linux-edac@vger.kernel.org. 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ciif EDAC 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ciconfig EDAC_LEGACY_SYSFS 278c2ecf20Sopenharmony_ci bool "EDAC legacy sysfs" 288c2ecf20Sopenharmony_ci default y 298c2ecf20Sopenharmony_ci help 308c2ecf20Sopenharmony_ci Enable the compatibility sysfs nodes. 318c2ecf20Sopenharmony_ci Use 'Y' if your edac utilities aren't ported to work with the newer 328c2ecf20Sopenharmony_ci structures. 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ciconfig EDAC_DEBUG 358c2ecf20Sopenharmony_ci bool "Debugging" 368c2ecf20Sopenharmony_ci select DEBUG_FS 378c2ecf20Sopenharmony_ci help 388c2ecf20Sopenharmony_ci This turns on debugging information for the entire EDAC subsystem. 398c2ecf20Sopenharmony_ci You do so by inserting edac_module with "edac_debug_level=x." Valid 408c2ecf20Sopenharmony_ci levels are 0-4 (from low to high) and by default it is set to 2. 418c2ecf20Sopenharmony_ci Usually you should select 'N' here. 428c2ecf20Sopenharmony_ci 438c2ecf20Sopenharmony_ciconfig EDAC_DECODE_MCE 448c2ecf20Sopenharmony_ci tristate "Decode MCEs in human-readable form (only on AMD for now)" 458c2ecf20Sopenharmony_ci depends on CPU_SUP_AMD && X86_MCE_AMD 468c2ecf20Sopenharmony_ci default y 478c2ecf20Sopenharmony_ci help 488c2ecf20Sopenharmony_ci Enable this option if you want to decode Machine Check Exceptions 498c2ecf20Sopenharmony_ci occurring on your machine in human-readable form. 508c2ecf20Sopenharmony_ci 518c2ecf20Sopenharmony_ci You should definitely say Y here in case you want to decode MCEs 528c2ecf20Sopenharmony_ci which occur really early upon boot, before the module infrastructure 538c2ecf20Sopenharmony_ci has been initialized. 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ciconfig EDAC_GHES 568c2ecf20Sopenharmony_ci bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 578c2ecf20Sopenharmony_ci depends on ACPI_APEI_GHES && (EDAC=y) 588c2ecf20Sopenharmony_ci help 598c2ecf20Sopenharmony_ci Not all machines support hardware-driven error report. Some of those 608c2ecf20Sopenharmony_ci provide a BIOS-driven error report mechanism via ACPI, using the 618c2ecf20Sopenharmony_ci APEI/GHES driver. By enabling this option, the error reports provided 628c2ecf20Sopenharmony_ci by GHES are sent to userspace via the EDAC API. 638c2ecf20Sopenharmony_ci 648c2ecf20Sopenharmony_ci When this option is enabled, it will disable the hardware-driven 658c2ecf20Sopenharmony_ci mechanisms, if a GHES BIOS is detected, entering into the 668c2ecf20Sopenharmony_ci "Firmware First" mode. 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci It should be noticed that keeping both GHES and a hardware-driven 698c2ecf20Sopenharmony_ci error mechanism won't work well, as BIOS will race with OS, while 708c2ecf20Sopenharmony_ci reading the error registers. So, if you want to not use "Firmware 718c2ecf20Sopenharmony_ci first" GHES error mechanism, you should disable GHES either at 728c2ecf20Sopenharmony_ci compilation time or by passing "ghes.disable=1" Kernel parameter 738c2ecf20Sopenharmony_ci at boot time. 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci In doubt, say 'Y'. 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_ciconfig EDAC_AMD64 788c2ecf20Sopenharmony_ci tristate "AMD64 (Opteron, Athlon64)" 798c2ecf20Sopenharmony_ci depends on AMD_NB && EDAC_DECODE_MCE 808c2ecf20Sopenharmony_ci help 818c2ecf20Sopenharmony_ci Support for error detection and correction of DRAM ECC errors on 828c2ecf20Sopenharmony_ci the AMD64 families (>= K8) of memory controllers. 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ciconfig EDAC_AMD64_ERROR_INJECTION 858c2ecf20Sopenharmony_ci bool "Sysfs HW Error injection facilities" 868c2ecf20Sopenharmony_ci depends on EDAC_AMD64 878c2ecf20Sopenharmony_ci help 888c2ecf20Sopenharmony_ci Recent Opterons (Family 10h and later) provide for Memory Error 898c2ecf20Sopenharmony_ci Injection into the ECC detection circuits. The amd64_edac module 908c2ecf20Sopenharmony_ci allows the operator/user to inject Uncorrectable and Correctable 918c2ecf20Sopenharmony_ci errors into DRAM. 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_ci When enabled, in each of the respective memory controller directories 948c2ecf20Sopenharmony_ci (/sys/devices/system/edac/mc/mcX), there are 3 input files: 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci - inject_section (0..3, 16-byte section of 64-byte cacheline), 978c2ecf20Sopenharmony_ci - inject_word (0..8, 16-bit word of 16-byte section), 988c2ecf20Sopenharmony_ci - inject_ecc_vector (hex ecc vector: select bits of inject word) 998c2ecf20Sopenharmony_ci 1008c2ecf20Sopenharmony_ci In addition, there are two control files, inject_read and inject_write, 1018c2ecf20Sopenharmony_ci which trigger the DRAM ECC Read and Write respectively. 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ciconfig EDAC_AL_MC 1048c2ecf20Sopenharmony_ci tristate "Amazon's Annapurna Lab Memory Controller" 1058c2ecf20Sopenharmony_ci depends on (ARCH_ALPINE || COMPILE_TEST) 1068c2ecf20Sopenharmony_ci help 1078c2ecf20Sopenharmony_ci Support for error detection and correction for Amazon's Annapurna 1088c2ecf20Sopenharmony_ci Labs Alpine chips which allow 1 bit correction and 2 bits detection. 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_ciconfig EDAC_AMD76X 1118c2ecf20Sopenharmony_ci tristate "AMD 76x (760, 762, 768)" 1128c2ecf20Sopenharmony_ci depends on PCI && X86_32 1138c2ecf20Sopenharmony_ci help 1148c2ecf20Sopenharmony_ci Support for error detection and correction on the AMD 76x 1158c2ecf20Sopenharmony_ci series of chipsets used with the Athlon processor. 1168c2ecf20Sopenharmony_ci 1178c2ecf20Sopenharmony_ciconfig EDAC_E7XXX 1188c2ecf20Sopenharmony_ci tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 1198c2ecf20Sopenharmony_ci depends on PCI && X86_32 1208c2ecf20Sopenharmony_ci help 1218c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1228c2ecf20Sopenharmony_ci E7205, E7500, E7501 and E7505 server chipsets. 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ciconfig EDAC_E752X 1258c2ecf20Sopenharmony_ci tristate "Intel e752x (e7520, e7525, e7320) and 3100" 1268c2ecf20Sopenharmony_ci depends on PCI && X86 1278c2ecf20Sopenharmony_ci help 1288c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1298c2ecf20Sopenharmony_ci E7520, E7525, E7320 server chipsets. 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_ciconfig EDAC_I82443BXGX 1328c2ecf20Sopenharmony_ci tristate "Intel 82443BX/GX (440BX/GX)" 1338c2ecf20Sopenharmony_ci depends on PCI && X86_32 1348c2ecf20Sopenharmony_ci depends on BROKEN 1358c2ecf20Sopenharmony_ci help 1368c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1378c2ecf20Sopenharmony_ci 82443BX/GX memory controllers (440BX/GX chipsets). 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_ciconfig EDAC_I82875P 1408c2ecf20Sopenharmony_ci tristate "Intel 82875p (D82875P, E7210)" 1418c2ecf20Sopenharmony_ci depends on PCI && X86_32 1428c2ecf20Sopenharmony_ci help 1438c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1448c2ecf20Sopenharmony_ci DP82785P and E7210 server chipsets. 1458c2ecf20Sopenharmony_ci 1468c2ecf20Sopenharmony_ciconfig EDAC_I82975X 1478c2ecf20Sopenharmony_ci tristate "Intel 82975x (D82975x)" 1488c2ecf20Sopenharmony_ci depends on PCI && X86 1498c2ecf20Sopenharmony_ci help 1508c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1518c2ecf20Sopenharmony_ci DP82975x server chipsets. 1528c2ecf20Sopenharmony_ci 1538c2ecf20Sopenharmony_ciconfig EDAC_I3000 1548c2ecf20Sopenharmony_ci tristate "Intel 3000/3010" 1558c2ecf20Sopenharmony_ci depends on PCI && X86 1568c2ecf20Sopenharmony_ci help 1578c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1588c2ecf20Sopenharmony_ci 3000 and 3010 server chipsets. 1598c2ecf20Sopenharmony_ci 1608c2ecf20Sopenharmony_ciconfig EDAC_I3200 1618c2ecf20Sopenharmony_ci tristate "Intel 3200" 1628c2ecf20Sopenharmony_ci depends on PCI && X86 1638c2ecf20Sopenharmony_ci help 1648c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1658c2ecf20Sopenharmony_ci 3200 and 3210 server chipsets. 1668c2ecf20Sopenharmony_ci 1678c2ecf20Sopenharmony_ciconfig EDAC_IE31200 1688c2ecf20Sopenharmony_ci tristate "Intel e312xx" 1698c2ecf20Sopenharmony_ci depends on PCI && X86 1708c2ecf20Sopenharmony_ci help 1718c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1728c2ecf20Sopenharmony_ci E3-1200 based DRAM controllers. 1738c2ecf20Sopenharmony_ci 1748c2ecf20Sopenharmony_ciconfig EDAC_X38 1758c2ecf20Sopenharmony_ci tristate "Intel X38" 1768c2ecf20Sopenharmony_ci depends on PCI && X86 1778c2ecf20Sopenharmony_ci help 1788c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 1798c2ecf20Sopenharmony_ci X38 server chipsets. 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_ciconfig EDAC_I5400 1828c2ecf20Sopenharmony_ci tristate "Intel 5400 (Seaburg) chipsets" 1838c2ecf20Sopenharmony_ci depends on PCI && X86 1848c2ecf20Sopenharmony_ci help 1858c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 1868c2ecf20Sopenharmony_ci i5400 MCH chipset (Seaburg). 1878c2ecf20Sopenharmony_ci 1888c2ecf20Sopenharmony_ciconfig EDAC_I7CORE 1898c2ecf20Sopenharmony_ci tristate "Intel i7 Core (Nehalem) processors" 1908c2ecf20Sopenharmony_ci depends on PCI && X86 && X86_MCE_INTEL 1918c2ecf20Sopenharmony_ci help 1928c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 1938c2ecf20Sopenharmony_ci i7 Core (Nehalem) Integrated Memory Controller that exists on 1948c2ecf20Sopenharmony_ci newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 1958c2ecf20Sopenharmony_ci and Xeon 55xx processors. 1968c2ecf20Sopenharmony_ci 1978c2ecf20Sopenharmony_ciconfig EDAC_I82860 1988c2ecf20Sopenharmony_ci tristate "Intel 82860" 1998c2ecf20Sopenharmony_ci depends on PCI && X86_32 2008c2ecf20Sopenharmony_ci help 2018c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 2028c2ecf20Sopenharmony_ci 82860 chipset. 2038c2ecf20Sopenharmony_ci 2048c2ecf20Sopenharmony_ciconfig EDAC_R82600 2058c2ecf20Sopenharmony_ci tristate "Radisys 82600 embedded chipset" 2068c2ecf20Sopenharmony_ci depends on PCI && X86_32 2078c2ecf20Sopenharmony_ci help 2088c2ecf20Sopenharmony_ci Support for error detection and correction on the Radisys 2098c2ecf20Sopenharmony_ci 82600 embedded chipset. 2108c2ecf20Sopenharmony_ci 2118c2ecf20Sopenharmony_ciconfig EDAC_I5000 2128c2ecf20Sopenharmony_ci tristate "Intel Greencreek/Blackford chipset" 2138c2ecf20Sopenharmony_ci depends on X86 && PCI 2148c2ecf20Sopenharmony_ci help 2158c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2168c2ecf20Sopenharmony_ci Greekcreek/Blackford chipsets. 2178c2ecf20Sopenharmony_ci 2188c2ecf20Sopenharmony_ciconfig EDAC_I5100 2198c2ecf20Sopenharmony_ci tristate "Intel San Clemente MCH" 2208c2ecf20Sopenharmony_ci depends on X86 && PCI 2218c2ecf20Sopenharmony_ci help 2228c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2238c2ecf20Sopenharmony_ci San Clemente MCH. 2248c2ecf20Sopenharmony_ci 2258c2ecf20Sopenharmony_ciconfig EDAC_I7300 2268c2ecf20Sopenharmony_ci tristate "Intel Clarksboro MCH" 2278c2ecf20Sopenharmony_ci depends on X86 && PCI 2288c2ecf20Sopenharmony_ci help 2298c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2308c2ecf20Sopenharmony_ci Clarksboro MCH (Intel 7300 chipset). 2318c2ecf20Sopenharmony_ci 2328c2ecf20Sopenharmony_ciconfig EDAC_SBRIDGE 2338c2ecf20Sopenharmony_ci tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 2348c2ecf20Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 2358c2ecf20Sopenharmony_ci help 2368c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2378c2ecf20Sopenharmony_ci Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 2388c2ecf20Sopenharmony_ci 2398c2ecf20Sopenharmony_ciconfig EDAC_SKX 2408c2ecf20Sopenharmony_ci tristate "Intel Skylake server Integrated MC" 2418c2ecf20Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 2428c2ecf20Sopenharmony_ci depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 2438c2ecf20Sopenharmony_ci select DMI 2448c2ecf20Sopenharmony_ci select ACPI_ADXL 2458c2ecf20Sopenharmony_ci help 2468c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2478c2ecf20Sopenharmony_ci Skylake server Integrated Memory Controllers. If your 2488c2ecf20Sopenharmony_ci system has non-volatile DIMMs you should also manually 2498c2ecf20Sopenharmony_ci select CONFIG_ACPI_NFIT. 2508c2ecf20Sopenharmony_ci 2518c2ecf20Sopenharmony_ciconfig EDAC_I10NM 2528c2ecf20Sopenharmony_ci tristate "Intel 10nm server Integrated MC" 2538c2ecf20Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 2548c2ecf20Sopenharmony_ci depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 2558c2ecf20Sopenharmony_ci select DMI 2568c2ecf20Sopenharmony_ci select ACPI_ADXL 2578c2ecf20Sopenharmony_ci help 2588c2ecf20Sopenharmony_ci Support for error detection and correction the Intel 2598c2ecf20Sopenharmony_ci 10nm server Integrated Memory Controllers. If your 2608c2ecf20Sopenharmony_ci system has non-volatile DIMMs you should also manually 2618c2ecf20Sopenharmony_ci select CONFIG_ACPI_NFIT. 2628c2ecf20Sopenharmony_ci 2638c2ecf20Sopenharmony_ciconfig EDAC_PND2 2648c2ecf20Sopenharmony_ci tristate "Intel Pondicherry2" 2658c2ecf20Sopenharmony_ci depends on PCI && X86_64 && X86_MCE_INTEL 2668c2ecf20Sopenharmony_ci help 2678c2ecf20Sopenharmony_ci Support for error detection and correction on the Intel 2688c2ecf20Sopenharmony_ci Pondicherry2 Integrated Memory Controller. This SoC IP is 2698c2ecf20Sopenharmony_ci first used on the Apollo Lake platform and Denverton 2708c2ecf20Sopenharmony_ci micro-server but may appear on others in the future. 2718c2ecf20Sopenharmony_ci 2728c2ecf20Sopenharmony_ciconfig EDAC_MPC85XX 2738c2ecf20Sopenharmony_ci bool "Freescale MPC83xx / MPC85xx" 2748c2ecf20Sopenharmony_ci depends on FSL_SOC && EDAC=y 2758c2ecf20Sopenharmony_ci help 2768c2ecf20Sopenharmony_ci Support for error detection and correction on the Freescale 2778c2ecf20Sopenharmony_ci MPC8349, MPC8560, MPC8540, MPC8548, T4240 2788c2ecf20Sopenharmony_ci 2798c2ecf20Sopenharmony_ciconfig EDAC_LAYERSCAPE 2808c2ecf20Sopenharmony_ci tristate "Freescale Layerscape DDR" 2818c2ecf20Sopenharmony_ci depends on ARCH_LAYERSCAPE || SOC_LS1021A 2828c2ecf20Sopenharmony_ci help 2838c2ecf20Sopenharmony_ci Support for error detection and correction on Freescale memory 2848c2ecf20Sopenharmony_ci controllers on Layerscape SoCs. 2858c2ecf20Sopenharmony_ci 2868c2ecf20Sopenharmony_ciconfig EDAC_MV64X60 2878c2ecf20Sopenharmony_ci tristate "Marvell MV64x60" 2888c2ecf20Sopenharmony_ci depends on MV64X60 2898c2ecf20Sopenharmony_ci help 2908c2ecf20Sopenharmony_ci Support for error detection and correction on the Marvell 2918c2ecf20Sopenharmony_ci MV64360 and MV64460 chipsets. 2928c2ecf20Sopenharmony_ci 2938c2ecf20Sopenharmony_ciconfig EDAC_PASEMI 2948c2ecf20Sopenharmony_ci tristate "PA Semi PWRficient" 2958c2ecf20Sopenharmony_ci depends on PPC_PASEMI && PCI 2968c2ecf20Sopenharmony_ci help 2978c2ecf20Sopenharmony_ci Support for error detection and correction on PA Semi 2988c2ecf20Sopenharmony_ci PWRficient. 2998c2ecf20Sopenharmony_ci 3008c2ecf20Sopenharmony_ciconfig EDAC_CELL 3018c2ecf20Sopenharmony_ci tristate "Cell Broadband Engine memory controller" 3028c2ecf20Sopenharmony_ci depends on PPC_CELL_COMMON 3038c2ecf20Sopenharmony_ci help 3048c2ecf20Sopenharmony_ci Support for error detection and correction on the 3058c2ecf20Sopenharmony_ci Cell Broadband Engine internal memory controller 3068c2ecf20Sopenharmony_ci on platform without a hypervisor 3078c2ecf20Sopenharmony_ci 3088c2ecf20Sopenharmony_ciconfig EDAC_PPC4XX 3098c2ecf20Sopenharmony_ci tristate "PPC4xx IBM DDR2 Memory Controller" 3108c2ecf20Sopenharmony_ci depends on 4xx 3118c2ecf20Sopenharmony_ci help 3128c2ecf20Sopenharmony_ci This enables support for EDAC on the ECC memory used 3138c2ecf20Sopenharmony_ci with the IBM DDR2 memory controller found in various 3148c2ecf20Sopenharmony_ci PowerPC 4xx embedded processors such as the 405EX[r], 3158c2ecf20Sopenharmony_ci 440SP, 440SPe, 460EX, 460GT and 460SX. 3168c2ecf20Sopenharmony_ci 3178c2ecf20Sopenharmony_ciconfig EDAC_AMD8131 3188c2ecf20Sopenharmony_ci tristate "AMD8131 HyperTransport PCI-X Tunnel" 3198c2ecf20Sopenharmony_ci depends on PCI && PPC_MAPLE 3208c2ecf20Sopenharmony_ci help 3218c2ecf20Sopenharmony_ci Support for error detection and correction on the 3228c2ecf20Sopenharmony_ci AMD8131 HyperTransport PCI-X Tunnel chip. 3238c2ecf20Sopenharmony_ci Note, add more Kconfig dependency if it's adopted 3248c2ecf20Sopenharmony_ci on some machine other than Maple. 3258c2ecf20Sopenharmony_ci 3268c2ecf20Sopenharmony_ciconfig EDAC_AMD8111 3278c2ecf20Sopenharmony_ci tristate "AMD8111 HyperTransport I/O Hub" 3288c2ecf20Sopenharmony_ci depends on PCI && PPC_MAPLE 3298c2ecf20Sopenharmony_ci help 3308c2ecf20Sopenharmony_ci Support for error detection and correction on the 3318c2ecf20Sopenharmony_ci AMD8111 HyperTransport I/O Hub chip. 3328c2ecf20Sopenharmony_ci Note, add more Kconfig dependency if it's adopted 3338c2ecf20Sopenharmony_ci on some machine other than Maple. 3348c2ecf20Sopenharmony_ci 3358c2ecf20Sopenharmony_ciconfig EDAC_CPC925 3368c2ecf20Sopenharmony_ci tristate "IBM CPC925 Memory Controller (PPC970FX)" 3378c2ecf20Sopenharmony_ci depends on PPC64 3388c2ecf20Sopenharmony_ci help 3398c2ecf20Sopenharmony_ci Support for error detection and correction on the 3408c2ecf20Sopenharmony_ci IBM CPC925 Bridge and Memory Controller, which is 3418c2ecf20Sopenharmony_ci a companion chip to the PowerPC 970 family of 3428c2ecf20Sopenharmony_ci processors. 3438c2ecf20Sopenharmony_ci 3448c2ecf20Sopenharmony_ciconfig EDAC_HIGHBANK_MC 3458c2ecf20Sopenharmony_ci tristate "Highbank Memory Controller" 3468c2ecf20Sopenharmony_ci depends on ARCH_HIGHBANK 3478c2ecf20Sopenharmony_ci help 3488c2ecf20Sopenharmony_ci Support for error detection and correction on the 3498c2ecf20Sopenharmony_ci Calxeda Highbank memory controller. 3508c2ecf20Sopenharmony_ci 3518c2ecf20Sopenharmony_ciconfig EDAC_HIGHBANK_L2 3528c2ecf20Sopenharmony_ci tristate "Highbank L2 Cache" 3538c2ecf20Sopenharmony_ci depends on ARCH_HIGHBANK 3548c2ecf20Sopenharmony_ci help 3558c2ecf20Sopenharmony_ci Support for error detection and correction on the 3568c2ecf20Sopenharmony_ci Calxeda Highbank memory controller. 3578c2ecf20Sopenharmony_ci 3588c2ecf20Sopenharmony_ciconfig EDAC_OCTEON_PC 3598c2ecf20Sopenharmony_ci tristate "Cavium Octeon Primary Caches" 3608c2ecf20Sopenharmony_ci depends on CPU_CAVIUM_OCTEON 3618c2ecf20Sopenharmony_ci help 3628c2ecf20Sopenharmony_ci Support for error detection and correction on the primary caches of 3638c2ecf20Sopenharmony_ci the cnMIPS cores of Cavium Octeon family SOCs. 3648c2ecf20Sopenharmony_ci 3658c2ecf20Sopenharmony_ciconfig EDAC_OCTEON_L2C 3668c2ecf20Sopenharmony_ci tristate "Cavium Octeon Secondary Caches (L2C)" 3678c2ecf20Sopenharmony_ci depends on CAVIUM_OCTEON_SOC 3688c2ecf20Sopenharmony_ci help 3698c2ecf20Sopenharmony_ci Support for error detection and correction on the 3708c2ecf20Sopenharmony_ci Cavium Octeon family of SOCs. 3718c2ecf20Sopenharmony_ci 3728c2ecf20Sopenharmony_ciconfig EDAC_OCTEON_LMC 3738c2ecf20Sopenharmony_ci tristate "Cavium Octeon DRAM Memory Controller (LMC)" 3748c2ecf20Sopenharmony_ci depends on CAVIUM_OCTEON_SOC 3758c2ecf20Sopenharmony_ci help 3768c2ecf20Sopenharmony_ci Support for error detection and correction on the 3778c2ecf20Sopenharmony_ci Cavium Octeon family of SOCs. 3788c2ecf20Sopenharmony_ci 3798c2ecf20Sopenharmony_ciconfig EDAC_OCTEON_PCI 3808c2ecf20Sopenharmony_ci tristate "Cavium Octeon PCI Controller" 3818c2ecf20Sopenharmony_ci depends on PCI && CAVIUM_OCTEON_SOC 3828c2ecf20Sopenharmony_ci help 3838c2ecf20Sopenharmony_ci Support for error detection and correction on the 3848c2ecf20Sopenharmony_ci Cavium Octeon family of SOCs. 3858c2ecf20Sopenharmony_ci 3868c2ecf20Sopenharmony_ciconfig EDAC_THUNDERX 3878c2ecf20Sopenharmony_ci tristate "Cavium ThunderX EDAC" 3888c2ecf20Sopenharmony_ci depends on ARM64 3898c2ecf20Sopenharmony_ci depends on PCI 3908c2ecf20Sopenharmony_ci help 3918c2ecf20Sopenharmony_ci Support for error detection and correction on the 3928c2ecf20Sopenharmony_ci Cavium ThunderX memory controllers (LMC), Cache 3938c2ecf20Sopenharmony_ci Coherent Processor Interconnect (CCPI) and L2 cache 3948c2ecf20Sopenharmony_ci blocks (TAD, CBC, MCI). 3958c2ecf20Sopenharmony_ci 3968c2ecf20Sopenharmony_ciconfig EDAC_ALTERA 3978c2ecf20Sopenharmony_ci bool "Altera SOCFPGA ECC" 3988c2ecf20Sopenharmony_ci depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10) 3998c2ecf20Sopenharmony_ci help 4008c2ecf20Sopenharmony_ci Support for error detection and correction on the 4018c2ecf20Sopenharmony_ci Altera SOCs. This is the global enable for the 4028c2ecf20Sopenharmony_ci various Altera peripherals. 4038c2ecf20Sopenharmony_ci 4048c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_SDRAM 4058c2ecf20Sopenharmony_ci bool "Altera SDRAM ECC" 4068c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y 4078c2ecf20Sopenharmony_ci help 4088c2ecf20Sopenharmony_ci Support for error detection and correction on the 4098c2ecf20Sopenharmony_ci Altera SDRAM Memory for Altera SoCs. Note that the 4108c2ecf20Sopenharmony_ci preloader must initialize the SDRAM before loading 4118c2ecf20Sopenharmony_ci the kernel. 4128c2ecf20Sopenharmony_ci 4138c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_L2C 4148c2ecf20Sopenharmony_ci bool "Altera L2 Cache ECC" 4158c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && CACHE_L2X0 4168c2ecf20Sopenharmony_ci help 4178c2ecf20Sopenharmony_ci Support for error detection and correction on the 4188c2ecf20Sopenharmony_ci Altera L2 cache Memory for Altera SoCs. This option 4198c2ecf20Sopenharmony_ci requires L2 cache. 4208c2ecf20Sopenharmony_ci 4218c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_OCRAM 4228c2ecf20Sopenharmony_ci bool "Altera On-Chip RAM ECC" 4238c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 4248c2ecf20Sopenharmony_ci help 4258c2ecf20Sopenharmony_ci Support for error detection and correction on the 4268c2ecf20Sopenharmony_ci Altera On-Chip RAM Memory for Altera SoCs. 4278c2ecf20Sopenharmony_ci 4288c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_ETHERNET 4298c2ecf20Sopenharmony_ci bool "Altera Ethernet FIFO ECC" 4308c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y 4318c2ecf20Sopenharmony_ci help 4328c2ecf20Sopenharmony_ci Support for error detection and correction on the 4338c2ecf20Sopenharmony_ci Altera Ethernet FIFO Memory for Altera SoCs. 4348c2ecf20Sopenharmony_ci 4358c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_NAND 4368c2ecf20Sopenharmony_ci bool "Altera NAND FIFO ECC" 4378c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && MTD_NAND_DENALI 4388c2ecf20Sopenharmony_ci help 4398c2ecf20Sopenharmony_ci Support for error detection and correction on the 4408c2ecf20Sopenharmony_ci Altera NAND FIFO Memory for Altera SoCs. 4418c2ecf20Sopenharmony_ci 4428c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_DMA 4438c2ecf20Sopenharmony_ci bool "Altera DMA FIFO ECC" 4448c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && PL330_DMA=y 4458c2ecf20Sopenharmony_ci help 4468c2ecf20Sopenharmony_ci Support for error detection and correction on the 4478c2ecf20Sopenharmony_ci Altera DMA FIFO Memory for Altera SoCs. 4488c2ecf20Sopenharmony_ci 4498c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_USB 4508c2ecf20Sopenharmony_ci bool "Altera USB FIFO ECC" 4518c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && USB_DWC2 4528c2ecf20Sopenharmony_ci help 4538c2ecf20Sopenharmony_ci Support for error detection and correction on the 4548c2ecf20Sopenharmony_ci Altera USB FIFO Memory for Altera SoCs. 4558c2ecf20Sopenharmony_ci 4568c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_QSPI 4578c2ecf20Sopenharmony_ci bool "Altera QSPI FIFO ECC" 4588c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 4598c2ecf20Sopenharmony_ci help 4608c2ecf20Sopenharmony_ci Support for error detection and correction on the 4618c2ecf20Sopenharmony_ci Altera QSPI FIFO Memory for Altera SoCs. 4628c2ecf20Sopenharmony_ci 4638c2ecf20Sopenharmony_ciconfig EDAC_ALTERA_SDMMC 4648c2ecf20Sopenharmony_ci bool "Altera SDMMC FIFO ECC" 4658c2ecf20Sopenharmony_ci depends on EDAC_ALTERA=y && MMC_DW 4668c2ecf20Sopenharmony_ci help 4678c2ecf20Sopenharmony_ci Support for error detection and correction on the 4688c2ecf20Sopenharmony_ci Altera SDMMC FIFO Memory for Altera SoCs. 4698c2ecf20Sopenharmony_ci 4708c2ecf20Sopenharmony_ciconfig EDAC_SIFIVE 4718c2ecf20Sopenharmony_ci bool "Sifive platform EDAC driver" 4728c2ecf20Sopenharmony_ci depends on EDAC=y && SIFIVE_L2 4738c2ecf20Sopenharmony_ci help 4748c2ecf20Sopenharmony_ci Support for error detection and correction on the SiFive SoCs. 4758c2ecf20Sopenharmony_ci 4768c2ecf20Sopenharmony_ciconfig EDAC_ARMADA_XP 4778c2ecf20Sopenharmony_ci bool "Marvell Armada XP DDR and L2 Cache ECC" 4788c2ecf20Sopenharmony_ci depends on MACH_MVEBU_V7 4798c2ecf20Sopenharmony_ci help 4808c2ecf20Sopenharmony_ci Support for error correction and detection on the Marvell Aramada XP 4818c2ecf20Sopenharmony_ci DDR RAM and L2 cache controllers. 4828c2ecf20Sopenharmony_ci 4838c2ecf20Sopenharmony_ciconfig EDAC_SYNOPSYS 4848c2ecf20Sopenharmony_ci tristate "Synopsys DDR Memory Controller" 4858c2ecf20Sopenharmony_ci depends on ARCH_ZYNQ || ARCH_ZYNQMP 4868c2ecf20Sopenharmony_ci help 4878c2ecf20Sopenharmony_ci Support for error detection and correction on the Synopsys DDR 4888c2ecf20Sopenharmony_ci memory controller. 4898c2ecf20Sopenharmony_ci 4908c2ecf20Sopenharmony_ciconfig EDAC_XGENE 4918c2ecf20Sopenharmony_ci tristate "APM X-Gene SoC" 4928c2ecf20Sopenharmony_ci depends on (ARM64 || COMPILE_TEST) 4938c2ecf20Sopenharmony_ci help 4948c2ecf20Sopenharmony_ci Support for error detection and correction on the 4958c2ecf20Sopenharmony_ci APM X-Gene family of SOCs. 4968c2ecf20Sopenharmony_ci 4978c2ecf20Sopenharmony_ciconfig EDAC_TI 4988c2ecf20Sopenharmony_ci tristate "Texas Instruments DDR3 ECC Controller" 4998c2ecf20Sopenharmony_ci depends on ARCH_KEYSTONE || SOC_DRA7XX 5008c2ecf20Sopenharmony_ci help 5018c2ecf20Sopenharmony_ci Support for error detection and correction on the TI SoCs. 5028c2ecf20Sopenharmony_ci 5038c2ecf20Sopenharmony_ciconfig EDAC_QCOM 5048c2ecf20Sopenharmony_ci tristate "QCOM EDAC Controller" 5058c2ecf20Sopenharmony_ci depends on ARCH_QCOM && QCOM_LLCC 5068c2ecf20Sopenharmony_ci help 5078c2ecf20Sopenharmony_ci Support for error detection and correction on the 5088c2ecf20Sopenharmony_ci Qualcomm Technologies, Inc. SoCs. 5098c2ecf20Sopenharmony_ci 5108c2ecf20Sopenharmony_ci This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 5118c2ecf20Sopenharmony_ci As of now, it supports error reporting for Last Level Cache Controller (LLCC) 5128c2ecf20Sopenharmony_ci of Tag RAM and Data RAM. 5138c2ecf20Sopenharmony_ci 5148c2ecf20Sopenharmony_ci For debugging issues having to do with stability and overall system 5158c2ecf20Sopenharmony_ci health, you should probably say 'Y' here. 5168c2ecf20Sopenharmony_ci 5178c2ecf20Sopenharmony_ciconfig EDAC_ASPEED 5188c2ecf20Sopenharmony_ci tristate "Aspeed AST 2500 SoC" 5198c2ecf20Sopenharmony_ci depends on MACH_ASPEED_G5 5208c2ecf20Sopenharmony_ci help 5218c2ecf20Sopenharmony_ci Support for error detection and correction on the Aspeed AST 2500 SoC. 5228c2ecf20Sopenharmony_ci 5238c2ecf20Sopenharmony_ci First, ECC must be configured in the bootloader. Then, this driver 5248c2ecf20Sopenharmony_ci will expose error counters via the EDAC kernel framework. 5258c2ecf20Sopenharmony_ci 5268c2ecf20Sopenharmony_ciconfig EDAC_BLUEFIELD 5278c2ecf20Sopenharmony_ci tristate "Mellanox BlueField Memory ECC" 5288c2ecf20Sopenharmony_ci depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 5298c2ecf20Sopenharmony_ci help 5308c2ecf20Sopenharmony_ci Support for error detection and correction on the 5318c2ecf20Sopenharmony_ci Mellanox BlueField SoCs. 5328c2ecf20Sopenharmony_ci 5338c2ecf20Sopenharmony_ciconfig EDAC_DMC520 5348c2ecf20Sopenharmony_ci tristate "ARM DMC-520 ECC" 5358c2ecf20Sopenharmony_ci depends on ARM64 5368c2ecf20Sopenharmony_ci help 5378c2ecf20Sopenharmony_ci Support for error detection and correction on the 5388c2ecf20Sopenharmony_ci SoCs with ARM DMC-520 DRAM controller. 5398c2ecf20Sopenharmony_ci 5408c2ecf20Sopenharmony_ciendif # EDAC 541