1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * SiFive FU540 Platform DMA driver
4 * Copyright (C) 2019 SiFive
5 *
6 * Based partially on:
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
10 *
11 * See the following sources for further documentation:
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 *   SiFive FU540-C000 v1.0
14 *   https://static.dev.sifive.com/FU540-C000-v1.0.pdf
15 */
16#ifndef _SF_PDMA_H
17#define _SF_PDMA_H
18
19#include <linux/dmaengine.h>
20#include <linux/dma-direction.h>
21
22#include "../dmaengine.h"
23#include "../virt-dma.h"
24
25#define PDMA_NR_CH					4
26
27#if (PDMA_NR_CH != 4)
28#error "Please define PDMA_NR_CH to 4"
29#endif
30
31#define PDMA_BASE_ADDR					0x3000000
32#define PDMA_CHAN_OFFSET				0x1000
33
34/* Register Offset */
35#define PDMA_CTRL					0x000
36#define PDMA_XFER_TYPE					0x004
37#define PDMA_XFER_SIZE					0x008
38#define PDMA_DST_ADDR					0x010
39#define PDMA_SRC_ADDR					0x018
40#define PDMA_ACT_TYPE					0x104 /* Read-only */
41#define PDMA_REMAINING_BYTE				0x108 /* Read-only */
42#define PDMA_CUR_DST_ADDR				0x110 /* Read-only*/
43#define PDMA_CUR_SRC_ADDR				0x118 /* Read-only*/
44
45/* CTRL */
46#define PDMA_CLEAR_CTRL					0x0
47#define PDMA_CLAIM_MASK					GENMASK(0, 0)
48#define PDMA_RUN_MASK					GENMASK(1, 1)
49#define PDMA_ENABLE_DONE_INT_MASK			GENMASK(14, 14)
50#define PDMA_ENABLE_ERR_INT_MASK			GENMASK(15, 15)
51#define PDMA_DONE_STATUS_MASK				GENMASK(30, 30)
52#define PDMA_ERR_STATUS_MASK				GENMASK(31, 31)
53
54/* Transfer Type */
55#define PDMA_FULL_SPEED					0xFF000008
56
57/* Error Recovery */
58#define MAX_RETRY					1
59
60#define SF_PDMA_REG_BASE(ch)	(pdma->membase + (PDMA_CHAN_OFFSET * (ch)))
61
62struct pdma_regs {
63	/* read-write regs */
64	void __iomem *ctrl;		/* 4 bytes */
65
66	void __iomem *xfer_type;	/* 4 bytes */
67	void __iomem *xfer_size;	/* 8 bytes */
68	void __iomem *dst_addr;		/* 8 bytes */
69	void __iomem *src_addr;		/* 8 bytes */
70
71	/* read-only */
72	void __iomem *act_type;		/* 4 bytes */
73	void __iomem *residue;		/* 8 bytes */
74	void __iomem *cur_dst_addr;	/* 8 bytes */
75	void __iomem *cur_src_addr;	/* 8 bytes */
76};
77
78struct sf_pdma_desc {
79	u32				xfer_type;
80	u64				xfer_size;
81	u64				dst_addr;
82	u64				src_addr;
83	struct virt_dma_desc		vdesc;
84	struct sf_pdma_chan		*chan;
85	bool				in_use;
86	enum dma_transfer_direction	dirn;
87	struct dma_async_tx_descriptor *async_tx;
88};
89
90enum sf_pdma_pm_state {
91	RUNNING = 0,
92	SUSPENDED,
93};
94
95struct sf_pdma_chan {
96	struct virt_dma_chan		vchan;
97	enum dma_status			status;
98	enum sf_pdma_pm_state		pm_state;
99	u32				slave_id;
100	struct sf_pdma			*pdma;
101	struct sf_pdma_desc		*desc;
102	struct dma_slave_config		cfg;
103	u32				attr;
104	dma_addr_t			dma_dev_addr;
105	u32				dma_dev_size;
106	struct tasklet_struct		done_tasklet;
107	struct tasklet_struct		err_tasklet;
108	struct pdma_regs		regs;
109	spinlock_t			lock; /* protect chan data */
110	bool				xfer_err;
111	int				txirq;
112	int				errirq;
113	int				retries;
114};
115
116struct sf_pdma {
117	struct dma_device       dma_dev;
118	void __iomem            *membase;
119	void __iomem            *mappedbase;
120	u32			n_chans;
121	struct sf_pdma_chan	chans[PDMA_NR_CH];
122};
123
124#endif /* _SF_PDMA_H */
125