1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2017 Marvell 4 * 5 * Antoine Tenart <antoine.tenart@free-electrons.com> 6 */ 7 8#ifndef __SAFEXCEL_H__ 9#define __SAFEXCEL_H__ 10 11#include <crypto/aead.h> 12#include <crypto/algapi.h> 13#include <crypto/internal/hash.h> 14#include <crypto/sha.h> 15#include <crypto/sha3.h> 16#include <crypto/skcipher.h> 17#include <linux/types.h> 18 19#define EIP197_HIA_VERSION_BE 0xca35 20#define EIP197_HIA_VERSION_LE 0x35ca 21#define EIP97_VERSION_LE 0x9e61 22#define EIP196_VERSION_LE 0x3bc4 23#define EIP197_VERSION_LE 0x3ac5 24#define EIP96_VERSION_LE 0x9f60 25#define EIP201_VERSION_LE 0x36c9 26#define EIP206_VERSION_LE 0x31ce 27#define EIP207_VERSION_LE 0x30cf 28#define EIP197_REG_LO16(reg) (reg & 0xffff) 29#define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff) 30#define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff) 31#define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \ 32 ((reg >> 4) & 0xf0) | \ 33 ((reg >> 12) & 0xf)) 34 35/* EIP197 HIA OPTIONS ENCODING */ 36#define EIP197_HIA_OPT_HAS_PE_ARB BIT(29) 37 38/* EIP206 OPTIONS ENCODING */ 39#define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) 40#define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) 41 42/* EIP197 OPTIONS ENCODING */ 43#define EIP197_OPT_HAS_TRC BIT(31) 44 45/* Static configuration */ 46#define EIP197_DEFAULT_RING_SIZE 400 47#define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */ 48#define EIP197_MAX_TOKENS 16 49#define EIP197_MAX_RINGS 4 50#define EIP197_FETCH_DEPTH 2 51#define EIP197_MAX_BATCH_SZ 64 52#define EIP197_MAX_RING_AIC 14 53 54#define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \ 55 GFP_KERNEL : GFP_ATOMIC) 56 57/* Custom on-stack requests (for invalidation) */ 58#define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \ 59 sizeof(struct safexcel_cipher_req) 60#define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \ 61 sizeof(struct safexcel_ahash_req) 62#define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \ 63 sizeof(struct safexcel_cipher_req) 64#define EIP197_REQUEST_ON_STACK(name, type, size) \ 65 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \ 66 struct type##_request *name = (void *)__##name##_desc 67 68/* Xilinx dev board base offsets */ 69#define EIP197_XLX_GPIO_BASE 0x200000 70#define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000 71#define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2 72#define EIP197_XLX_USER_INT_ENB_MSK 0x2004 73#define EIP197_XLX_USER_INT_ENB_SET 0x2008 74#define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c 75#define EIP197_XLX_USER_INT_BLOCK 0x2040 76#define EIP197_XLX_USER_INT_PEND 0x2048 77#define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080 78#define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100 79#define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084 80#define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504 81#define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088 82#define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908 83#define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c 84#define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c 85 86/* Helper defines for probe function */ 87#define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci) 88 89/* Register base offsets */ 90#define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic) 91#define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g) 92#define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r) 93#define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr) 94#define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe) 95#define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr) 96#define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse) 97#define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr) 98#define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg) 99#define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe) 100#define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global) 101 102/* EIP197 base offsets */ 103#define EIP197_HIA_AIC_BASE 0x90000 104#define EIP197_HIA_AIC_G_BASE 0x90000 105#define EIP197_HIA_AIC_R_BASE 0x90800 106#define EIP197_HIA_AIC_xDR_BASE 0x80000 107#define EIP197_HIA_DFE_BASE 0x8c000 108#define EIP197_HIA_DFE_THR_BASE 0x8c040 109#define EIP197_HIA_DSE_BASE 0x8d000 110#define EIP197_HIA_DSE_THR_BASE 0x8d040 111#define EIP197_HIA_GEN_CFG_BASE 0xf0000 112#define EIP197_PE_BASE 0xa0000 113#define EIP197_GLOBAL_BASE 0xf0000 114 115/* EIP97 base offsets */ 116#define EIP97_HIA_AIC_BASE 0x0 117#define EIP97_HIA_AIC_G_BASE 0x0 118#define EIP97_HIA_AIC_R_BASE 0x0 119#define EIP97_HIA_AIC_xDR_BASE 0x0 120#define EIP97_HIA_DFE_BASE 0xf000 121#define EIP97_HIA_DFE_THR_BASE 0xf200 122#define EIP97_HIA_DSE_BASE 0xf400 123#define EIP97_HIA_DSE_THR_BASE 0xf600 124#define EIP97_HIA_GEN_CFG_BASE 0x10000 125#define EIP97_PE_BASE 0x10000 126#define EIP97_GLOBAL_BASE 0x10000 127 128/* CDR/RDR register offsets */ 129#define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000) 130#define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r)) 131#define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800) 132#define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000 133#define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004 134#define EIP197_HIA_xDR_RING_SIZE 0x0018 135#define EIP197_HIA_xDR_DESC_SIZE 0x001c 136#define EIP197_HIA_xDR_CFG 0x0020 137#define EIP197_HIA_xDR_DMA_CFG 0x0024 138#define EIP197_HIA_xDR_THRESH 0x0028 139#define EIP197_HIA_xDR_PREP_COUNT 0x002c 140#define EIP197_HIA_xDR_PROC_COUNT 0x0030 141#define EIP197_HIA_xDR_PREP_PNTR 0x0034 142#define EIP197_HIA_xDR_PROC_PNTR 0x0038 143#define EIP197_HIA_xDR_STAT 0x003c 144 145/* register offsets */ 146#define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) 147#define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) 148#define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) 149#define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) 150#define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) 151#define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) 152#define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) 153#define EIP197_HIA_RA_PE_STAT 0x0014 154#define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000) 155#define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r)) 156#define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 157#define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r)) 158#define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r)) 159#define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r)) 160#define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808 161#define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810 162#define EIP197_HIA_AIC_G_ACK 0xf810 163#define EIP197_HIA_MST_CTRL 0xfff4 164#define EIP197_HIA_OPTIONS 0xfff8 165#define EIP197_HIA_VERSION 0xfffc 166#define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) 167#define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) 168#define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n))) 169#define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n))) 170#define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n))) 171#define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n))) 172#define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n))) 173#define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n))) 174#define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n))) 175#define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n))) 176#define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n))) 177#define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) 178#define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) 179#define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) 180#define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n))) 181#define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) 182#define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n))) 183#define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n))) 184#define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n))) 185#define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) 186#define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) 187#define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n))) 188#define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n))) 189#define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n))) 190#define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n))) 191#define EIP197_MST_CTRL 0xfff4 192#define EIP197_OPTIONS 0xfff8 193#define EIP197_VERSION 0xfffc 194 195/* EIP197-specific registers, no indirection */ 196#define EIP197_CLASSIFICATION_RAMS 0xe0000 197#define EIP197_TRC_CTRL 0xf0800 198#define EIP197_TRC_LASTRES 0xf0804 199#define EIP197_TRC_REGINDEX 0xf0808 200#define EIP197_TRC_PARAMS 0xf0820 201#define EIP197_TRC_FREECHAIN 0xf0824 202#define EIP197_TRC_PARAMS2 0xf0828 203#define EIP197_TRC_ECCCTRL 0xf0830 204#define EIP197_TRC_ECCSTAT 0xf0834 205#define EIP197_TRC_ECCADMINSTAT 0xf0838 206#define EIP197_TRC_ECCDATASTAT 0xf083c 207#define EIP197_TRC_ECCDATA 0xf0840 208#define EIP197_STRC_CONFIG 0xf43f0 209#define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n))) 210#define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n))) 211#define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n))) 212#define EIP197_FLUE_OFFSETS 0xf6808 213#define EIP197_FLUE_ARC4_OFFSET 0xf680c 214#define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n))) 215#define EIP197_CS_RAM_CTRL 0xf7ff0 216 217/* EIP197_HIA_xDR_DESC_SIZE */ 218#define EIP197_xDR_DESC_MODE_64BIT BIT(31) 219#define EIP197_CDR_DESC_MODE_ADCP BIT(30) 220 221/* EIP197_HIA_xDR_DMA_CFG */ 222#define EIP197_HIA_xDR_WR_RES_BUF BIT(22) 223#define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23) 224#define EIP197_HIA_xDR_WR_OWN_BUF BIT(24) 225#define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) 226#define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) 227 228/* EIP197_HIA_CDR_THRESH */ 229#define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n) 230#define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22) 231#define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23) 232#define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 233 234/* EIP197_HIA_RDR_THRESH */ 235#define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n) 236#define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23) 237#define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */ 238 239/* EIP197_HIA_xDR_PREP_COUNT */ 240#define EIP197_xDR_PREP_CLR_COUNT BIT(31) 241 242/* EIP197_HIA_xDR_PROC_COUNT */ 243#define EIP197_xDR_PROC_xD_PKT_OFFSET 24 244#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0) 245#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24) 246#define EIP197_xDR_PROC_CLR_COUNT BIT(31) 247 248/* EIP197_HIA_xDR_STAT */ 249#define EIP197_xDR_DMA_ERR BIT(0) 250#define EIP197_xDR_PREP_CMD_THRES BIT(1) 251#define EIP197_xDR_ERR BIT(2) 252#define EIP197_xDR_THRESH BIT(4) 253#define EIP197_xDR_TIMEOUT BIT(5) 254 255#define EIP197_HIA_RA_PE_CTRL_RESET BIT(31) 256#define EIP197_HIA_RA_PE_CTRL_EN BIT(30) 257 258/* EIP197_HIA_OPTIONS */ 259#define EIP197_N_RINGS_OFFSET 0 260#define EIP197_N_RINGS_MASK GENMASK(3, 0) 261#define EIP197_N_PES_OFFSET 4 262#define EIP197_N_PES_MASK GENMASK(4, 0) 263#define EIP97_N_PES_MASK GENMASK(2, 0) 264#define EIP197_HWDATAW_OFFSET 25 265#define EIP197_HWDATAW_MASK GENMASK(3, 0) 266#define EIP97_HWDATAW_MASK GENMASK(2, 0) 267#define EIP197_CFSIZE_OFFSET 9 268#define EIP197_CFSIZE_ADJUST 4 269#define EIP97_CFSIZE_OFFSET 8 270#define EIP197_CFSIZE_MASK GENMASK(2, 0) 271#define EIP97_CFSIZE_MASK GENMASK(3, 0) 272#define EIP197_RFSIZE_OFFSET 12 273#define EIP197_RFSIZE_ADJUST 4 274#define EIP97_RFSIZE_OFFSET 12 275#define EIP197_RFSIZE_MASK GENMASK(2, 0) 276#define EIP97_RFSIZE_MASK GENMASK(3, 0) 277 278/* EIP197_HIA_AIC_R_ENABLE_CTRL */ 279#define EIP197_CDR_IRQ(n) BIT((n) * 2) 280#define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1) 281 282/* EIP197_HIA_DFE/DSE_CFG */ 283#define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) 284#define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) 285#define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) 286#define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14) 287#define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) 288#define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) 289#define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) 290#define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29) 291#define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29) 292#define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30) 293 294/* EIP197_HIA_DFE/DSE_THR_CTRL */ 295#define EIP197_DxE_THR_CTRL_EN BIT(30) 296#define EIP197_DxE_THR_CTRL_RESET_PE BIT(31) 297 298/* EIP197_PE_ICE_PUE/FPP_CTRL */ 299#define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16) 300#define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0 301#define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3) 302 303/* EIP197_HIA_AIC_G_ENABLED_STAT */ 304#define EIP197_G_IRQ_DFE(n) BIT((n) << 1) 305#define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1) 306#define EIP197_G_IRQ_RING BIT(16) 307#define EIP197_G_IRQ_PE(n) BIT((n) + 20) 308 309/* EIP197_HIA_MST_CTRL */ 310#define RD_CACHE_3BITS 0x5 311#define WR_CACHE_3BITS 0x3 312#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0)) 313#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0)) 314#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) 315#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) 316#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) 317#define EIP197_MST_CTRL_BYTE_SWAP BIT(24) 318#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) 319#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) 320 321/* EIP197_PE_IN_DBUF/TBUF_THRES */ 322#define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) 323#define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) 324 325/* EIP197_PE_OUT_DBUF_THRES */ 326#define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) 327#define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) 328 329/* EIP197_PE_ICE_SCRATCH_CTRL */ 330#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2) 331#define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3) 332#define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24) 333#define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25) 334 335/* EIP197_PE_ICE_SCRATCH_RAM */ 336#define EIP197_NUM_OF_SCRATCH_BLOCKS 32 337 338/* EIP197_PE_ICE_PUE/FPP_CTRL */ 339#define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0) 340#define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14) 341#define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15) 342 343/* EIP197_PE_ICE_RAM_CTRL */ 344#define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0) 345#define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1) 346 347/* EIP197_PE_EIP96_TOKEN_CTRL */ 348#define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16) 349#define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17) 350#define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22) 351 352/* EIP197_PE_EIP96_FUNCTION_EN */ 353#define EIP197_FUNCTION_ALL 0xffffffff 354 355/* EIP197_PE_EIP96_CONTEXT_CTRL */ 356#define EIP197_CONTEXT_SIZE(n) (n) 357#define EIP197_ADDRESS_MODE BIT(8) 358#define EIP197_CONTROL_MODE BIT(9) 359 360/* EIP197_PE_EIP96_TOKEN_CTRL2 */ 361#define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3) 362 363/* EIP197_PE_DEBUG */ 364#define EIP197_DEBUG_OCE_BYPASS BIT(1) 365 366/* EIP197_STRC_CONFIG */ 367#define EIP197_STRC_CONFIG_INIT BIT(31) 368#define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8) 369#define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0) 370 371/* EIP197_FLUE_CONFIG */ 372#define EIP197_FLUE_CONFIG_MAGIC 0xc7000004 373 374/* Context Control */ 375struct safexcel_context_record { 376 __le32 control0; 377 __le32 control1; 378 379 __le32 data[40]; 380} __packed; 381 382/* control0 */ 383#define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0 384#define CONTEXT_CONTROL_TYPE_NULL_IN 0x1 385#define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2 386#define CONTEXT_CONTROL_TYPE_HASH_IN 0x3 387#define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4 388#define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5 389#define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6 390#define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7 391#define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe 392#define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf 393#define CONTEXT_CONTROL_RESTART_HASH BIT(4) 394#define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5) 395#define CONTEXT_CONTROL_SIZE(n) ((n) << 8) 396#define CONTEXT_CONTROL_KEY_EN BIT(16) 397#define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17) 398#define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17) 399#define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17) 400#define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17) 401#define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17) 402#define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17) 403#define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17) 404#define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21) 405#define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21) 406#define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21) 407#define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21) 408#define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23) 409#define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23) 410#define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23) 411#define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23) 412#define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23) 413#define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23) 414#define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23) 415#define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23) 416#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23) 417#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23) 418#define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23) 419#define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23) 420#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23) 421#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23) 422#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23) 423#define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23) 424#define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23) 425#define CONTEXT_CONTROL_INV_FR (0x5 << 24) 426#define CONTEXT_CONTROL_INV_TR (0x6 << 24) 427 428/* control1 */ 429#define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0) 430#define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0) 431#define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0) 432#define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0) 433#define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0) 434#define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0) 435#define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0) 436#define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17)) 437#define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0) 438#define CONTEXT_CONTROL_IV0 BIT(5) 439#define CONTEXT_CONTROL_IV1 BIT(6) 440#define CONTEXT_CONTROL_IV2 BIT(7) 441#define CONTEXT_CONTROL_IV3 BIT(8) 442#define CONTEXT_CONTROL_DIGEST_CNT BIT(9) 443#define CONTEXT_CONTROL_COUNTER_MODE BIT(10) 444#define CONTEXT_CONTROL_CRYPTO_STORE BIT(12) 445#define CONTEXT_CONTROL_HASH_STORE BIT(19) 446 447#define EIP197_XCM_MODE_GCM 1 448#define EIP197_XCM_MODE_CCM 2 449 450#define EIP197_AEAD_TYPE_IPSEC_ESP 2 451#define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3 452#define EIP197_AEAD_IPSEC_IV_SIZE 8 453#define EIP197_AEAD_IPSEC_NONCE_SIZE 4 454#define EIP197_AEAD_IPSEC_COUNTER_SIZE 4 455#define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3 456 457/* The hash counter given to the engine in the context has a granularity of 458 * 64 bits. 459 */ 460#define EIP197_COUNTER_BLOCK_SIZE 64 461 462/* EIP197_CS_RAM_CTRL */ 463#define EIP197_TRC_ENABLE_0 BIT(4) 464#define EIP197_TRC_ENABLE_1 BIT(5) 465#define EIP197_TRC_ENABLE_2 BIT(6) 466#define EIP197_TRC_ENABLE_MASK GENMASK(6, 4) 467#define EIP197_CS_BANKSEL_MASK GENMASK(14, 12) 468#define EIP197_CS_BANKSEL_OFS 12 469 470/* EIP197_TRC_PARAMS */ 471#define EIP197_TRC_PARAMS_SW_RESET BIT(0) 472#define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2) 473#define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4) 474#define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10) 475#define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18) 476 477/* EIP197_TRC_FREECHAIN */ 478#define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p) 479#define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16) 480 481/* EIP197_TRC_PARAMS2 */ 482#define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p) 483#define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18) 484 485/* Cache helpers */ 486#define EIP197_MIN_DSIZE 1024 487#define EIP197_MIN_ASIZE 8 488#define EIP197_CS_TRC_REC_WC 64 489#define EIP197_CS_RC_SIZE (4 * sizeof(u32)) 490#define EIP197_CS_RC_NEXT(x) (x) 491#define EIP197_CS_RC_PREV(x) ((x) << 10) 492#define EIP197_RC_NULL 0x3ff 493 494/* Result data */ 495struct result_data_desc { 496 u32 packet_length:17; 497 u32 error_code:15; 498 499 u8 bypass_length:4; 500 u8 e15:1; 501 u16 rsvd0; 502 u8 hash_bytes:1; 503 u8 hash_length:6; 504 u8 generic_bytes:1; 505 u8 checksum:1; 506 u8 next_header:1; 507 u8 length:1; 508 509 u16 application_id; 510 u16 rsvd1; 511 512 u32 rsvd2[5]; 513} __packed; 514 515 516/* Basic Result Descriptor format */ 517struct safexcel_result_desc { 518 u32 particle_size:17; 519 u8 rsvd0:3; 520 u8 descriptor_overflow:1; 521 u8 buffer_overflow:1; 522 u8 last_seg:1; 523 u8 first_seg:1; 524 u16 result_size:8; 525 526 u32 rsvd1; 527 528 u32 data_lo; 529 u32 data_hi; 530} __packed; 531 532/* 533 * The EIP(1)97 only needs to fetch the descriptor part of 534 * the result descriptor, not the result token part! 535 */ 536#define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\ 537 sizeof(u32)) 538#define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\ 539 sizeof(u32)) 540 541struct safexcel_token { 542 u32 packet_length:17; 543 u8 stat:2; 544 u16 instructions:9; 545 u8 opcode:4; 546} __packed; 547 548#define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16) 549 550#define EIP197_TOKEN_CTX_OFFSET(x) (x) 551#define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11) 552#define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12) 553 554#define EIP197_TOKEN_STAT_LAST_HASH BIT(0) 555#define EIP197_TOKEN_STAT_LAST_PACKET BIT(1) 556#define EIP197_TOKEN_OPCODE_DIRECTION 0x0 557#define EIP197_TOKEN_OPCODE_INSERT 0x2 558#define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT 559#define EIP197_TOKEN_OPCODE_RETRIEVE 0x4 560#define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa 561#define EIP197_TOKEN_OPCODE_VERIFY 0xd 562#define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe 563#define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0) 564 565static inline void eip197_noop_token(struct safexcel_token *token) 566{ 567 token->opcode = EIP197_TOKEN_OPCODE_NOOP; 568 token->packet_length = BIT(2); 569 token->stat = 0; 570 token->instructions = 0; 571} 572 573/* Instructions */ 574#define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c 575#define EIP197_TOKEN_INS_ORIGIN_IV0 0x14 576#define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b 577#define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5) 578#define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5) 579#define EIP197_TOKEN_INS_TYPE_HASH BIT(6) 580#define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7) 581#define EIP197_TOKEN_INS_LAST BIT(8) 582 583/* Processing Engine Control Data */ 584struct safexcel_control_data_desc { 585 u32 packet_length:17; 586 u16 options:13; 587 u8 type:2; 588 589 u16 application_id; 590 u16 rsvd; 591 592 u32 context_lo; 593 u32 context_hi; 594 595 u32 control0; 596 u32 control1; 597 598 u32 token[EIP197_EMB_TOKENS]; 599} __packed; 600 601#define EIP197_OPTION_MAGIC_VALUE BIT(0) 602#define EIP197_OPTION_64BIT_CTX BIT(1) 603#define EIP197_OPTION_RC_AUTO (0x2 << 3) 604#define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8) 605#define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10) 606#define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9) 607 608#define EIP197_TYPE_BCLA 0x0 609#define EIP197_TYPE_EXTENDED 0x3 610#define EIP197_CONTEXT_SMALL 0x2 611#define EIP197_CONTEXT_SIZE_MASK 0x3 612 613/* Basic Command Descriptor format */ 614struct safexcel_command_desc { 615 u32 particle_size:17; 616 u8 rsvd0:5; 617 u8 last_seg:1; 618 u8 first_seg:1; 619 u8 additional_cdata_size:8; 620 621 u32 rsvd1; 622 623 u32 data_lo; 624 u32 data_hi; 625 626 u32 atok_lo; 627 u32 atok_hi; 628 629 struct safexcel_control_data_desc control_data; 630} __packed; 631 632#define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\ 633 sizeof(u32)) 634 635/* 636 * Internal structures & functions 637 */ 638 639#define EIP197_FW_TERMINAL_NOPS 2 640#define EIP197_FW_START_POLLCNT 16 641#define EIP197_FW_PUE_READY 0x14 642#define EIP197_FW_FPP_READY 0x18 643 644enum eip197_fw { 645 FW_IFPP = 0, 646 FW_IPUE, 647 FW_NB 648}; 649 650struct safexcel_desc_ring { 651 void *base; 652 void *shbase; 653 void *base_end; 654 void *shbase_end; 655 dma_addr_t base_dma; 656 dma_addr_t shbase_dma; 657 658 /* write and read pointers */ 659 void *write; 660 void *shwrite; 661 void *read; 662 663 /* descriptor element offset */ 664 unsigned int offset; 665 unsigned int shoffset; 666}; 667 668enum safexcel_alg_type { 669 SAFEXCEL_ALG_TYPE_SKCIPHER, 670 SAFEXCEL_ALG_TYPE_AEAD, 671 SAFEXCEL_ALG_TYPE_AHASH, 672}; 673 674struct safexcel_config { 675 u32 pes; 676 u32 rings; 677 678 u32 cd_size; 679 u32 cd_offset; 680 u32 cdsh_offset; 681 682 u32 rd_size; 683 u32 rd_offset; 684 u32 res_offset; 685}; 686 687struct safexcel_work_data { 688 struct work_struct work; 689 struct safexcel_crypto_priv *priv; 690 int ring; 691}; 692 693struct safexcel_ring { 694 spinlock_t lock; 695 696 struct workqueue_struct *workqueue; 697 struct safexcel_work_data work_data; 698 699 /* command/result rings */ 700 struct safexcel_desc_ring cdr; 701 struct safexcel_desc_ring rdr; 702 703 /* result ring crypto API request */ 704 struct crypto_async_request **rdr_req; 705 706 /* queue */ 707 struct crypto_queue queue; 708 spinlock_t queue_lock; 709 710 /* Number of requests in the engine. */ 711 int requests; 712 713 /* The ring is currently handling at least one request */ 714 bool busy; 715 716 /* Store for current requests when bailing out of the dequeueing 717 * function when no enough resources are available. 718 */ 719 struct crypto_async_request *req; 720 struct crypto_async_request *backlog; 721 722 /* irq of this ring */ 723 int irq; 724}; 725 726/* EIP integration context flags */ 727enum safexcel_eip_version { 728 /* Platform (EIP integration context) specifier */ 729 EIP97IES_MRVL, 730 EIP197B_MRVL, 731 EIP197D_MRVL, 732 EIP197_DEVBRD 733}; 734 735/* Priority we use for advertising our algorithms */ 736#define SAFEXCEL_CRA_PRIORITY 300 737 738/* SM3 digest result for zero length message */ 739#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ 740 "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ 741 "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \ 742 "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B" 743 744/* EIP algorithm presence flags */ 745enum safexcel_eip_algorithms { 746 SAFEXCEL_ALG_BC0 = BIT(5), 747 SAFEXCEL_ALG_SM4 = BIT(6), 748 SAFEXCEL_ALG_SM3 = BIT(7), 749 SAFEXCEL_ALG_CHACHA20 = BIT(8), 750 SAFEXCEL_ALG_POLY1305 = BIT(9), 751 SAFEXCEL_SEQMASK_256 = BIT(10), 752 SAFEXCEL_SEQMASK_384 = BIT(11), 753 SAFEXCEL_ALG_AES = BIT(12), 754 SAFEXCEL_ALG_AES_XFB = BIT(13), 755 SAFEXCEL_ALG_DES = BIT(15), 756 SAFEXCEL_ALG_DES_XFB = BIT(16), 757 SAFEXCEL_ALG_ARC4 = BIT(18), 758 SAFEXCEL_ALG_AES_XTS = BIT(20), 759 SAFEXCEL_ALG_WIRELESS = BIT(21), 760 SAFEXCEL_ALG_MD5 = BIT(22), 761 SAFEXCEL_ALG_SHA1 = BIT(23), 762 SAFEXCEL_ALG_SHA2_256 = BIT(25), 763 SAFEXCEL_ALG_SHA2_512 = BIT(26), 764 SAFEXCEL_ALG_XCBC_MAC = BIT(27), 765 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29), 766 SAFEXCEL_ALG_GHASH = BIT(30), 767 SAFEXCEL_ALG_SHA3 = BIT(31), 768}; 769 770struct safexcel_register_offsets { 771 u32 hia_aic; 772 u32 hia_aic_g; 773 u32 hia_aic_r; 774 u32 hia_aic_xdr; 775 u32 hia_dfe; 776 u32 hia_dfe_thr; 777 u32 hia_dse; 778 u32 hia_dse_thr; 779 u32 hia_gen_cfg; 780 u32 pe; 781 u32 global; 782}; 783 784enum safexcel_flags { 785 EIP197_TRC_CACHE = BIT(0), 786 SAFEXCEL_HW_EIP197 = BIT(1), 787 EIP197_PE_ARB = BIT(2), 788 EIP197_ICE = BIT(3), 789 EIP197_SIMPLE_TRC = BIT(4), 790 EIP197_OCE = BIT(5), 791}; 792 793struct safexcel_hwconfig { 794 enum safexcel_eip_algorithms algo_flags; 795 int hwver; 796 int hiaver; 797 int ppver; 798 int icever; 799 int pever; 800 int ocever; 801 int psever; 802 int hwdataw; 803 int hwcfsize; 804 int hwrfsize; 805 int hwnumpes; 806 int hwnumrings; 807 int hwnumraic; 808}; 809 810struct safexcel_crypto_priv { 811 void __iomem *base; 812 struct device *dev; 813 struct clk *clk; 814 struct clk *reg_clk; 815 struct safexcel_config config; 816 817 enum safexcel_eip_version version; 818 struct safexcel_register_offsets offsets; 819 struct safexcel_hwconfig hwconfig; 820 u32 flags; 821 822 /* context DMA pool */ 823 struct dma_pool *context_pool; 824 825 atomic_t ring_used; 826 827 struct safexcel_ring *ring; 828}; 829 830struct safexcel_context { 831 int (*send)(struct crypto_async_request *req, int ring, 832 int *commands, int *results); 833 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring, 834 struct crypto_async_request *req, bool *complete, 835 int *ret); 836 struct safexcel_context_record *ctxr; 837 struct safexcel_crypto_priv *priv; 838 dma_addr_t ctxr_dma; 839 840 union { 841 __le32 le[SHA3_512_BLOCK_SIZE / 4]; 842 __be32 be[SHA3_512_BLOCK_SIZE / 4]; 843 u32 word[SHA3_512_BLOCK_SIZE / 4]; 844 u8 byte[SHA3_512_BLOCK_SIZE]; 845 } ipad, opad; 846 847 int ring; 848 bool needs_inv; 849 bool exit_inv; 850}; 851 852#define HASH_CACHE_SIZE SHA512_BLOCK_SIZE 853 854struct safexcel_ahash_export_state { 855 u64 len; 856 u64 processed; 857 858 u32 digest; 859 860 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)]; 861 u8 cache[HASH_CACHE_SIZE]; 862}; 863 864/* 865 * Template structure to describe the algorithms in order to register them. 866 * It also has the purpose to contain our private structure and is actually 867 * the only way I know in this framework to avoid having global pointers... 868 */ 869struct safexcel_alg_template { 870 struct safexcel_crypto_priv *priv; 871 enum safexcel_alg_type type; 872 enum safexcel_eip_algorithms algo_mask; 873 union { 874 struct skcipher_alg skcipher; 875 struct aead_alg aead; 876 struct ahash_alg ahash; 877 } alg; 878}; 879 880struct safexcel_inv_result { 881 struct completion completion; 882 int error; 883}; 884 885void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring); 886int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv, 887 void *rdp); 888void safexcel_complete(struct safexcel_crypto_priv *priv, int ring); 889int safexcel_invalidate_cache(struct crypto_async_request *async, 890 struct safexcel_crypto_priv *priv, 891 dma_addr_t ctxr_dma, int ring); 892int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv, 893 struct safexcel_desc_ring *cdr, 894 struct safexcel_desc_ring *rdr); 895int safexcel_select_ring(struct safexcel_crypto_priv *priv); 896void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv, 897 struct safexcel_desc_ring *ring); 898void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring); 899void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv, 900 struct safexcel_desc_ring *ring); 901struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv, 902 int ring_id, 903 bool first, bool last, 904 dma_addr_t data, u32 len, 905 u32 full_data_len, 906 dma_addr_t context, 907 struct safexcel_token **atoken); 908struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv, 909 int ring_id, 910 bool first, bool last, 911 dma_addr_t data, u32 len); 912int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv, 913 int ring); 914int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv, 915 int ring, 916 struct safexcel_result_desc *rdesc); 917void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv, 918 int ring, 919 struct safexcel_result_desc *rdesc, 920 struct crypto_async_request *req); 921inline struct crypto_async_request * 922safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring); 923void safexcel_inv_complete(struct crypto_async_request *req, int error); 924int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key, 925 unsigned int keylen, const char *alg, 926 unsigned int state_sz); 927 928/* available algorithms */ 929extern struct safexcel_alg_template safexcel_alg_ecb_des; 930extern struct safexcel_alg_template safexcel_alg_cbc_des; 931extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede; 932extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede; 933extern struct safexcel_alg_template safexcel_alg_ecb_aes; 934extern struct safexcel_alg_template safexcel_alg_cbc_aes; 935extern struct safexcel_alg_template safexcel_alg_cfb_aes; 936extern struct safexcel_alg_template safexcel_alg_ofb_aes; 937extern struct safexcel_alg_template safexcel_alg_ctr_aes; 938extern struct safexcel_alg_template safexcel_alg_md5; 939extern struct safexcel_alg_template safexcel_alg_sha1; 940extern struct safexcel_alg_template safexcel_alg_sha224; 941extern struct safexcel_alg_template safexcel_alg_sha256; 942extern struct safexcel_alg_template safexcel_alg_sha384; 943extern struct safexcel_alg_template safexcel_alg_sha512; 944extern struct safexcel_alg_template safexcel_alg_hmac_md5; 945extern struct safexcel_alg_template safexcel_alg_hmac_sha1; 946extern struct safexcel_alg_template safexcel_alg_hmac_sha224; 947extern struct safexcel_alg_template safexcel_alg_hmac_sha256; 948extern struct safexcel_alg_template safexcel_alg_hmac_sha384; 949extern struct safexcel_alg_template safexcel_alg_hmac_sha512; 950extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes; 951extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes; 952extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes; 953extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes; 954extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes; 955extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede; 956extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes; 957extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes; 958extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes; 959extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes; 960extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes; 961extern struct safexcel_alg_template safexcel_alg_xts_aes; 962extern struct safexcel_alg_template safexcel_alg_gcm; 963extern struct safexcel_alg_template safexcel_alg_ccm; 964extern struct safexcel_alg_template safexcel_alg_crc32; 965extern struct safexcel_alg_template safexcel_alg_cbcmac; 966extern struct safexcel_alg_template safexcel_alg_xcbcmac; 967extern struct safexcel_alg_template safexcel_alg_cmac; 968extern struct safexcel_alg_template safexcel_alg_chacha20; 969extern struct safexcel_alg_template safexcel_alg_chachapoly; 970extern struct safexcel_alg_template safexcel_alg_chachapoly_esp; 971extern struct safexcel_alg_template safexcel_alg_sm3; 972extern struct safexcel_alg_template safexcel_alg_hmac_sm3; 973extern struct safexcel_alg_template safexcel_alg_ecb_sm4; 974extern struct safexcel_alg_template safexcel_alg_cbc_sm4; 975extern struct safexcel_alg_template safexcel_alg_ofb_sm4; 976extern struct safexcel_alg_template safexcel_alg_cfb_sm4; 977extern struct safexcel_alg_template safexcel_alg_ctr_sm4; 978extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4; 979extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4; 980extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4; 981extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4; 982extern struct safexcel_alg_template safexcel_alg_sha3_224; 983extern struct safexcel_alg_template safexcel_alg_sha3_256; 984extern struct safexcel_alg_template safexcel_alg_sha3_384; 985extern struct safexcel_alg_template safexcel_alg_sha3_512; 986extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224; 987extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256; 988extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384; 989extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512; 990extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des; 991extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede; 992extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede; 993extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede; 994extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede; 995extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des; 996extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des; 997extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des; 998extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des; 999extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm; 1000extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm; 1001extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm; 1002 1003#endif 1004