18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 28c2ecf20Sopenharmony_ci/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ 38c2ecf20Sopenharmony_ci 48c2ecf20Sopenharmony_ci#ifndef __CC_SRAM_MGR_H__ 58c2ecf20Sopenharmony_ci#define __CC_SRAM_MGR_H__ 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci#ifndef CC_CC_SRAM_SIZE 88c2ecf20Sopenharmony_ci#define CC_CC_SRAM_SIZE 4096 98c2ecf20Sopenharmony_ci#endif 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_cistruct cc_drvdata; 128c2ecf20Sopenharmony_ci 138c2ecf20Sopenharmony_ci#define NULL_SRAM_ADDR ((u32)-1) 148c2ecf20Sopenharmony_ci 158c2ecf20Sopenharmony_ci/** 168c2ecf20Sopenharmony_ci * cc_sram_mgr_init() - Initializes SRAM pool. 178c2ecf20Sopenharmony_ci * The first X bytes of SRAM are reserved for ROM usage, hence, pool 188c2ecf20Sopenharmony_ci * starts right after X bytes. 198c2ecf20Sopenharmony_ci * 208c2ecf20Sopenharmony_ci * @drvdata: Associated device driver context 218c2ecf20Sopenharmony_ci * 228c2ecf20Sopenharmony_ci * Return: 238c2ecf20Sopenharmony_ci * Zero for success, negative value otherwise. 248c2ecf20Sopenharmony_ci */ 258c2ecf20Sopenharmony_ciint cc_sram_mgr_init(struct cc_drvdata *drvdata); 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/** 288c2ecf20Sopenharmony_ci * cc_sram_alloc() - Allocate buffer from SRAM pool. 298c2ecf20Sopenharmony_ci * 308c2ecf20Sopenharmony_ci * @drvdata: Associated device driver context 318c2ecf20Sopenharmony_ci * @size: The requested bytes to allocate 328c2ecf20Sopenharmony_ci * 338c2ecf20Sopenharmony_ci * Return: 348c2ecf20Sopenharmony_ci * Address offset in SRAM or NULL_SRAM_ADDR for failure. 358c2ecf20Sopenharmony_ci */ 368c2ecf20Sopenharmony_ciu32 cc_sram_alloc(struct cc_drvdata *drvdata, u32 size); 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_ci/** 398c2ecf20Sopenharmony_ci * cc_set_sram_desc() - Create const descriptors sequence to 408c2ecf20Sopenharmony_ci * set values in given array into SRAM. 418c2ecf20Sopenharmony_ci * Note: each const value can't exceed word size. 428c2ecf20Sopenharmony_ci * 438c2ecf20Sopenharmony_ci * @src: A pointer to array of words to set as consts. 448c2ecf20Sopenharmony_ci * @dst: The target SRAM buffer to set into 458c2ecf20Sopenharmony_ci * @nelement: The number of words in "src" array 468c2ecf20Sopenharmony_ci * @seq: A pointer to the given IN/OUT descriptor sequence 478c2ecf20Sopenharmony_ci * @seq_len: A pointer to the given IN/OUT sequence length 488c2ecf20Sopenharmony_ci */ 498c2ecf20Sopenharmony_civoid cc_set_sram_desc(const u32 *src, u32 dst, unsigned int nelement, 508c2ecf20Sopenharmony_ci struct cc_hw_desc *seq, unsigned int *seq_len); 518c2ecf20Sopenharmony_ci 528c2ecf20Sopenharmony_ci#endif /*__CC_SRAM_MGR_H__*/ 53