1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2016 Cavium, Inc. 4 */ 5 6#include <linux/device.h> 7#include <linux/firmware.h> 8#include <linux/interrupt.h> 9#include <linux/module.h> 10#include <linux/moduleparam.h> 11#include <linux/pci.h> 12#include <linux/printk.h> 13#include <linux/version.h> 14 15#include "cptpf.h" 16 17#define DRV_NAME "thunder-cpt" 18#define DRV_VERSION "1.0" 19 20static u32 num_vfs = 4; /* Default 4 VF enabled */ 21module_param(num_vfs, uint, 0444); 22MODULE_PARM_DESC(num_vfs, "Number of VFs to enable(1-16)"); 23 24/* 25 * Disable cores specified by coremask 26 */ 27static void cpt_disable_cores(struct cpt_device *cpt, u64 coremask, 28 u8 type, u8 grp) 29{ 30 u64 pf_exe_ctl; 31 u32 timeout = 100; 32 u64 grpmask = 0; 33 struct device *dev = &cpt->pdev->dev; 34 35 if (type == AE_TYPES) 36 coremask = (coremask << cpt->max_se_cores); 37 38 /* Disengage the cores from groups */ 39 grpmask = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); 40 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 41 (grpmask & ~coremask)); 42 udelay(CSR_DELAY); 43 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); 44 while (grp & coremask) { 45 dev_err(dev, "Cores still busy %llx", coremask); 46 grp = cpt_read_csr64(cpt->reg_base, 47 CPTX_PF_EXEC_BUSY(0)); 48 if (timeout--) 49 break; 50 51 udelay(CSR_DELAY); 52 } 53 54 /* Disable the cores */ 55 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); 56 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 57 (pf_exe_ctl & ~coremask)); 58 udelay(CSR_DELAY); 59} 60 61/* 62 * Enable cores specified by coremask 63 */ 64static void cpt_enable_cores(struct cpt_device *cpt, u64 coremask, 65 u8 type) 66{ 67 u64 pf_exe_ctl; 68 69 if (type == AE_TYPES) 70 coremask = (coremask << cpt->max_se_cores); 71 72 pf_exe_ctl = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0)); 73 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 74 (pf_exe_ctl | coremask)); 75 udelay(CSR_DELAY); 76} 77 78static void cpt_configure_group(struct cpt_device *cpt, u8 grp, 79 u64 coremask, u8 type) 80{ 81 u64 pf_gx_en = 0; 82 83 if (type == AE_TYPES) 84 coremask = (coremask << cpt->max_se_cores); 85 86 pf_gx_en = cpt_read_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp)); 87 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 88 (pf_gx_en | coremask)); 89 udelay(CSR_DELAY); 90} 91 92static void cpt_disable_mbox_interrupts(struct cpt_device *cpt) 93{ 94 /* Clear mbox(0) interupts for all vfs */ 95 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull); 96} 97 98static void cpt_disable_ecc_interrupts(struct cpt_device *cpt) 99{ 100 /* Clear ecc(0) interupts for all vfs */ 101 cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull); 102} 103 104static void cpt_disable_exec_interrupts(struct cpt_device *cpt) 105{ 106 /* Clear exec interupts for all vfs */ 107 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull); 108} 109 110static void cpt_disable_all_interrupts(struct cpt_device *cpt) 111{ 112 cpt_disable_mbox_interrupts(cpt); 113 cpt_disable_ecc_interrupts(cpt); 114 cpt_disable_exec_interrupts(cpt); 115} 116 117static void cpt_enable_mbox_interrupts(struct cpt_device *cpt) 118{ 119 /* Set mbox(0) interupts for all vfs */ 120 cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull); 121} 122 123static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode) 124{ 125 int ret = 0, core = 0, shift = 0; 126 u32 total_cores = 0; 127 struct device *dev = &cpt->pdev->dev; 128 129 if (!mcode || !mcode->code) { 130 dev_err(dev, "Either the mcode is null or data is NULL\n"); 131 return -EINVAL; 132 } 133 134 if (mcode->code_size == 0) { 135 dev_err(dev, "microcode size is 0\n"); 136 return -EINVAL; 137 } 138 139 /* Assumes 0-9 are SE cores for UCODE_BASE registers and 140 * AE core bases follow 141 */ 142 if (mcode->is_ae) { 143 core = CPT_MAX_SE_CORES; /* start couting from 10 */ 144 total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */ 145 } else { 146 core = 0; /* start couting from 0 */ 147 total_cores = CPT_MAX_SE_CORES; /* upto 9 */ 148 } 149 150 /* Point to microcode for each core of the group */ 151 for (; core < total_cores ; core++, shift++) { 152 if (mcode->core_mask & (1 << shift)) { 153 cpt_write_csr64(cpt->reg_base, 154 CPTX_PF_ENGX_UCODE_BASE(0, core), 155 (u64)mcode->phys_base); 156 } 157 } 158 return ret; 159} 160 161static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode) 162{ 163 int ret = 0; 164 struct device *dev = &cpt->pdev->dev; 165 166 /* Make device not ready */ 167 cpt->flags &= ~CPT_FLAG_DEVICE_READY; 168 /* Disable All PF interrupts */ 169 cpt_disable_all_interrupts(cpt); 170 /* Calculate mcode group and coremasks */ 171 if (mcode->is_ae) { 172 if (mcode->num_cores > cpt->max_ae_cores) { 173 dev_err(dev, "Requested for more cores than available AE cores\n"); 174 ret = -EINVAL; 175 goto cpt_init_fail; 176 } 177 178 if (cpt->next_group >= CPT_MAX_CORE_GROUPS) { 179 dev_err(dev, "Can't load, all eight microcode groups in use"); 180 return -ENFILE; 181 } 182 183 mcode->group = cpt->next_group; 184 /* Convert requested cores to mask */ 185 mcode->core_mask = GENMASK(mcode->num_cores, 0); 186 cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES, 187 mcode->group); 188 /* Load microcode for AE engines */ 189 ret = cpt_load_microcode(cpt, mcode); 190 if (ret) { 191 dev_err(dev, "Microcode load Failed for %s\n", 192 mcode->version); 193 goto cpt_init_fail; 194 } 195 cpt->next_group++; 196 /* Configure group mask for the mcode */ 197 cpt_configure_group(cpt, mcode->group, mcode->core_mask, 198 AE_TYPES); 199 /* Enable AE cores for the group mask */ 200 cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES); 201 } else { 202 if (mcode->num_cores > cpt->max_se_cores) { 203 dev_err(dev, "Requested for more cores than available SE cores\n"); 204 ret = -EINVAL; 205 goto cpt_init_fail; 206 } 207 if (cpt->next_group >= CPT_MAX_CORE_GROUPS) { 208 dev_err(dev, "Can't load, all eight microcode groups in use"); 209 return -ENFILE; 210 } 211 212 mcode->group = cpt->next_group; 213 /* Covert requested cores to mask */ 214 mcode->core_mask = GENMASK(mcode->num_cores, 0); 215 cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES, 216 mcode->group); 217 /* Load microcode for SE engines */ 218 ret = cpt_load_microcode(cpt, mcode); 219 if (ret) { 220 dev_err(dev, "Microcode load Failed for %s\n", 221 mcode->version); 222 goto cpt_init_fail; 223 } 224 cpt->next_group++; 225 /* Configure group mask for the mcode */ 226 cpt_configure_group(cpt, mcode->group, mcode->core_mask, 227 SE_TYPES); 228 /* Enable SE cores for the group mask */ 229 cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES); 230 } 231 232 /* Enabled PF mailbox interrupts */ 233 cpt_enable_mbox_interrupts(cpt); 234 cpt->flags |= CPT_FLAG_DEVICE_READY; 235 236 return ret; 237 238cpt_init_fail: 239 /* Enabled PF mailbox interrupts */ 240 cpt_enable_mbox_interrupts(cpt); 241 242 return ret; 243} 244 245struct ucode_header { 246 u8 version[CPT_UCODE_VERSION_SZ]; 247 u32 code_length; 248 u32 data_length; 249 u64 sram_address; 250}; 251 252static int cpt_ucode_load_fw(struct cpt_device *cpt, const u8 *fw, bool is_ae) 253{ 254 const struct firmware *fw_entry; 255 struct device *dev = &cpt->pdev->dev; 256 struct ucode_header *ucode; 257 unsigned int code_length; 258 struct microcode *mcode; 259 int j, ret = 0; 260 261 ret = request_firmware(&fw_entry, fw, dev); 262 if (ret) 263 return ret; 264 265 ucode = (struct ucode_header *)fw_entry->data; 266 mcode = &cpt->mcode[cpt->next_mc_idx]; 267 memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ); 268 code_length = ntohl(ucode->code_length); 269 if (code_length == 0 || code_length >= INT_MAX / 2) { 270 ret = -EINVAL; 271 goto fw_release; 272 } 273 mcode->code_size = code_length * 2; 274 275 mcode->is_ae = is_ae; 276 mcode->core_mask = 0ULL; 277 mcode->num_cores = is_ae ? 6 : 10; 278 279 /* Allocate DMAable space */ 280 mcode->code = dma_alloc_coherent(&cpt->pdev->dev, mcode->code_size, 281 &mcode->phys_base, GFP_KERNEL); 282 if (!mcode->code) { 283 dev_err(dev, "Unable to allocate space for microcode"); 284 ret = -ENOMEM; 285 goto fw_release; 286 } 287 288 memcpy((void *)mcode->code, (void *)(fw_entry->data + sizeof(*ucode)), 289 mcode->code_size); 290 291 /* Byte swap 64-bit */ 292 for (j = 0; j < (mcode->code_size / 8); j++) 293 ((u64 *)mcode->code)[j] = cpu_to_be64(((u64 *)mcode->code)[j]); 294 /* MC needs 16-bit swap */ 295 for (j = 0; j < (mcode->code_size / 2); j++) 296 ((u16 *)mcode->code)[j] = cpu_to_be16(((u16 *)mcode->code)[j]); 297 298 dev_dbg(dev, "mcode->code_size = %u\n", mcode->code_size); 299 dev_dbg(dev, "mcode->is_ae = %u\n", mcode->is_ae); 300 dev_dbg(dev, "mcode->num_cores = %u\n", mcode->num_cores); 301 dev_dbg(dev, "mcode->code = %llx\n", (u64)mcode->code); 302 dev_dbg(dev, "mcode->phys_base = %llx\n", mcode->phys_base); 303 304 ret = do_cpt_init(cpt, mcode); 305 if (ret) { 306 dev_err(dev, "do_cpt_init failed with ret: %d\n", ret); 307 goto fw_release; 308 } 309 310 dev_info(dev, "Microcode Loaded %s\n", mcode->version); 311 mcode->is_mc_valid = 1; 312 cpt->next_mc_idx++; 313 314fw_release: 315 release_firmware(fw_entry); 316 317 return ret; 318} 319 320static int cpt_ucode_load(struct cpt_device *cpt) 321{ 322 int ret = 0; 323 struct device *dev = &cpt->pdev->dev; 324 325 ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-ae.out", true); 326 if (ret) { 327 dev_err(dev, "ae:cpt_ucode_load failed with ret: %d\n", ret); 328 return ret; 329 } 330 ret = cpt_ucode_load_fw(cpt, "cpt8x-mc-se.out", false); 331 if (ret) { 332 dev_err(dev, "se:cpt_ucode_load failed with ret: %d\n", ret); 333 return ret; 334 } 335 336 return ret; 337} 338 339static irqreturn_t cpt_mbx0_intr_handler(int irq, void *cpt_irq) 340{ 341 struct cpt_device *cpt = (struct cpt_device *)cpt_irq; 342 343 cpt_mbox_intr_handler(cpt, 0); 344 345 return IRQ_HANDLED; 346} 347 348static void cpt_reset(struct cpt_device *cpt) 349{ 350 cpt_write_csr64(cpt->reg_base, CPTX_PF_RESET(0), 1); 351} 352 353static void cpt_find_max_enabled_cores(struct cpt_device *cpt) 354{ 355 union cptx_pf_constants pf_cnsts = {0}; 356 357 pf_cnsts.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_CONSTANTS(0)); 358 cpt->max_se_cores = pf_cnsts.s.se; 359 cpt->max_ae_cores = pf_cnsts.s.ae; 360} 361 362static u32 cpt_check_bist_status(struct cpt_device *cpt) 363{ 364 union cptx_pf_bist_status bist_sts = {0}; 365 366 bist_sts.u = cpt_read_csr64(cpt->reg_base, 367 CPTX_PF_BIST_STATUS(0)); 368 369 return bist_sts.u; 370} 371 372static u64 cpt_check_exe_bist_status(struct cpt_device *cpt) 373{ 374 union cptx_pf_exe_bist_status bist_sts = {0}; 375 376 bist_sts.u = cpt_read_csr64(cpt->reg_base, 377 CPTX_PF_EXE_BIST_STATUS(0)); 378 379 return bist_sts.u; 380} 381 382static void cpt_disable_all_cores(struct cpt_device *cpt) 383{ 384 u32 grp, timeout = 100; 385 struct device *dev = &cpt->pdev->dev; 386 387 /* Disengage the cores from groups */ 388 for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) { 389 cpt_write_csr64(cpt->reg_base, CPTX_PF_GX_EN(0, grp), 0); 390 udelay(CSR_DELAY); 391 } 392 393 grp = cpt_read_csr64(cpt->reg_base, CPTX_PF_EXEC_BUSY(0)); 394 while (grp) { 395 dev_err(dev, "Cores still busy"); 396 grp = cpt_read_csr64(cpt->reg_base, 397 CPTX_PF_EXEC_BUSY(0)); 398 if (timeout--) 399 break; 400 401 udelay(CSR_DELAY); 402 } 403 /* Disable the cores */ 404 cpt_write_csr64(cpt->reg_base, CPTX_PF_EXE_CTL(0), 0); 405} 406 407/** 408 * Ensure all cores are disengaged from all groups by 409 * calling cpt_disable_all_cores() before calling this 410 * function. 411 */ 412static void cpt_unload_microcode(struct cpt_device *cpt) 413{ 414 u32 grp = 0, core; 415 416 /* Free microcode bases and reset group masks */ 417 for (grp = 0; grp < CPT_MAX_CORE_GROUPS; grp++) { 418 struct microcode *mcode = &cpt->mcode[grp]; 419 420 if (cpt->mcode[grp].code) 421 dma_free_coherent(&cpt->pdev->dev, mcode->code_size, 422 mcode->code, mcode->phys_base); 423 mcode->code = NULL; 424 } 425 /* Clear UCODE_BASE registers for all engines */ 426 for (core = 0; core < CPT_MAX_TOTAL_CORES; core++) 427 cpt_write_csr64(cpt->reg_base, 428 CPTX_PF_ENGX_UCODE_BASE(0, core), 0ull); 429} 430 431static int cpt_device_init(struct cpt_device *cpt) 432{ 433 u64 bist; 434 struct device *dev = &cpt->pdev->dev; 435 436 /* Reset the PF when probed first */ 437 cpt_reset(cpt); 438 msleep(100); 439 440 /*Check BIST status*/ 441 bist = (u64)cpt_check_bist_status(cpt); 442 if (bist) { 443 dev_err(dev, "RAM BIST failed with code 0x%llx", bist); 444 return -ENODEV; 445 } 446 447 bist = cpt_check_exe_bist_status(cpt); 448 if (bist) { 449 dev_err(dev, "Engine BIST failed with code 0x%llx", bist); 450 return -ENODEV; 451 } 452 453 /*Get CLK frequency*/ 454 /*Get max enabled cores */ 455 cpt_find_max_enabled_cores(cpt); 456 /*Disable all cores*/ 457 cpt_disable_all_cores(cpt); 458 /*Reset device parameters*/ 459 cpt->next_mc_idx = 0; 460 cpt->next_group = 0; 461 /* PF is ready */ 462 cpt->flags |= CPT_FLAG_DEVICE_READY; 463 464 return 0; 465} 466 467static int cpt_register_interrupts(struct cpt_device *cpt) 468{ 469 int ret; 470 struct device *dev = &cpt->pdev->dev; 471 472 /* Enable MSI-X */ 473 ret = pci_alloc_irq_vectors(cpt->pdev, CPT_PF_MSIX_VECTORS, 474 CPT_PF_MSIX_VECTORS, PCI_IRQ_MSIX); 475 if (ret < 0) { 476 dev_err(&cpt->pdev->dev, "Request for #%d msix vectors failed\n", 477 CPT_PF_MSIX_VECTORS); 478 return ret; 479 } 480 481 /* Register mailbox interrupt handlers */ 482 ret = request_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), 483 cpt_mbx0_intr_handler, 0, "CPT Mbox0", cpt); 484 if (ret) 485 goto fail; 486 487 /* Enable mailbox interrupt */ 488 cpt_enable_mbox_interrupts(cpt); 489 return 0; 490 491fail: 492 dev_err(dev, "Request irq failed\n"); 493 pci_disable_msix(cpt->pdev); 494 return ret; 495} 496 497static void cpt_unregister_interrupts(struct cpt_device *cpt) 498{ 499 free_irq(pci_irq_vector(cpt->pdev, CPT_PF_INT_VEC_E_MBOXX(0)), cpt); 500 pci_disable_msix(cpt->pdev); 501} 502 503static int cpt_sriov_init(struct cpt_device *cpt, int num_vfs) 504{ 505 int pos = 0; 506 int err; 507 u16 total_vf_cnt; 508 struct pci_dev *pdev = cpt->pdev; 509 510 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); 511 if (!pos) { 512 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n"); 513 return -ENODEV; 514 } 515 516 cpt->num_vf_en = num_vfs; /* User requested VFs */ 517 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt); 518 if (total_vf_cnt < cpt->num_vf_en) 519 cpt->num_vf_en = total_vf_cnt; 520 521 if (!total_vf_cnt) 522 return 0; 523 524 /*Enabled the available VFs */ 525 err = pci_enable_sriov(pdev, cpt->num_vf_en); 526 if (err) { 527 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n", 528 cpt->num_vf_en); 529 cpt->num_vf_en = 0; 530 return err; 531 } 532 533 /* TODO: Optionally enable static VQ priorities feature */ 534 535 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n", 536 cpt->num_vf_en); 537 538 cpt->flags |= CPT_FLAG_SRIOV_ENABLED; 539 540 return 0; 541} 542 543static int cpt_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 544{ 545 struct device *dev = &pdev->dev; 546 struct cpt_device *cpt; 547 int err; 548 549 if (num_vfs > 16 || num_vfs < 4) { 550 dev_warn(dev, "Invalid vf count %d, Resetting it to 4(default)\n", 551 num_vfs); 552 num_vfs = 4; 553 } 554 555 cpt = devm_kzalloc(dev, sizeof(*cpt), GFP_KERNEL); 556 if (!cpt) 557 return -ENOMEM; 558 559 pci_set_drvdata(pdev, cpt); 560 cpt->pdev = pdev; 561 err = pci_enable_device(pdev); 562 if (err) { 563 dev_err(dev, "Failed to enable PCI device\n"); 564 pci_set_drvdata(pdev, NULL); 565 return err; 566 } 567 568 err = pci_request_regions(pdev, DRV_NAME); 569 if (err) { 570 dev_err(dev, "PCI request regions failed 0x%x\n", err); 571 goto cpt_err_disable_device; 572 } 573 574 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48)); 575 if (err) { 576 dev_err(dev, "Unable to get usable DMA configuration\n"); 577 goto cpt_err_release_regions; 578 } 579 580 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48)); 581 if (err) { 582 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n"); 583 goto cpt_err_release_regions; 584 } 585 586 /* MAP PF's configuration registers */ 587 cpt->reg_base = pcim_iomap(pdev, 0, 0); 588 if (!cpt->reg_base) { 589 dev_err(dev, "Cannot map config register space, aborting\n"); 590 err = -ENOMEM; 591 goto cpt_err_release_regions; 592 } 593 594 /* CPT device HW initialization */ 595 cpt_device_init(cpt); 596 597 /* Register interrupts */ 598 err = cpt_register_interrupts(cpt); 599 if (err) 600 goto cpt_err_release_regions; 601 602 err = cpt_ucode_load(cpt); 603 if (err) 604 goto cpt_err_unregister_interrupts; 605 606 /* Configure SRIOV */ 607 err = cpt_sriov_init(cpt, num_vfs); 608 if (err) 609 goto cpt_err_unregister_interrupts; 610 611 return 0; 612 613cpt_err_unregister_interrupts: 614 cpt_unregister_interrupts(cpt); 615cpt_err_release_regions: 616 pci_release_regions(pdev); 617cpt_err_disable_device: 618 pci_disable_device(pdev); 619 pci_set_drvdata(pdev, NULL); 620 return err; 621} 622 623static void cpt_remove(struct pci_dev *pdev) 624{ 625 struct cpt_device *cpt = pci_get_drvdata(pdev); 626 627 /* Disengage SE and AE cores from all groups*/ 628 cpt_disable_all_cores(cpt); 629 /* Unload microcodes */ 630 cpt_unload_microcode(cpt); 631 cpt_unregister_interrupts(cpt); 632 pci_disable_sriov(pdev); 633 pci_release_regions(pdev); 634 pci_disable_device(pdev); 635 pci_set_drvdata(pdev, NULL); 636} 637 638static void cpt_shutdown(struct pci_dev *pdev) 639{ 640 struct cpt_device *cpt = pci_get_drvdata(pdev); 641 642 if (!cpt) 643 return; 644 645 dev_info(&pdev->dev, "Shutdown device %x:%x.\n", 646 (u32)pdev->vendor, (u32)pdev->device); 647 648 cpt_unregister_interrupts(cpt); 649 pci_release_regions(pdev); 650 pci_disable_device(pdev); 651 pci_set_drvdata(pdev, NULL); 652} 653 654/* Supported devices */ 655static const struct pci_device_id cpt_id_table[] = { 656 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_PF_DEVICE_ID) }, 657 { 0, } /* end of table */ 658}; 659 660static struct pci_driver cpt_pci_driver = { 661 .name = DRV_NAME, 662 .id_table = cpt_id_table, 663 .probe = cpt_probe, 664 .remove = cpt_remove, 665 .shutdown = cpt_shutdown, 666}; 667 668module_pci_driver(cpt_pci_driver); 669 670MODULE_AUTHOR("George Cherian <george.cherian@cavium.com>"); 671MODULE_DESCRIPTION("Cavium Thunder CPT Physical Function Driver"); 672MODULE_LICENSE("GPL v2"); 673MODULE_VERSION(DRV_VERSION); 674MODULE_DEVICE_TABLE(pci, cpt_id_table); 675