1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org> 4 * Copyright (C) 2004 John Steele Scott <toojays@toojays.net> 5 * 6 * TODO: Need a big cleanup here. Basically, we need to have different 7 * cpufreq_driver structures for the different type of HW instead of the 8 * current mess. We also need to better deal with the detection of the 9 * type of machine. 10 */ 11 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14#include <linux/module.h> 15#include <linux/types.h> 16#include <linux/errno.h> 17#include <linux/kernel.h> 18#include <linux/delay.h> 19#include <linux/sched.h> 20#include <linux/adb.h> 21#include <linux/pmu.h> 22#include <linux/cpufreq.h> 23#include <linux/init.h> 24#include <linux/device.h> 25#include <linux/hardirq.h> 26#include <linux/of_device.h> 27#include <asm/prom.h> 28#include <asm/machdep.h> 29#include <asm/irq.h> 30#include <asm/pmac_feature.h> 31#include <asm/mmu_context.h> 32#include <asm/sections.h> 33#include <asm/cputable.h> 34#include <asm/time.h> 35#include <asm/mpic.h> 36#include <asm/keylargo.h> 37#include <asm/switch_to.h> 38 39/* WARNING !!! This will cause calibrate_delay() to be called, 40 * but this is an __init function ! So you MUST go edit 41 * init/main.c to make it non-init before enabling DEBUG_FREQ 42 */ 43#undef DEBUG_FREQ 44 45extern void low_choose_7447a_dfs(int dfs); 46extern void low_choose_750fx_pll(int pll); 47extern void low_sleep_handler(void); 48 49/* 50 * Currently, PowerMac cpufreq supports only high & low frequencies 51 * that are set by the firmware 52 */ 53static unsigned int low_freq; 54static unsigned int hi_freq; 55static unsigned int cur_freq; 56static unsigned int sleep_freq; 57static unsigned long transition_latency; 58 59/* 60 * Different models uses different mechanisms to switch the frequency 61 */ 62static int (*set_speed_proc)(int low_speed); 63static unsigned int (*get_speed_proc)(void); 64 65/* 66 * Some definitions used by the various speedprocs 67 */ 68static u32 voltage_gpio; 69static u32 frequency_gpio; 70static u32 slew_done_gpio; 71static int no_schedule; 72static int has_cpu_l2lve; 73static int is_pmu_based; 74 75/* There are only two frequency states for each processor. Values 76 * are in kHz for the time being. 77 */ 78#define CPUFREQ_HIGH 0 79#define CPUFREQ_LOW 1 80 81static struct cpufreq_frequency_table pmac_cpu_freqs[] = { 82 {0, CPUFREQ_HIGH, 0}, 83 {0, CPUFREQ_LOW, 0}, 84 {0, 0, CPUFREQ_TABLE_END}, 85}; 86 87static inline void local_delay(unsigned long ms) 88{ 89 if (no_schedule) 90 mdelay(ms); 91 else 92 msleep(ms); 93} 94 95#ifdef DEBUG_FREQ 96static inline void debug_calc_bogomips(void) 97{ 98 /* This will cause a recalc of bogomips and display the 99 * result. We backup/restore the value to avoid affecting the 100 * core cpufreq framework's own calculation. 101 */ 102 unsigned long save_lpj = loops_per_jiffy; 103 calibrate_delay(); 104 loops_per_jiffy = save_lpj; 105} 106#endif /* DEBUG_FREQ */ 107 108/* Switch CPU speed under 750FX CPU control 109 */ 110static int cpu_750fx_cpu_speed(int low_speed) 111{ 112 u32 hid2; 113 114 if (low_speed == 0) { 115 /* ramping up, set voltage first */ 116 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); 117 /* Make sure we sleep for at least 1ms */ 118 local_delay(10); 119 120 /* tweak L2 for high voltage */ 121 if (has_cpu_l2lve) { 122 hid2 = mfspr(SPRN_HID2); 123 hid2 &= ~0x2000; 124 mtspr(SPRN_HID2, hid2); 125 } 126 } 127#ifdef CONFIG_PPC_BOOK3S_32 128 low_choose_750fx_pll(low_speed); 129#endif 130 if (low_speed == 1) { 131 /* tweak L2 for low voltage */ 132 if (has_cpu_l2lve) { 133 hid2 = mfspr(SPRN_HID2); 134 hid2 |= 0x2000; 135 mtspr(SPRN_HID2, hid2); 136 } 137 138 /* ramping down, set voltage last */ 139 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); 140 local_delay(10); 141 } 142 143 return 0; 144} 145 146static unsigned int cpu_750fx_get_cpu_speed(void) 147{ 148 if (mfspr(SPRN_HID1) & HID1_PS) 149 return low_freq; 150 else 151 return hi_freq; 152} 153 154/* Switch CPU speed using DFS */ 155static int dfs_set_cpu_speed(int low_speed) 156{ 157 if (low_speed == 0) { 158 /* ramping up, set voltage first */ 159 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); 160 /* Make sure we sleep for at least 1ms */ 161 local_delay(1); 162 } 163 164 /* set frequency */ 165#ifdef CONFIG_PPC_BOOK3S_32 166 low_choose_7447a_dfs(low_speed); 167#endif 168 udelay(100); 169 170 if (low_speed == 1) { 171 /* ramping down, set voltage last */ 172 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); 173 local_delay(1); 174 } 175 176 return 0; 177} 178 179static unsigned int dfs_get_cpu_speed(void) 180{ 181 if (mfspr(SPRN_HID1) & HID1_DFS) 182 return low_freq; 183 else 184 return hi_freq; 185} 186 187 188/* Switch CPU speed using slewing GPIOs 189 */ 190static int gpios_set_cpu_speed(int low_speed) 191{ 192 int gpio, timeout = 0; 193 194 /* If ramping up, set voltage first */ 195 if (low_speed == 0) { 196 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); 197 /* Delay is way too big but it's ok, we schedule */ 198 local_delay(10); 199 } 200 201 /* Set frequency */ 202 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0); 203 if (low_speed == ((gpio & 0x01) == 0)) 204 goto skip; 205 206 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio, 207 low_speed ? 0x04 : 0x05); 208 udelay(200); 209 do { 210 if (++timeout > 100) 211 break; 212 local_delay(1); 213 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0); 214 } while((gpio & 0x02) == 0); 215 skip: 216 /* If ramping down, set voltage last */ 217 if (low_speed == 1) { 218 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); 219 /* Delay is way too big but it's ok, we schedule */ 220 local_delay(10); 221 } 222 223#ifdef DEBUG_FREQ 224 debug_calc_bogomips(); 225#endif 226 227 return 0; 228} 229 230/* Switch CPU speed under PMU control 231 */ 232static int pmu_set_cpu_speed(int low_speed) 233{ 234 struct adb_request req; 235 unsigned long save_l2cr; 236 unsigned long save_l3cr; 237 unsigned int pic_prio; 238 unsigned long flags; 239 240 preempt_disable(); 241 242#ifdef DEBUG_FREQ 243 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1)); 244#endif 245 pmu_suspend(); 246 247 /* Disable all interrupt sources on openpic */ 248 pic_prio = mpic_cpu_get_priority(); 249 mpic_cpu_set_priority(0xf); 250 251 /* Make sure the decrementer won't interrupt us */ 252 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 253 /* Make sure any pending DEC interrupt occurring while we did 254 * the above didn't re-enable the DEC */ 255 mb(); 256 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 257 258 /* We can now disable MSR_EE */ 259 local_irq_save(flags); 260 261 /* Giveup the FPU & vec */ 262 enable_kernel_fp(); 263 264#ifdef CONFIG_ALTIVEC 265 if (cpu_has_feature(CPU_FTR_ALTIVEC)) 266 enable_kernel_altivec(); 267#endif /* CONFIG_ALTIVEC */ 268 269 /* Save & disable L2 and L3 caches */ 270 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ 271 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ 272 273 /* Send the new speed command. My assumption is that this command 274 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep 275 */ 276 pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed); 277 while (!req.complete) 278 pmu_poll(); 279 280 /* Prepare the northbridge for the speed transition */ 281 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1); 282 283 /* Call low level code to backup CPU state and recover from 284 * hardware reset 285 */ 286 low_sleep_handler(); 287 288 /* Restore the northbridge */ 289 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0); 290 291 /* Restore L2 cache */ 292 if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0) 293 _set_L2CR(save_l2cr); 294 /* Restore L3 cache */ 295 if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0) 296 _set_L3CR(save_l3cr); 297 298 /* Restore userland MMU context */ 299 switch_mmu_context(NULL, current->active_mm, NULL); 300 301#ifdef DEBUG_FREQ 302 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1)); 303#endif 304 305 /* Restore low level PMU operations */ 306 pmu_unlock(); 307 308 /* 309 * Restore decrementer; we'll take a decrementer interrupt 310 * as soon as interrupts are re-enabled and the generic 311 * clockevents code will reprogram it with the right value. 312 */ 313 set_dec(1); 314 315 /* Restore interrupts */ 316 mpic_cpu_set_priority(pic_prio); 317 318 /* Let interrupts flow again ... */ 319 local_irq_restore(flags); 320 321#ifdef DEBUG_FREQ 322 debug_calc_bogomips(); 323#endif 324 325 pmu_resume(); 326 327 preempt_enable(); 328 329 return 0; 330} 331 332static int do_set_cpu_speed(struct cpufreq_policy *policy, int speed_mode) 333{ 334 unsigned long l3cr; 335 static unsigned long prev_l3cr; 336 337 if (speed_mode == CPUFREQ_LOW && 338 cpu_has_feature(CPU_FTR_L3CR)) { 339 l3cr = _get_L3CR(); 340 if (l3cr & L3CR_L3E) { 341 prev_l3cr = l3cr; 342 _set_L3CR(0); 343 } 344 } 345 set_speed_proc(speed_mode == CPUFREQ_LOW); 346 if (speed_mode == CPUFREQ_HIGH && 347 cpu_has_feature(CPU_FTR_L3CR)) { 348 l3cr = _get_L3CR(); 349 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr) 350 _set_L3CR(prev_l3cr); 351 } 352 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq; 353 354 return 0; 355} 356 357static unsigned int pmac_cpufreq_get_speed(unsigned int cpu) 358{ 359 return cur_freq; 360} 361 362static int pmac_cpufreq_target( struct cpufreq_policy *policy, 363 unsigned int index) 364{ 365 int rc; 366 367 rc = do_set_cpu_speed(policy, index); 368 369 ppc_proc_freq = cur_freq * 1000ul; 370 return rc; 371} 372 373static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy) 374{ 375 cpufreq_generic_init(policy, pmac_cpu_freqs, transition_latency); 376 return 0; 377} 378 379static u32 read_gpio(struct device_node *np) 380{ 381 const u32 *reg = of_get_property(np, "reg", NULL); 382 u32 offset; 383 384 if (reg == NULL) 385 return 0; 386 /* That works for all keylargos but shall be fixed properly 387 * some day... The problem is that it seems we can't rely 388 * on the "reg" property of the GPIO nodes, they are either 389 * relative to the base of KeyLargo or to the base of the 390 * GPIO space, and the device-tree doesn't help. 391 */ 392 offset = *reg; 393 if (offset < KEYLARGO_GPIO_LEVELS0) 394 offset += KEYLARGO_GPIO_LEVELS0; 395 return offset; 396} 397 398static int pmac_cpufreq_suspend(struct cpufreq_policy *policy) 399{ 400 /* Ok, this could be made a bit smarter, but let's be robust for now. We 401 * always force a speed change to high speed before sleep, to make sure 402 * we have appropriate voltage and/or bus speed for the wakeup process, 403 * and to make sure our loops_per_jiffies are "good enough", that is will 404 * not cause too short delays if we sleep in low speed and wake in high 405 * speed.. 406 */ 407 no_schedule = 1; 408 sleep_freq = cur_freq; 409 if (cur_freq == low_freq && !is_pmu_based) 410 do_set_cpu_speed(policy, CPUFREQ_HIGH); 411 return 0; 412} 413 414static int pmac_cpufreq_resume(struct cpufreq_policy *policy) 415{ 416 /* If we resume, first check if we have a get() function */ 417 if (get_speed_proc) 418 cur_freq = get_speed_proc(); 419 else 420 cur_freq = 0; 421 422 /* We don't, hrm... we don't really know our speed here, best 423 * is that we force a switch to whatever it was, which is 424 * probably high speed due to our suspend() routine 425 */ 426 do_set_cpu_speed(policy, sleep_freq == low_freq ? 427 CPUFREQ_LOW : CPUFREQ_HIGH); 428 429 ppc_proc_freq = cur_freq * 1000ul; 430 431 no_schedule = 0; 432 return 0; 433} 434 435static struct cpufreq_driver pmac_cpufreq_driver = { 436 .verify = cpufreq_generic_frequency_table_verify, 437 .target_index = pmac_cpufreq_target, 438 .get = pmac_cpufreq_get_speed, 439 .init = pmac_cpufreq_cpu_init, 440 .suspend = pmac_cpufreq_suspend, 441 .resume = pmac_cpufreq_resume, 442 .flags = CPUFREQ_PM_NO_WARN | 443 CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING, 444 .attr = cpufreq_generic_attr, 445 .name = "powermac", 446}; 447 448 449static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode) 450{ 451 struct device_node *volt_gpio_np = of_find_node_by_name(NULL, 452 "voltage-gpio"); 453 struct device_node *freq_gpio_np = of_find_node_by_name(NULL, 454 "frequency-gpio"); 455 struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL, 456 "slewing-done"); 457 const u32 *value; 458 459 /* 460 * Check to see if it's GPIO driven or PMU only 461 * 462 * The way we extract the GPIO address is slightly hackish, but it 463 * works well enough for now. We need to abstract the whole GPIO 464 * stuff sooner or later anyway 465 */ 466 467 if (volt_gpio_np) 468 voltage_gpio = read_gpio(volt_gpio_np); 469 if (freq_gpio_np) 470 frequency_gpio = read_gpio(freq_gpio_np); 471 if (slew_done_gpio_np) 472 slew_done_gpio = read_gpio(slew_done_gpio_np); 473 474 of_node_put(volt_gpio_np); 475 of_node_put(freq_gpio_np); 476 of_node_put(slew_done_gpio_np); 477 478 /* If we use the frequency GPIOs, calculate the min/max speeds based 479 * on the bus frequencies 480 */ 481 if (frequency_gpio && slew_done_gpio) { 482 int lenp, rc; 483 const u32 *freqs, *ratio; 484 485 freqs = of_get_property(cpunode, "bus-frequencies", &lenp); 486 lenp /= sizeof(u32); 487 if (freqs == NULL || lenp != 2) { 488 pr_err("bus-frequencies incorrect or missing\n"); 489 return 1; 490 } 491 ratio = of_get_property(cpunode, "processor-to-bus-ratio*2", 492 NULL); 493 if (ratio == NULL) { 494 pr_err("processor-to-bus-ratio*2 missing\n"); 495 return 1; 496 } 497 498 /* Get the min/max bus frequencies */ 499 low_freq = min(freqs[0], freqs[1]); 500 hi_freq = max(freqs[0], freqs[1]); 501 502 /* Grrrr.. It _seems_ that the device-tree is lying on the low bus 503 * frequency, it claims it to be around 84Mhz on some models while 504 * it appears to be approx. 101Mhz on all. Let's hack around here... 505 * fortunately, we don't need to be too precise 506 */ 507 if (low_freq < 98000000) 508 low_freq = 101000000; 509 510 /* Convert those to CPU core clocks */ 511 low_freq = (low_freq * (*ratio)) / 2000; 512 hi_freq = (hi_freq * (*ratio)) / 2000; 513 514 /* Now we get the frequencies, we read the GPIO to see what is out current 515 * speed 516 */ 517 rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0); 518 cur_freq = (rc & 0x01) ? hi_freq : low_freq; 519 520 set_speed_proc = gpios_set_cpu_speed; 521 return 1; 522 } 523 524 /* If we use the PMU, look for the min & max frequencies in the 525 * device-tree 526 */ 527 value = of_get_property(cpunode, "min-clock-frequency", NULL); 528 if (!value) 529 return 1; 530 low_freq = (*value) / 1000; 531 /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree 532 * here */ 533 if (low_freq < 100000) 534 low_freq *= 10; 535 536 value = of_get_property(cpunode, "max-clock-frequency", NULL); 537 if (!value) 538 return 1; 539 hi_freq = (*value) / 1000; 540 set_speed_proc = pmu_set_cpu_speed; 541 is_pmu_based = 1; 542 543 return 0; 544} 545 546static int pmac_cpufreq_init_7447A(struct device_node *cpunode) 547{ 548 struct device_node *volt_gpio_np; 549 550 if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL) 551 return 1; 552 553 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select"); 554 if (volt_gpio_np) 555 voltage_gpio = read_gpio(volt_gpio_np); 556 of_node_put(volt_gpio_np); 557 if (!voltage_gpio){ 558 pr_err("missing cpu-vcore-select gpio\n"); 559 return 1; 560 } 561 562 /* OF only reports the high frequency */ 563 hi_freq = cur_freq; 564 low_freq = cur_freq/2; 565 566 /* Read actual frequency from CPU */ 567 cur_freq = dfs_get_cpu_speed(); 568 set_speed_proc = dfs_set_cpu_speed; 569 get_speed_proc = dfs_get_cpu_speed; 570 571 return 0; 572} 573 574static int pmac_cpufreq_init_750FX(struct device_node *cpunode) 575{ 576 struct device_node *volt_gpio_np; 577 u32 pvr; 578 const u32 *value; 579 580 if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL) 581 return 1; 582 583 hi_freq = cur_freq; 584 value = of_get_property(cpunode, "reduced-clock-frequency", NULL); 585 if (!value) 586 return 1; 587 low_freq = (*value) / 1000; 588 589 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select"); 590 if (volt_gpio_np) 591 voltage_gpio = read_gpio(volt_gpio_np); 592 593 of_node_put(volt_gpio_np); 594 pvr = mfspr(SPRN_PVR); 595 has_cpu_l2lve = !((pvr & 0xf00) == 0x100); 596 597 set_speed_proc = cpu_750fx_cpu_speed; 598 get_speed_proc = cpu_750fx_get_cpu_speed; 599 cur_freq = cpu_750fx_get_cpu_speed(); 600 601 return 0; 602} 603 604/* Currently, we support the following machines: 605 * 606 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz) 607 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz) 608 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz) 609 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz) 610 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz) 611 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage) 612 * - Recent MacRISC3 laptops 613 * - All new machines with 7447A CPUs 614 */ 615static int __init pmac_cpufreq_setup(void) 616{ 617 struct device_node *cpunode; 618 const u32 *value; 619 620 if (strstr(boot_command_line, "nocpufreq")) 621 return 0; 622 623 /* Get first CPU node */ 624 cpunode = of_cpu_device_node_get(0); 625 if (!cpunode) 626 goto out; 627 628 /* Get current cpu clock freq */ 629 value = of_get_property(cpunode, "clock-frequency", NULL); 630 if (!value) 631 goto out; 632 cur_freq = (*value) / 1000; 633 634 /* Check for 7447A based MacRISC3 */ 635 if (of_machine_is_compatible("MacRISC3") && 636 of_get_property(cpunode, "dynamic-power-step", NULL) && 637 PVR_VER(mfspr(SPRN_PVR)) == 0x8003) { 638 pmac_cpufreq_init_7447A(cpunode); 639 640 /* Allow dynamic switching */ 641 transition_latency = 8000000; 642 pmac_cpufreq_driver.flags &= ~CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING; 643 /* Check for other MacRISC3 machines */ 644 } else if (of_machine_is_compatible("PowerBook3,4") || 645 of_machine_is_compatible("PowerBook3,5") || 646 of_machine_is_compatible("MacRISC3")) { 647 pmac_cpufreq_init_MacRISC3(cpunode); 648 /* Else check for iBook2 500/600 */ 649 } else if (of_machine_is_compatible("PowerBook4,1")) { 650 hi_freq = cur_freq; 651 low_freq = 400000; 652 set_speed_proc = pmu_set_cpu_speed; 653 is_pmu_based = 1; 654 } 655 /* Else check for TiPb 550 */ 656 else if (of_machine_is_compatible("PowerBook3,3") && cur_freq == 550000) { 657 hi_freq = cur_freq; 658 low_freq = 500000; 659 set_speed_proc = pmu_set_cpu_speed; 660 is_pmu_based = 1; 661 } 662 /* Else check for TiPb 400 & 500 */ 663 else if (of_machine_is_compatible("PowerBook3,2")) { 664 /* We only know about the 400 MHz and the 500Mhz model 665 * they both have 300 MHz as low frequency 666 */ 667 if (cur_freq < 350000 || cur_freq > 550000) 668 goto out; 669 hi_freq = cur_freq; 670 low_freq = 300000; 671 set_speed_proc = pmu_set_cpu_speed; 672 is_pmu_based = 1; 673 } 674 /* Else check for 750FX */ 675 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000) 676 pmac_cpufreq_init_750FX(cpunode); 677out: 678 of_node_put(cpunode); 679 if (set_speed_proc == NULL) 680 return -ENODEV; 681 682 pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq; 683 pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq; 684 ppc_proc_freq = cur_freq * 1000ul; 685 686 pr_info("Registering PowerMac CPU frequency driver\n"); 687 pr_info("Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n", 688 low_freq/1000, hi_freq/1000, cur_freq/1000); 689 690 return cpufreq_register_driver(&pmac_cpufreq_driver); 691} 692 693module_init(pmac_cpufreq_setup); 694 695