1// SPDX-License-Identifier: GPL-2.0
2/*
3 * STM32 Low-Power Timer Encoder and Counter driver
4 *
5 * Copyright (C) STMicroelectronics 2017
6 *
7 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
8 *
9 * Inspired by 104-quad-8 and stm32-timer-trigger drivers.
10 *
11 */
12
13#include <linux/bitfield.h>
14#include <linux/counter.h>
15#include <linux/mfd/stm32-lptimer.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/platform_device.h>
20
21struct stm32_lptim_cnt {
22	struct counter_device counter;
23	struct device *dev;
24	struct regmap *regmap;
25	struct clk *clk;
26	u32 ceiling;
27	u32 polarity;
28	u32 quadrature_mode;
29	bool enabled;
30};
31
32static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
33{
34	u32 val;
35	int ret;
36
37	ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
38	if (ret)
39		return ret;
40
41	return FIELD_GET(STM32_LPTIM_ENABLE, val);
42}
43
44static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
45					int enable)
46{
47	int ret;
48	u32 val;
49
50	val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
51	ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
52	if (ret)
53		return ret;
54
55	if (!enable) {
56		clk_disable(priv->clk);
57		priv->enabled = false;
58		return 0;
59	}
60
61	/* LP timer must be enabled before writing CMP & ARR */
62	ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
63	if (ret)
64		return ret;
65
66	ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
67	if (ret)
68		return ret;
69
70	/* ensure CMP & ARR registers are properly written */
71	ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
72				       (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
73				       100, 1000);
74	if (ret)
75		return ret;
76
77	ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
78			   STM32_LPTIM_CMPOKCF_ARROKCF);
79	if (ret)
80		return ret;
81
82	ret = clk_enable(priv->clk);
83	if (ret) {
84		regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
85		return ret;
86	}
87	priv->enabled = true;
88
89	/* Start LP timer in continuous mode */
90	return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
91				  STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
92}
93
94static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
95{
96	u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
97		   STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
98	u32 val;
99
100	/* Setup LP timer encoder/counter and polarity, without prescaler */
101	if (priv->quadrature_mode)
102		val = enable ? STM32_LPTIM_ENC : 0;
103	else
104		val = enable ? STM32_LPTIM_COUNTMODE : 0;
105	val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
106
107	return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
108}
109
110/**
111 * enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
112 * @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
113 * @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
114 *
115 * In non-quadrature mode, device counts up on active edge.
116 * In quadrature mode, encoder counting scenarios are as follows:
117 * +---------+----------+--------------------+--------------------+
118 * | Active  | Level on |      IN1 signal    |     IN2 signal     |
119 * | edge    | opposite +----------+---------+----------+---------+
120 * |         | signal   |  Rising  | Falling |  Rising  | Falling |
121 * +---------+----------+----------+---------+----------+---------+
122 * | Rising  | High ->  |   Down   |    -    |   Up     |    -    |
123 * | edge    | Low  ->  |   Up     |    -    |   Down   |    -    |
124 * +---------+----------+----------+---------+----------+---------+
125 * | Falling | High ->  |    -     |   Up    |    -     |   Down  |
126 * | edge    | Low  ->  |    -     |   Down  |    -     |   Up    |
127 * +---------+----------+----------+---------+----------+---------+
128 * | Both    | High ->  |   Down   |   Up    |   Up     |   Down  |
129 * | edges   | Low  ->  |   Up     |   Down  |   Down   |   Up    |
130 * +---------+----------+----------+---------+----------+---------+
131 */
132enum stm32_lptim_cnt_function {
133	STM32_LPTIM_COUNTER_INCREASE,
134	STM32_LPTIM_ENCODER_BOTH_EDGE,
135};
136
137static enum counter_count_function stm32_lptim_cnt_functions[] = {
138	[STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
139	[STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
140};
141
142enum stm32_lptim_synapse_action {
143	STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
144	STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
145	STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
146	STM32_LPTIM_SYNAPSE_ACTION_NONE,
147};
148
149static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
150	/* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
151	[STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
152	[STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
153	[STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
154	[STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
155};
156
157static int stm32_lptim_cnt_read(struct counter_device *counter,
158				struct counter_count *count, unsigned long *val)
159{
160	struct stm32_lptim_cnt *const priv = counter->priv;
161	u32 cnt;
162	int ret;
163
164	ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
165	if (ret)
166		return ret;
167
168	*val = cnt;
169
170	return 0;
171}
172
173static int stm32_lptim_cnt_function_get(struct counter_device *counter,
174					struct counter_count *count,
175					size_t *function)
176{
177	struct stm32_lptim_cnt *const priv = counter->priv;
178
179	if (!priv->quadrature_mode) {
180		*function = STM32_LPTIM_COUNTER_INCREASE;
181		return 0;
182	}
183
184	if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
185		*function = STM32_LPTIM_ENCODER_BOTH_EDGE;
186		return 0;
187	}
188
189	return -EINVAL;
190}
191
192static int stm32_lptim_cnt_function_set(struct counter_device *counter,
193					struct counter_count *count,
194					size_t function)
195{
196	struct stm32_lptim_cnt *const priv = counter->priv;
197
198	if (stm32_lptim_is_enabled(priv))
199		return -EBUSY;
200
201	switch (function) {
202	case STM32_LPTIM_COUNTER_INCREASE:
203		priv->quadrature_mode = 0;
204		return 0;
205	case STM32_LPTIM_ENCODER_BOTH_EDGE:
206		priv->quadrature_mode = 1;
207		priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
208		return 0;
209	}
210
211	return -EINVAL;
212}
213
214static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
215					   struct counter_count *count,
216					   void *private, char *buf)
217{
218	struct stm32_lptim_cnt *const priv = counter->priv;
219	int ret;
220
221	ret = stm32_lptim_is_enabled(priv);
222	if (ret < 0)
223		return ret;
224
225	return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
226}
227
228static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
229					    struct counter_count *count,
230					    void *private,
231					    const char *buf, size_t len)
232{
233	struct stm32_lptim_cnt *const priv = counter->priv;
234	bool enable;
235	int ret;
236
237	ret = kstrtobool(buf, &enable);
238	if (ret)
239		return ret;
240
241	/* Check nobody uses the timer, or already disabled/enabled */
242	ret = stm32_lptim_is_enabled(priv);
243	if ((ret < 0) || (!ret && !enable))
244		return ret;
245	if (enable && ret)
246		return -EBUSY;
247
248	ret = stm32_lptim_setup(priv, enable);
249	if (ret)
250		return ret;
251
252	ret = stm32_lptim_set_enable_state(priv, enable);
253	if (ret)
254		return ret;
255
256	return len;
257}
258
259static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
260					    struct counter_count *count,
261					    void *private, char *buf)
262{
263	struct stm32_lptim_cnt *const priv = counter->priv;
264
265	return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
266}
267
268static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
269					     struct counter_count *count,
270					     void *private,
271					     const char *buf, size_t len)
272{
273	struct stm32_lptim_cnt *const priv = counter->priv;
274	unsigned int ceiling;
275	int ret;
276
277	if (stm32_lptim_is_enabled(priv))
278		return -EBUSY;
279
280	ret = kstrtouint(buf, 0, &ceiling);
281	if (ret)
282		return ret;
283
284	if (ceiling > STM32_LPTIM_MAX_ARR)
285		return -EINVAL;
286
287	priv->ceiling = ceiling;
288
289	return len;
290}
291
292static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
293	{
294		.name = "enable",
295		.read = stm32_lptim_cnt_enable_read,
296		.write = stm32_lptim_cnt_enable_write
297	},
298	{
299		.name = "ceiling",
300		.read = stm32_lptim_cnt_ceiling_read,
301		.write = stm32_lptim_cnt_ceiling_write
302	},
303};
304
305static int stm32_lptim_cnt_action_get(struct counter_device *counter,
306				      struct counter_count *count,
307				      struct counter_synapse *synapse,
308				      size_t *action)
309{
310	struct stm32_lptim_cnt *const priv = counter->priv;
311	size_t function;
312	int err;
313
314	err = stm32_lptim_cnt_function_get(counter, count, &function);
315	if (err)
316		return err;
317
318	switch (function) {
319	case STM32_LPTIM_COUNTER_INCREASE:
320		/* LP Timer acts as up-counter on input 1 */
321		if (synapse->signal->id == count->synapses[0].signal->id)
322			*action = priv->polarity;
323		else
324			*action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
325		return 0;
326	case STM32_LPTIM_ENCODER_BOTH_EDGE:
327		*action = priv->polarity;
328		return 0;
329	}
330
331	return -EINVAL;
332}
333
334static int stm32_lptim_cnt_action_set(struct counter_device *counter,
335				      struct counter_count *count,
336				      struct counter_synapse *synapse,
337				      size_t action)
338{
339	struct stm32_lptim_cnt *const priv = counter->priv;
340	size_t function;
341	int err;
342
343	if (stm32_lptim_is_enabled(priv))
344		return -EBUSY;
345
346	err = stm32_lptim_cnt_function_get(counter, count, &function);
347	if (err)
348		return err;
349
350	/* only set polarity when in counter mode (on input 1) */
351	if (function == STM32_LPTIM_COUNTER_INCREASE
352	    && synapse->signal->id == count->synapses[0].signal->id) {
353		switch (action) {
354		case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
355		case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
356		case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
357			priv->polarity = action;
358			return 0;
359		}
360	}
361
362	return -EINVAL;
363}
364
365static const struct counter_ops stm32_lptim_cnt_ops = {
366	.count_read = stm32_lptim_cnt_read,
367	.function_get = stm32_lptim_cnt_function_get,
368	.function_set = stm32_lptim_cnt_function_set,
369	.action_get = stm32_lptim_cnt_action_get,
370	.action_set = stm32_lptim_cnt_action_set,
371};
372
373static struct counter_signal stm32_lptim_cnt_signals[] = {
374	{
375		.id = 0,
376		.name = "Channel 1 Quadrature A"
377	},
378	{
379		.id = 1,
380		.name = "Channel 1 Quadrature B"
381	}
382};
383
384static struct counter_synapse stm32_lptim_cnt_synapses[] = {
385	{
386		.actions_list = stm32_lptim_cnt_synapse_actions,
387		.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
388		.signal = &stm32_lptim_cnt_signals[0]
389	},
390	{
391		.actions_list = stm32_lptim_cnt_synapse_actions,
392		.num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
393		.signal = &stm32_lptim_cnt_signals[1]
394	}
395};
396
397/* LP timer with encoder */
398static struct counter_count stm32_lptim_enc_counts = {
399	.id = 0,
400	.name = "LPTimer Count",
401	.functions_list = stm32_lptim_cnt_functions,
402	.num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
403	.synapses = stm32_lptim_cnt_synapses,
404	.num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
405	.ext = stm32_lptim_cnt_ext,
406	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
407};
408
409/* LP timer without encoder (counter only) */
410static struct counter_count stm32_lptim_in1_counts = {
411	.id = 0,
412	.name = "LPTimer Count",
413	.functions_list = stm32_lptim_cnt_functions,
414	.num_functions = 1,
415	.synapses = stm32_lptim_cnt_synapses,
416	.num_synapses = 1,
417	.ext = stm32_lptim_cnt_ext,
418	.num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
419};
420
421static int stm32_lptim_cnt_probe(struct platform_device *pdev)
422{
423	struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
424	struct stm32_lptim_cnt *priv;
425
426	if (IS_ERR_OR_NULL(ddata))
427		return -EINVAL;
428
429	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
430	if (!priv)
431		return -ENOMEM;
432
433	priv->dev = &pdev->dev;
434	priv->regmap = ddata->regmap;
435	priv->clk = ddata->clk;
436	priv->ceiling = STM32_LPTIM_MAX_ARR;
437
438	/* Initialize Counter device */
439	priv->counter.name = dev_name(&pdev->dev);
440	priv->counter.parent = &pdev->dev;
441	priv->counter.ops = &stm32_lptim_cnt_ops;
442	if (ddata->has_encoder) {
443		priv->counter.counts = &stm32_lptim_enc_counts;
444		priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
445	} else {
446		priv->counter.counts = &stm32_lptim_in1_counts;
447		priv->counter.num_signals = 1;
448	}
449	priv->counter.num_counts = 1;
450	priv->counter.signals = stm32_lptim_cnt_signals;
451	priv->counter.priv = priv;
452
453	platform_set_drvdata(pdev, priv);
454
455	return devm_counter_register(&pdev->dev, &priv->counter);
456}
457
458#ifdef CONFIG_PM_SLEEP
459static int stm32_lptim_cnt_suspend(struct device *dev)
460{
461	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
462	int ret;
463
464	/* Only take care of enabled counter: don't disturb other MFD child */
465	if (priv->enabled) {
466		ret = stm32_lptim_setup(priv, 0);
467		if (ret)
468			return ret;
469
470		ret = stm32_lptim_set_enable_state(priv, 0);
471		if (ret)
472			return ret;
473
474		/* Force enable state for later resume */
475		priv->enabled = true;
476	}
477
478	return pinctrl_pm_select_sleep_state(dev);
479}
480
481static int stm32_lptim_cnt_resume(struct device *dev)
482{
483	struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
484	int ret;
485
486	ret = pinctrl_pm_select_default_state(dev);
487	if (ret)
488		return ret;
489
490	if (priv->enabled) {
491		priv->enabled = false;
492		ret = stm32_lptim_setup(priv, 1);
493		if (ret)
494			return ret;
495
496		ret = stm32_lptim_set_enable_state(priv, 1);
497		if (ret)
498			return ret;
499	}
500
501	return 0;
502}
503#endif
504
505static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
506			 stm32_lptim_cnt_resume);
507
508static const struct of_device_id stm32_lptim_cnt_of_match[] = {
509	{ .compatible = "st,stm32-lptimer-counter", },
510	{},
511};
512MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
513
514static struct platform_driver stm32_lptim_cnt_driver = {
515	.probe = stm32_lptim_cnt_probe,
516	.driver = {
517		.name = "stm32-lptimer-counter",
518		.of_match_table = stm32_lptim_cnt_of_match,
519		.pm = &stm32_lptim_cnt_pm_ops,
520	},
521};
522module_platform_driver(stm32_lptim_cnt_driver);
523
524MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
525MODULE_ALIAS("platform:stm32-lptimer-counter");
526MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
527MODULE_LICENSE("GPL v2");
528