1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * System timer for CSR SiRFprimaII 4 * 5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 6 */ 7 8#include <linux/kernel.h> 9#include <linux/interrupt.h> 10#include <linux/clockchips.h> 11#include <linux/clocksource.h> 12#include <linux/cpu.h> 13#include <linux/bitops.h> 14#include <linux/irq.h> 15#include <linux/clk.h> 16#include <linux/slab.h> 17#include <linux/of.h> 18#include <linux/of_irq.h> 19#include <linux/of_address.h> 20#include <linux/sched_clock.h> 21 22#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 23#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 24#define SIRFSOC_TIMER_MATCH_0 0x0018 25#define SIRFSOC_TIMER_MATCH_1 0x001c 26#define SIRFSOC_TIMER_COUNTER_0 0x0048 27#define SIRFSOC_TIMER_COUNTER_1 0x004c 28#define SIRFSOC_TIMER_INTR_STATUS 0x0060 29#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064 30#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068 31#define SIRFSOC_TIMER_64COUNTER_LO 0x006c 32#define SIRFSOC_TIMER_64COUNTER_HI 0x0070 33#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074 34#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078 35#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c 36#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080 37 38#define SIRFSOC_TIMER_REG_CNT 6 39 40static unsigned long atlas7_timer_rate; 41 42static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { 43 SIRFSOC_TIMER_WATCHDOG_EN, 44 SIRFSOC_TIMER_32COUNTER_0_CTRL, 45 SIRFSOC_TIMER_32COUNTER_1_CTRL, 46 SIRFSOC_TIMER_64COUNTER_CTRL, 47 SIRFSOC_TIMER_64COUNTER_RLATCHED_LO, 48 SIRFSOC_TIMER_64COUNTER_RLATCHED_HI, 49}; 50 51static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; 52 53static void __iomem *sirfsoc_timer_base; 54 55/* disable count and interrupt */ 56static inline void sirfsoc_timer_count_disable(int idx) 57{ 58 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, 59 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); 60} 61 62/* enable count and interrupt */ 63static inline void sirfsoc_timer_count_enable(int idx) 64{ 65 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, 66 sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx); 67} 68 69/* timer interrupt handler */ 70static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) 71{ 72 struct clock_event_device *ce = dev_id; 73 int cpu = smp_processor_id(); 74 75 /* clear timer interrupt */ 76 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); 77 78 if (clockevent_state_oneshot(ce)) 79 sirfsoc_timer_count_disable(cpu); 80 81 ce->event_handler(ce); 82 83 return IRQ_HANDLED; 84} 85 86/* read 64-bit timer counter */ 87static u64 sirfsoc_timer_read(struct clocksource *cs) 88{ 89 u64 cycles; 90 91 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | 92 BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); 93 94 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); 95 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); 96 97 return cycles; 98} 99 100static int sirfsoc_timer_set_next_event(unsigned long delta, 101 struct clock_event_device *ce) 102{ 103 int cpu = smp_processor_id(); 104 105 /* disable timer first, then modify the related registers */ 106 sirfsoc_timer_count_disable(cpu); 107 108 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + 109 4 * cpu); 110 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + 111 4 * cpu); 112 113 /* enable the tick */ 114 sirfsoc_timer_count_enable(cpu); 115 116 return 0; 117} 118 119/* Oneshot is enabled in set_next_event */ 120static int sirfsoc_timer_shutdown(struct clock_event_device *evt) 121{ 122 sirfsoc_timer_count_disable(smp_processor_id()); 123 return 0; 124} 125 126static void sirfsoc_clocksource_suspend(struct clocksource *cs) 127{ 128 int i; 129 130 for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++) 131 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); 132} 133 134static void sirfsoc_clocksource_resume(struct clocksource *cs) 135{ 136 int i; 137 138 for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++) 139 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); 140 141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], 142 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); 143 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], 144 sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); 145 146 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | 147 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); 148} 149 150static struct clock_event_device __percpu *sirfsoc_clockevent; 151 152static struct clocksource sirfsoc_clocksource = { 153 .name = "sirfsoc_clocksource", 154 .rating = 200, 155 .mask = CLOCKSOURCE_MASK(64), 156 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 157 .read = sirfsoc_timer_read, 158 .suspend = sirfsoc_clocksource_suspend, 159 .resume = sirfsoc_clocksource_resume, 160}; 161 162static unsigned int sirfsoc_timer_irq, sirfsoc_timer1_irq; 163 164static int sirfsoc_local_timer_starting_cpu(unsigned int cpu) 165{ 166 struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu); 167 unsigned int irq; 168 const char *name; 169 170 if (cpu == 0) { 171 irq = sirfsoc_timer_irq; 172 name = "sirfsoc_timer0"; 173 } else { 174 irq = sirfsoc_timer1_irq; 175 name = "sirfsoc_timer1"; 176 } 177 178 ce->irq = irq; 179 ce->name = "local_timer"; 180 ce->features = CLOCK_EVT_FEAT_ONESHOT; 181 ce->rating = 200; 182 ce->set_state_shutdown = sirfsoc_timer_shutdown; 183 ce->set_state_oneshot = sirfsoc_timer_shutdown; 184 ce->tick_resume = sirfsoc_timer_shutdown; 185 ce->set_next_event = sirfsoc_timer_set_next_event; 186 clockevents_calc_mult_shift(ce, atlas7_timer_rate, 60); 187 ce->max_delta_ns = clockevent_delta2ns(-2, ce); 188 ce->max_delta_ticks = (unsigned long)-2; 189 ce->min_delta_ns = clockevent_delta2ns(2, ce); 190 ce->min_delta_ticks = 2; 191 ce->cpumask = cpumask_of(cpu); 192 193 BUG_ON(request_irq(ce->irq, sirfsoc_timer_interrupt, 194 IRQF_TIMER | IRQF_NOBALANCING, name, ce)); 195 irq_force_affinity(ce->irq, cpumask_of(cpu)); 196 197 clockevents_register_device(ce); 198 return 0; 199} 200 201static int sirfsoc_local_timer_dying_cpu(unsigned int cpu) 202{ 203 struct clock_event_device *ce = per_cpu_ptr(sirfsoc_clockevent, cpu); 204 205 sirfsoc_timer_count_disable(1); 206 207 if (cpu == 0) 208 free_irq(sirfsoc_timer_irq, ce); 209 else 210 free_irq(sirfsoc_timer1_irq, ce); 211 return 0; 212} 213 214static int __init sirfsoc_clockevent_init(void) 215{ 216 sirfsoc_clockevent = alloc_percpu(struct clock_event_device); 217 BUG_ON(!sirfsoc_clockevent); 218 219 /* Install and invoke hotplug callbacks */ 220 return cpuhp_setup_state(CPUHP_AP_MARCO_TIMER_STARTING, 221 "clockevents/marco:starting", 222 sirfsoc_local_timer_starting_cpu, 223 sirfsoc_local_timer_dying_cpu); 224} 225 226/* initialize the kernel jiffy timer source */ 227static int __init sirfsoc_atlas7_timer_init(struct device_node *np) 228{ 229 struct clk *clk; 230 231 clk = of_clk_get(np, 0); 232 BUG_ON(IS_ERR(clk)); 233 234 BUG_ON(clk_prepare_enable(clk)); 235 236 atlas7_timer_rate = clk_get_rate(clk); 237 238 /* timer dividers: 0, not divided */ 239 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); 240 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL); 241 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL); 242 243 /* Initialize timer counters to 0 */ 244 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO); 245 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI); 246 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | 247 BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); 248 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0); 249 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1); 250 251 /* Clear all interrupts */ 252 writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); 253 254 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, atlas7_timer_rate)); 255 256 return sirfsoc_clockevent_init(); 257} 258 259static int __init sirfsoc_of_timer_init(struct device_node *np) 260{ 261 sirfsoc_timer_base = of_iomap(np, 0); 262 if (!sirfsoc_timer_base) { 263 pr_err("unable to map timer cpu registers\n"); 264 return -ENXIO; 265 } 266 267 sirfsoc_timer_irq = irq_of_parse_and_map(np, 0); 268 if (!sirfsoc_timer_irq) { 269 pr_err("No irq passed for timer0 via DT\n"); 270 return -EINVAL; 271 } 272 273 sirfsoc_timer1_irq = irq_of_parse_and_map(np, 1); 274 if (!sirfsoc_timer1_irq) { 275 pr_err("No irq passed for timer1 via DT\n"); 276 return -EINVAL; 277 } 278 279 return sirfsoc_atlas7_timer_init(np); 280} 281TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init); 282