1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Zynq UltraScale+ MPSoC Divider support 4 * 5 * Copyright (C) 2016-2019 Xilinx 6 * 7 * Adjustable divider clock implementation 8 */ 9 10#include <linux/clk.h> 11#include <linux/clk-provider.h> 12#include <linux/slab.h> 13#include "clk-zynqmp.h" 14 15/* 16 * DOC: basic adjustable divider clock that cannot gate 17 * 18 * Traits of this clock: 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 22 * parent - fixed parent. No clk_set_parent support 23 */ 24 25#define to_zynqmp_clk_divider(_hw) \ 26 container_of(_hw, struct zynqmp_clk_divider, hw) 27 28#define CLK_FRAC BIT(13) /* has a fractional parent */ 29#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */ 30 31/** 32 * struct zynqmp_clk_divider - adjustable divider clock 33 * @hw: handle between common and hardware-specific interfaces 34 * @flags: Hardware specific flags 35 * @is_frac: The divider is a fractional divider 36 * @clk_id: Id of clock 37 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2) 38 */ 39struct zynqmp_clk_divider { 40 struct clk_hw hw; 41 u8 flags; 42 bool is_frac; 43 u32 clk_id; 44 u32 div_type; 45 u16 max_div; 46}; 47 48static inline int zynqmp_divider_get_val(unsigned long parent_rate, 49 unsigned long rate, u16 flags) 50{ 51 int up, down; 52 unsigned long up_rate, down_rate; 53 54 if (flags & CLK_DIVIDER_POWER_OF_TWO) { 55 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); 56 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate); 57 58 up = __roundup_pow_of_two(up); 59 down = __rounddown_pow_of_two(down); 60 61 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); 62 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); 63 64 return (rate - up_rate) <= (down_rate - rate) ? up : down; 65 66 } else { 67 return DIV_ROUND_CLOSEST(parent_rate, rate); 68 } 69} 70 71/** 72 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock 73 * @hw: handle between common and hardware-specific interfaces 74 * @parent_rate: rate of parent clock 75 * 76 * Return: 0 on success else error+reason 77 */ 78static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, 79 unsigned long parent_rate) 80{ 81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 82 const char *clk_name = clk_hw_get_name(hw); 83 u32 clk_id = divider->clk_id; 84 u32 div_type = divider->div_type; 85 u32 div, value; 86 int ret; 87 88 ret = zynqmp_pm_clock_getdivider(clk_id, &div); 89 90 if (ret) 91 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 92 __func__, clk_name, ret); 93 94 if (div_type == TYPE_DIV1) 95 value = div & 0xFFFF; 96 else 97 value = div >> 16; 98 99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 100 value = 1 << value; 101 102 if (!value) { 103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), 104 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n", 105 clk_name); 106 return parent_rate; 107 } 108 109 return DIV_ROUND_UP_ULL(parent_rate, value); 110} 111 112/** 113 * zynqmp_clk_divider_round_rate() - Round rate of divider clock 114 * @hw: handle between common and hardware-specific interfaces 115 * @rate: rate of clock to be set 116 * @prate: rate of parent clock 117 * 118 * Return: 0 on success else error+reason 119 */ 120static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, 121 unsigned long rate, 122 unsigned long *prate) 123{ 124 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 125 const char *clk_name = clk_hw_get_name(hw); 126 u32 clk_id = divider->clk_id; 127 u32 div_type = divider->div_type; 128 u32 bestdiv; 129 int ret; 130 u8 width; 131 132 /* if read only, just return current value */ 133 if (divider->flags & CLK_DIVIDER_READ_ONLY) { 134 ret = zynqmp_pm_clock_getdivider(clk_id, &bestdiv); 135 136 if (ret) 137 pr_warn_once("%s() get divider failed for %s, ret = %d\n", 138 __func__, clk_name, ret); 139 if (div_type == TYPE_DIV1) 140 bestdiv = bestdiv & 0xFFFF; 141 else 142 bestdiv = bestdiv >> 16; 143 144 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 145 bestdiv = 1 << bestdiv; 146 147 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); 148 } 149 150 width = fls(divider->max_div); 151 152 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); 153 154 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) 155 *prate = rate; 156 157 return rate; 158} 159 160/** 161 * zynqmp_clk_divider_set_rate() - Set rate of divider clock 162 * @hw: handle between common and hardware-specific interfaces 163 * @rate: rate of clock to be set 164 * @parent_rate: rate of parent clock 165 * 166 * Return: 0 on success else error+reason 167 */ 168static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 169 unsigned long parent_rate) 170{ 171 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); 172 const char *clk_name = clk_hw_get_name(hw); 173 u32 clk_id = divider->clk_id; 174 u32 div_type = divider->div_type; 175 u32 value, div; 176 int ret; 177 178 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags); 179 if (div_type == TYPE_DIV1) { 180 div = value & 0xFFFF; 181 div |= 0xffff << 16; 182 } else { 183 div = 0xffff; 184 div |= value << 16; 185 } 186 187 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 188 div = __ffs(div); 189 190 ret = zynqmp_pm_clock_setdivider(clk_id, div); 191 192 if (ret) 193 pr_warn_once("%s() set divider failed for %s, ret = %d\n", 194 __func__, clk_name, ret); 195 196 return ret; 197} 198 199static const struct clk_ops zynqmp_clk_divider_ops = { 200 .recalc_rate = zynqmp_clk_divider_recalc_rate, 201 .round_rate = zynqmp_clk_divider_round_rate, 202 .set_rate = zynqmp_clk_divider_set_rate, 203}; 204 205/** 206 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware. 207 * @clk_id: Id of clock 208 * @type: Divider type 209 * 210 * Return: Maximum divisor of a clock if query data is successful 211 * U16_MAX in case of query data is not success 212 */ 213static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) 214{ 215 struct zynqmp_pm_query_data qdata = {0}; 216 u32 ret_payload[PAYLOAD_ARG_CNT]; 217 int ret; 218 219 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR; 220 qdata.arg1 = clk_id; 221 qdata.arg2 = type; 222 ret = zynqmp_pm_query_data(qdata, ret_payload); 223 /* 224 * To maintain backward compatibility return maximum possible value 225 * (0xFFFF) if query for max divisor is not successful. 226 */ 227 if (ret) 228 return U16_MAX; 229 230 return ret_payload[1]; 231} 232 233/** 234 * zynqmp_clk_register_divider() - Register a divider clock 235 * @name: Name of this clock 236 * @clk_id: Id of clock 237 * @parents: Name of this clock's parents 238 * @num_parents: Number of parents 239 * @nodes: Clock topology node 240 * 241 * Return: clock hardware to registered clock divider 242 */ 243struct clk_hw *zynqmp_clk_register_divider(const char *name, 244 u32 clk_id, 245 const char * const *parents, 246 u8 num_parents, 247 const struct clock_topology *nodes) 248{ 249 struct zynqmp_clk_divider *div; 250 struct clk_hw *hw; 251 struct clk_init_data init; 252 int ret; 253 254 /* allocate the divider */ 255 div = kzalloc(sizeof(*div), GFP_KERNEL); 256 if (!div) 257 return ERR_PTR(-ENOMEM); 258 259 init.name = name; 260 init.ops = &zynqmp_clk_divider_ops; 261 /* CLK_FRAC is not defined in the common clk framework */ 262 init.flags = nodes->flag & ~CLK_FRAC; 263 init.parent_names = parents; 264 init.num_parents = 1; 265 266 /* struct clk_divider assignments */ 267 div->is_frac = !!((nodes->flag & CLK_FRAC) | 268 (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); 269 div->flags = nodes->type_flag; 270 div->hw.init = &init; 271 div->clk_id = clk_id; 272 div->div_type = nodes->type; 273 274 /* 275 * To achieve best possible rate, maximum limit of divider is required 276 * while computation. 277 */ 278 div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); 279 280 hw = &div->hw; 281 ret = clk_hw_register(NULL, hw); 282 if (ret) { 283 kfree(div); 284 hw = ERR_PTR(ret); 285 } 286 287 return hw; 288} 289