1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *  Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8
9#include <linux/spinlock.h>
10
11#include <linux/firmware/xlnx-zynqmp.h>
12
13enum topology_type {
14	TYPE_INVALID,
15	TYPE_MUX,
16	TYPE_PLL,
17	TYPE_FIXEDFACTOR,
18	TYPE_DIV1,
19	TYPE_DIV2,
20	TYPE_GATE,
21};
22
23/**
24 * struct clock_topology - Clock topology
25 * @type:	Type of topology
26 * @flag:	Topology flags
27 * @type_flag:	Topology type specific flag
28 */
29struct clock_topology {
30	u32 type;
31	u32 flag;
32	u32 type_flag;
33	u8 custom_type_flag;
34};
35
36struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
37				       const char * const *parents,
38				       u8 num_parents,
39				       const struct clock_topology *nodes);
40
41struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
42					const char * const *parents,
43					u8 num_parents,
44					const struct clock_topology *nodes);
45
46struct clk_hw *zynqmp_clk_register_divider(const char *name,
47					   u32 clk_id,
48					   const char * const *parents,
49					   u8 num_parents,
50					   const struct clock_topology *nodes);
51
52struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
53				       const char * const *parents,
54				       u8 num_parents,
55				       const struct clock_topology *nodes);
56
57struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
58					u32 clk_id,
59					const char * const *parents,
60					u8 num_parents,
61					const struct clock_topology *nodes);
62
63#endif
64