1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Zynq clock controller 4 * 5 * Copyright (C) 2012 - 2013 Xilinx 6 * 7 * Sören Brinkmann <soren.brinkmann@xilinx.com> 8 */ 9 10#include <linux/clk/zynq.h> 11#include <linux/clk.h> 12#include <linux/clk-provider.h> 13#include <linux/of.h> 14#include <linux/of_address.h> 15#include <linux/slab.h> 16#include <linux/string.h> 17#include <linux/io.h> 18 19static void __iomem *zynq_clkc_base; 20 21#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) 22#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) 23#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) 24#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) 25#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) 26#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) 27#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) 28#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) 29#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) 30#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) 31#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) 32#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) 33#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) 34#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) 35#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) 36#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) 37#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) 38#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) 39#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) 40#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) 41#define SLCR_621_TRUE (zynq_clkc_base + 0xc4) 42#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) 43 44#define NUM_MIO_PINS 54 45 46#define DBG_CLK_CTRL_CLKACT_TRC BIT(0) 47#define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) 48 49enum zynq_clk { 50 armpll, ddrpll, iopll, 51 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, 52 ddr2x, ddr3x, dci, 53 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, 54 sdio0, sdio1, uart0, uart1, spi0, spi1, dma, 55 usb0_aper, usb1_aper, gem0_aper, gem1_aper, 56 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, 57 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, 58 smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; 59 60static struct clk *ps_clk; 61static struct clk *clks[clk_max]; 62static struct clk_onecell_data clk_data; 63 64static DEFINE_SPINLOCK(armpll_lock); 65static DEFINE_SPINLOCK(ddrpll_lock); 66static DEFINE_SPINLOCK(iopll_lock); 67static DEFINE_SPINLOCK(armclk_lock); 68static DEFINE_SPINLOCK(swdtclk_lock); 69static DEFINE_SPINLOCK(ddrclk_lock); 70static DEFINE_SPINLOCK(dciclk_lock); 71static DEFINE_SPINLOCK(gem0clk_lock); 72static DEFINE_SPINLOCK(gem1clk_lock); 73static DEFINE_SPINLOCK(canclk_lock); 74static DEFINE_SPINLOCK(canmioclk_lock); 75static DEFINE_SPINLOCK(dbgclk_lock); 76static DEFINE_SPINLOCK(aperclk_lock); 77 78static const char *const armpll_parents[] __initconst = {"armpll_int", 79 "ps_clk"}; 80static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", 81 "ps_clk"}; 82static const char *const iopll_parents[] __initconst = {"iopll_int", 83 "ps_clk"}; 84static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; 85static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; 86static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", 87 "can0_mio_mux"}; 88static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", 89 "can1_mio_mux"}; 90static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", 91 "dummy_name"}; 92 93static const char *const dbgtrc_emio_input_names[] __initconst = { 94 "trace_emio_clk"}; 95static const char *const gem0_emio_input_names[] __initconst = { 96 "gem0_emio_clk"}; 97static const char *const gem1_emio_input_names[] __initconst = { 98 "gem1_emio_clk"}; 99static const char *const swdt_ext_clk_input_names[] __initconst = { 100 "swdt_ext_clk"}; 101 102static void __init zynq_clk_register_fclk(enum zynq_clk fclk, 103 const char *clk_name, void __iomem *fclk_ctrl_reg, 104 const char **parents, int enable) 105{ 106 struct clk *clk; 107 u32 enable_reg; 108 char *mux_name; 109 char *div0_name; 110 char *div1_name; 111 spinlock_t *fclk_lock; 112 spinlock_t *fclk_gate_lock; 113 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; 114 115 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); 116 if (!fclk_lock) 117 goto err; 118 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); 119 if (!fclk_gate_lock) 120 goto err_fclk_gate_lock; 121 spin_lock_init(fclk_lock); 122 spin_lock_init(fclk_gate_lock); 123 124 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); 125 if (!mux_name) 126 goto err_mux_name; 127 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 128 if (!div0_name) 129 goto err_div0_name; 130 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 131 if (!div1_name) 132 goto err_div1_name; 133 134 clk = clk_register_mux(NULL, mux_name, parents, 4, 135 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, 136 fclk_lock); 137 138 clk = clk_register_divider(NULL, div0_name, mux_name, 139 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 140 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); 141 142 clk = clk_register_divider(NULL, div1_name, div0_name, 143 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, 144 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 145 fclk_lock); 146 147 clks[fclk] = clk_register_gate(NULL, clk_name, 148 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, 149 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); 150 enable_reg = readl(fclk_gate_reg) & 1; 151 if (enable && !enable_reg) { 152 if (clk_prepare_enable(clks[fclk])) 153 pr_warn("%s: FCLK%u enable failed\n", __func__, 154 fclk - fclk0); 155 } 156 kfree(mux_name); 157 kfree(div0_name); 158 kfree(div1_name); 159 160 return; 161 162err_div1_name: 163 kfree(div0_name); 164err_div0_name: 165 kfree(mux_name); 166err_mux_name: 167 kfree(fclk_gate_lock); 168err_fclk_gate_lock: 169 kfree(fclk_lock); 170err: 171 clks[fclk] = ERR_PTR(-ENOMEM); 172} 173 174static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, 175 enum zynq_clk clk1, const char *clk_name0, 176 const char *clk_name1, void __iomem *clk_ctrl, 177 const char **parents, unsigned int two_gates) 178{ 179 struct clk *clk; 180 char *mux_name; 181 char *div_name; 182 spinlock_t *lock; 183 184 lock = kmalloc(sizeof(*lock), GFP_KERNEL); 185 if (!lock) 186 goto err; 187 spin_lock_init(lock); 188 189 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 190 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 191 192 clk = clk_register_mux(NULL, mux_name, parents, 4, 193 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); 194 195 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 196 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 197 198 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, 199 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); 200 if (two_gates) 201 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, 202 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); 203 204 kfree(mux_name); 205 kfree(div_name); 206 207 return; 208 209err: 210 clks[clk0] = ERR_PTR(-ENOMEM); 211 if (two_gates) 212 clks[clk1] = ERR_PTR(-ENOMEM); 213} 214 215static void __init zynq_clk_setup(struct device_node *np) 216{ 217 int i; 218 u32 tmp; 219 int ret; 220 struct clk *clk; 221 char *clk_name; 222 unsigned int fclk_enable = 0; 223 const char *clk_output_name[clk_max]; 224 const char *cpu_parents[4]; 225 const char *periph_parents[4]; 226 const char *swdt_ext_clk_mux_parents[2]; 227 const char *can_mio_mux_parents[NUM_MIO_PINS]; 228 const char *dummy_nm = "dummy_name"; 229 230 pr_info("Zynq clock init\n"); 231 232 /* get clock output names from DT */ 233 for (i = 0; i < clk_max; i++) { 234 if (of_property_read_string_index(np, "clock-output-names", 235 i, &clk_output_name[i])) { 236 pr_err("%s: clock output name not in DT\n", __func__); 237 BUG(); 238 } 239 } 240 cpu_parents[0] = clk_output_name[armpll]; 241 cpu_parents[1] = clk_output_name[armpll]; 242 cpu_parents[2] = clk_output_name[ddrpll]; 243 cpu_parents[3] = clk_output_name[iopll]; 244 periph_parents[0] = clk_output_name[iopll]; 245 periph_parents[1] = clk_output_name[iopll]; 246 periph_parents[2] = clk_output_name[armpll]; 247 periph_parents[3] = clk_output_name[ddrpll]; 248 249 of_property_read_u32(np, "fclk-enable", &fclk_enable); 250 251 /* ps_clk */ 252 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); 253 if (ret) { 254 pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); 255 tmp = 33333333; 256 } 257 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); 258 259 /* PLLs */ 260 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 261 SLCR_PLL_STATUS, 0, &armpll_lock); 262 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 263 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 264 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); 265 266 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 267 SLCR_PLL_STATUS, 1, &ddrpll_lock); 268 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 269 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, 270 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); 271 272 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 273 SLCR_PLL_STATUS, 2, &iopll_lock); 274 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 275 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, 276 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); 277 278 /* CPU clocks */ 279 tmp = readl(SLCR_621_TRUE) & 1; 280 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 281 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, 282 &armclk_lock); 283 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 284 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 285 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 286 287 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], 288 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 289 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); 290 291 clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, 292 1, 2); 293 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], 294 "cpu_3or2x_div", CLK_IGNORE_UNUSED, 295 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); 296 297 clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, 298 2 + tmp); 299 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], 300 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 301 26, 0, &armclk_lock); 302 clk_prepare_enable(clks[cpu_2x]); 303 304 clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, 305 4 + 2 * tmp); 306 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], 307 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, 308 0, &armclk_lock); 309 310 /* Timers */ 311 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; 312 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { 313 int idx = of_property_match_string(np, "clock-names", 314 swdt_ext_clk_input_names[i]); 315 if (idx >= 0) 316 swdt_ext_clk_mux_parents[i + 1] = 317 of_clk_get_parent_name(np, idx); 318 else 319 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 320 } 321 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 322 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | 323 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, 324 &swdtclk_lock); 325 326 /* DDR clocks */ 327 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 328 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | 329 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 330 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], 331 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); 332 clk_prepare_enable(clks[ddr2x]); 333 clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, 334 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | 335 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); 336 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], 337 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); 338 clk_prepare_enable(clks[ddr3x]); 339 340 clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, 341 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 342 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); 343 clk = clk_register_divider(NULL, "dci_div1", "dci_div0", 344 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, 345 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 346 &dciclk_lock); 347 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", 348 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, 349 &dciclk_lock); 350 clk_prepare_enable(clks[dci]); 351 352 /* Peripheral clocks */ 353 for (i = fclk0; i <= fclk3; i++) { 354 int enable = !!(fclk_enable & BIT(i - fclk0)); 355 zynq_clk_register_fclk(i, clk_output_name[i], 356 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), 357 periph_parents, enable); 358 } 359 360 zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, 361 SLCR_LQSPI_CLK_CTRL, periph_parents, 0); 362 363 zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, 364 SLCR_SMC_CLK_CTRL, periph_parents, 0); 365 366 zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, 367 SLCR_PCAP_CLK_CTRL, periph_parents, 0); 368 369 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], 370 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, 371 periph_parents, 1); 372 373 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], 374 clk_output_name[uart1], SLCR_UART_CLK_CTRL, 375 periph_parents, 1); 376 377 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], 378 clk_output_name[spi1], SLCR_SPI_CLK_CTRL, 379 periph_parents, 1); 380 381 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { 382 int idx = of_property_match_string(np, "clock-names", 383 gem0_emio_input_names[i]); 384 if (idx >= 0) 385 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 386 idx); 387 } 388 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 389 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, 390 &gem0clk_lock); 391 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 392 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 393 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 394 clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", 395 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 396 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 397 &gem0clk_lock); 398 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 399 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 400 SLCR_GEM0_CLK_CTRL, 6, 1, 0, 401 &gem0clk_lock); 402 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 403 "gem0_emio_mux", CLK_SET_RATE_PARENT, 404 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 405 406 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { 407 int idx = of_property_match_string(np, "clock-names", 408 gem1_emio_input_names[i]); 409 if (idx >= 0) 410 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 411 idx); 412 } 413 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 414 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, 415 &gem1clk_lock); 416 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 417 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 418 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 419 clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", 420 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 421 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 422 &gem1clk_lock); 423 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 424 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 425 SLCR_GEM1_CLK_CTRL, 6, 1, 0, 426 &gem1clk_lock); 427 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 428 "gem1_emio_mux", CLK_SET_RATE_PARENT, 429 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 430 431 tmp = strlen("mio_clk_00x"); 432 clk_name = kmalloc(tmp, GFP_KERNEL); 433 for (i = 0; i < NUM_MIO_PINS; i++) { 434 int idx; 435 436 snprintf(clk_name, tmp, "mio_clk_%2.2d", i); 437 idx = of_property_match_string(np, "clock-names", clk_name); 438 if (idx >= 0) 439 can_mio_mux_parents[i] = of_clk_get_parent_name(np, 440 idx); 441 else 442 can_mio_mux_parents[i] = dummy_nm; 443 } 444 kfree(clk_name); 445 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 446 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, 447 &canclk_lock); 448 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 449 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 450 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 451 clk = clk_register_divider(NULL, "can_div1", "can_div0", 452 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, 453 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 454 &canclk_lock); 455 clk = clk_register_gate(NULL, "can0_gate", "can_div1", 456 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, 457 &canclk_lock); 458 clk = clk_register_gate(NULL, "can1_gate", "can_div1", 459 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 460 &canclk_lock); 461 clk = clk_register_mux(NULL, "can0_mio_mux", 462 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 463 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, 464 &canmioclk_lock); 465 clk = clk_register_mux(NULL, "can1_mio_mux", 466 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | 467 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, 468 0, &canmioclk_lock); 469 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 470 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 471 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, 472 &canmioclk_lock); 473 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 474 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | 475 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, 476 0, &canmioclk_lock); 477 478 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 479 int idx = of_property_match_string(np, "clock-names", 480 dbgtrc_emio_input_names[i]); 481 if (idx >= 0) 482 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 483 idx); 484 } 485 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 486 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, 487 &dbgclk_lock); 488 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 489 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 490 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 491 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 492 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, 493 &dbgclk_lock); 494 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 495 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 496 0, 0, &dbgclk_lock); 497 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], 498 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, 499 &dbgclk_lock); 500 501 /* leave debug clocks in the state the bootloader set them up to */ 502 tmp = readl(SLCR_DBG_CLK_CTRL); 503 if (tmp & DBG_CLK_CTRL_CLKACT_TRC) 504 if (clk_prepare_enable(clks[dbg_trc])) 505 pr_warn("%s: trace clk enable failed\n", __func__); 506 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) 507 if (clk_prepare_enable(clks[dbg_apb])) 508 pr_warn("%s: debug APB clk enable failed\n", __func__); 509 510 /* One gated clock for all APER clocks. */ 511 clks[dma] = clk_register_gate(NULL, clk_output_name[dma], 512 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, 513 &aperclk_lock); 514 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], 515 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, 516 &aperclk_lock); 517 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], 518 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, 519 &aperclk_lock); 520 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], 521 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, 522 &aperclk_lock); 523 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], 524 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, 525 &aperclk_lock); 526 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], 527 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, 528 &aperclk_lock); 529 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], 530 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, 531 &aperclk_lock); 532 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], 533 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, 534 &aperclk_lock); 535 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], 536 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, 537 &aperclk_lock); 538 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], 539 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, 540 &aperclk_lock); 541 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], 542 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, 543 &aperclk_lock); 544 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], 545 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, 546 &aperclk_lock); 547 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], 548 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, 549 &aperclk_lock); 550 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], 551 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, 552 &aperclk_lock); 553 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], 554 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, 555 &aperclk_lock); 556 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], 557 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, 558 &aperclk_lock); 559 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], 560 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, 561 &aperclk_lock); 562 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], 563 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, 564 &aperclk_lock); 565 566 for (i = 0; i < ARRAY_SIZE(clks); i++) { 567 if (IS_ERR(clks[i])) { 568 pr_err("Zynq clk %d: register failed with %ld\n", 569 i, PTR_ERR(clks[i])); 570 BUG(); 571 } 572 } 573 574 clk_data.clks = clks; 575 clk_data.clk_num = ARRAY_SIZE(clks); 576 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 577} 578 579CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); 580 581void __init zynq_clock_init(void) 582{ 583 struct device_node *np; 584 struct device_node *slcr; 585 struct resource res; 586 587 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); 588 if (!np) { 589 pr_err("%s: clkc node not found\n", __func__); 590 goto np_err; 591 } 592 593 if (of_address_to_resource(np, 0, &res)) { 594 pr_err("%pOFn: failed to get resource\n", np); 595 goto np_err; 596 } 597 598 slcr = of_get_parent(np); 599 600 if (slcr->data) { 601 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; 602 } else { 603 pr_err("%pOFn: Unable to get I/O memory\n", np); 604 of_node_put(slcr); 605 goto np_err; 606 } 607 608 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); 609 610 of_node_put(slcr); 611 of_node_put(np); 612 613 return; 614 615np_err: 616 of_node_put(np); 617 BUG(); 618} 619