1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Driver for the ICST307 VCO clock found in the ARM Reference designs. 4 * We wrap the custom interface from <asm/hardware/icst.h> into the generic 5 * clock framework. 6 * 7 * Copyright (C) 2012-2015 Linus Walleij 8 * 9 * TODO: when all ARM reference designs are migrated to generic clocks, the 10 * ICST clock code from the ARM tree should probably be merged into this 11 * file. 12 */ 13#include <linux/kernel.h> 14#include <linux/slab.h> 15#include <linux/export.h> 16#include <linux/err.h> 17#include <linux/clk-provider.h> 18#include <linux/io.h> 19#include <linux/regmap.h> 20#include <linux/mfd/syscon.h> 21 22#include "icst.h" 23#include "clk-icst.h" 24 25/* Magic unlocking token used on all Versatile boards */ 26#define VERSATILE_LOCK_VAL 0xA05F 27 28#define VERSATILE_AUX_OSC_BITS 0x7FFFF 29#define INTEGRATOR_AP_CM_BITS 0xFF 30#define INTEGRATOR_AP_SYS_BITS 0xFF 31#define INTEGRATOR_CP_CM_CORE_BITS 0x7FF 32#define INTEGRATOR_CP_CM_MEM_BITS 0x7FF000 33 34#define INTEGRATOR_AP_PCI_25_33_MHZ BIT(8) 35 36/** 37 * struct clk_icst - ICST VCO clock wrapper 38 * @hw: corresponding clock hardware entry 39 * @vcoreg: VCO register address 40 * @lockreg: VCO lock register address 41 * @params: parameters for this ICST instance 42 * @rate: current rate 43 * @ctype: the type of control register for the ICST 44 */ 45struct clk_icst { 46 struct clk_hw hw; 47 struct regmap *map; 48 u32 vcoreg_off; 49 u32 lockreg_off; 50 struct icst_params *params; 51 unsigned long rate; 52 enum icst_control_type ctype; 53}; 54 55#define to_icst(_hw) container_of(_hw, struct clk_icst, hw) 56 57/** 58 * vco_get() - get ICST VCO settings from a certain ICST 59 * @icst: the ICST clock to get 60 * @vco: the VCO struct to return the value in 61 */ 62static int vco_get(struct clk_icst *icst, struct icst_vco *vco) 63{ 64 u32 val; 65 int ret; 66 67 ret = regmap_read(icst->map, icst->vcoreg_off, &val); 68 if (ret) 69 return ret; 70 71 /* 72 * The Integrator/AP core clock can only access the low eight 73 * bits of the v PLL divider. Bit 8 is tied low and always zero, 74 * r is hardwired to 22 and output divider s is hardwired to 1 75 * (divide by 2) according to the document 76 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and 77 * CM1136JF-S User Guide" ARM DUI 0138E, page 3-13 thru 3-14. 78 */ 79 if (icst->ctype == ICST_INTEGRATOR_AP_CM) { 80 vco->v = val & INTEGRATOR_AP_CM_BITS; 81 vco->r = 22; 82 vco->s = 1; 83 return 0; 84 } 85 86 /* 87 * The Integrator/AP system clock on the base board can only 88 * access the low eight bits of the v PLL divider. Bit 8 is tied low 89 * and always zero, r is hardwired to 46, and the output divider is 90 * hardwired to 3 (divide by 4) according to the document 91 * "Integrator AP ASIC Development Motherboard" ARM DUI 0098B, 92 * page 3-16. 93 */ 94 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { 95 vco->v = val & INTEGRATOR_AP_SYS_BITS; 96 vco->r = 46; 97 vco->s = 3; 98 return 0; 99 } 100 101 /* 102 * The Integrator/AP PCI clock is using an odd pattern to create 103 * the child clock, basically a single bit called DIVX/Y is used 104 * to select between two different hardwired values: setting the 105 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the 106 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies 107 * 33 or 25 MHz respectively. 108 */ 109 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 110 bool divxy = !!(val & INTEGRATOR_AP_PCI_25_33_MHZ); 111 112 vco->v = divxy ? 17 : 14; 113 vco->r = divxy ? 22 : 14; 114 vco->s = 1; 115 return 0; 116 } 117 118 /* 119 * The Integrator/CP core clock can access the low eight bits 120 * of the v PLL divider. Bit 8 is tied low and always zero, 121 * r is hardwired to 22 and the output divider s is accessible 122 * in bits 8 thru 10 according to the document 123 * "Integrator/CM940T, CM920T, CM740T, and CM720T User Guide" 124 * ARM DUI 0157A, page 3-20 thru 3-23 and 4-10. 125 */ 126 if (icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { 127 vco->v = val & 0xFF; 128 vco->r = 22; 129 vco->s = (val >> 8) & 7; 130 return 0; 131 } 132 133 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { 134 vco->v = (val >> 12) & 0xFF; 135 vco->r = 22; 136 vco->s = (val >> 20) & 7; 137 return 0; 138 } 139 140 vco->v = val & 0x1ff; 141 vco->r = (val >> 9) & 0x7f; 142 vco->s = (val >> 16) & 03; 143 return 0; 144} 145 146/** 147 * vco_set() - commit changes to an ICST VCO 148 * @icst: the ICST clock to set 149 * @vco: the VCO struct to set the changes from 150 */ 151static int vco_set(struct clk_icst *icst, struct icst_vco vco) 152{ 153 u32 mask; 154 u32 val; 155 int ret; 156 157 /* Mask the bits used by the VCO */ 158 switch (icst->ctype) { 159 case ICST_INTEGRATOR_AP_CM: 160 mask = INTEGRATOR_AP_CM_BITS; 161 val = vco.v & 0xFF; 162 if (vco.v & 0x100) 163 pr_err("ICST error: tried to set bit 8 of VDW\n"); 164 if (vco.s != 1) 165 pr_err("ICST error: tried to use VOD != 1\n"); 166 if (vco.r != 22) 167 pr_err("ICST error: tried to use RDW != 22\n"); 168 break; 169 case ICST_INTEGRATOR_AP_SYS: 170 mask = INTEGRATOR_AP_SYS_BITS; 171 val = vco.v & 0xFF; 172 if (vco.v & 0x100) 173 pr_err("ICST error: tried to set bit 8 of VDW\n"); 174 if (vco.s != 3) 175 pr_err("ICST error: tried to use VOD != 1\n"); 176 if (vco.r != 46) 177 pr_err("ICST error: tried to use RDW != 22\n"); 178 break; 179 case ICST_INTEGRATOR_CP_CM_CORE: 180 mask = INTEGRATOR_CP_CM_CORE_BITS; /* Uses 12 bits */ 181 val = (vco.v & 0xFF) | vco.s << 8; 182 if (vco.v & 0x100) 183 pr_err("ICST error: tried to set bit 8 of VDW\n"); 184 if (vco.r != 22) 185 pr_err("ICST error: tried to use RDW != 22\n"); 186 break; 187 case ICST_INTEGRATOR_CP_CM_MEM: 188 mask = INTEGRATOR_CP_CM_MEM_BITS; /* Uses 12 bits */ 189 val = ((vco.v & 0xFF) << 12) | (vco.s << 20); 190 if (vco.v & 0x100) 191 pr_err("ICST error: tried to set bit 8 of VDW\n"); 192 if (vco.r != 22) 193 pr_err("ICST error: tried to use RDW != 22\n"); 194 break; 195 default: 196 /* Regular auxilary oscillator */ 197 mask = VERSATILE_AUX_OSC_BITS; 198 val = vco.v | (vco.r << 9) | (vco.s << 16); 199 break; 200 } 201 202 pr_debug("ICST: new val = 0x%08x\n", val); 203 204 /* This magic unlocks the VCO so it can be controlled */ 205 ret = regmap_write(icst->map, icst->lockreg_off, VERSATILE_LOCK_VAL); 206 if (ret) 207 return ret; 208 ret = regmap_update_bits(icst->map, icst->vcoreg_off, mask, val); 209 if (ret) 210 return ret; 211 /* This locks the VCO again */ 212 ret = regmap_write(icst->map, icst->lockreg_off, 0); 213 if (ret) 214 return ret; 215 return 0; 216} 217 218static unsigned long icst_recalc_rate(struct clk_hw *hw, 219 unsigned long parent_rate) 220{ 221 struct clk_icst *icst = to_icst(hw); 222 struct icst_vco vco; 223 int ret; 224 225 if (parent_rate) 226 icst->params->ref = parent_rate; 227 ret = vco_get(icst, &vco); 228 if (ret) { 229 pr_err("ICST: could not get VCO setting\n"); 230 return 0; 231 } 232 icst->rate = icst_hz(icst->params, vco); 233 return icst->rate; 234} 235 236static long icst_round_rate(struct clk_hw *hw, unsigned long rate, 237 unsigned long *prate) 238{ 239 struct clk_icst *icst = to_icst(hw); 240 struct icst_vco vco; 241 242 if (icst->ctype == ICST_INTEGRATOR_AP_CM || 243 icst->ctype == ICST_INTEGRATOR_CP_CM_CORE) { 244 if (rate <= 12000000) 245 return 12000000; 246 if (rate >= 160000000) 247 return 160000000; 248 /* Slam to closest megahertz */ 249 return DIV_ROUND_CLOSEST(rate, 1000000) * 1000000; 250 } 251 252 if (icst->ctype == ICST_INTEGRATOR_CP_CM_MEM) { 253 if (rate <= 6000000) 254 return 6000000; 255 if (rate >= 66000000) 256 return 66000000; 257 /* Slam to closest 0.5 megahertz */ 258 return DIV_ROUND_CLOSEST(rate, 500000) * 500000; 259 } 260 261 if (icst->ctype == ICST_INTEGRATOR_AP_SYS) { 262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ 263 if (rate <= 3000000) 264 return 3000000; 265 if (rate >= 50000000) 266 return 5000000; 267 /* Slam to closest 0.25 MHz */ 268 return DIV_ROUND_CLOSEST(rate, 250000) * 250000; 269 } 270 271 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 272 /* 273 * If we're below or less than halfway from 25 to 33 MHz 274 * select 25 MHz 275 */ 276 if (rate <= 25000000 || rate < 29000000) 277 return 25000000; 278 /* Else just return the default frequency */ 279 return 33000000; 280 } 281 282 vco = icst_hz_to_vco(icst->params, rate); 283 return icst_hz(icst->params, vco); 284} 285 286static int icst_set_rate(struct clk_hw *hw, unsigned long rate, 287 unsigned long parent_rate) 288{ 289 struct clk_icst *icst = to_icst(hw); 290 struct icst_vco vco; 291 292 if (icst->ctype == ICST_INTEGRATOR_AP_PCI) { 293 /* This clock is especially primitive */ 294 unsigned int val; 295 int ret; 296 297 if (rate == 25000000) { 298 val = 0; 299 } else if (rate == 33000000) { 300 val = INTEGRATOR_AP_PCI_25_33_MHZ; 301 } else { 302 pr_err("ICST: cannot set PCI frequency %lu\n", 303 rate); 304 return -EINVAL; 305 } 306 ret = regmap_write(icst->map, icst->lockreg_off, 307 VERSATILE_LOCK_VAL); 308 if (ret) 309 return ret; 310 ret = regmap_update_bits(icst->map, icst->vcoreg_off, 311 INTEGRATOR_AP_PCI_25_33_MHZ, 312 val); 313 if (ret) 314 return ret; 315 /* This locks the VCO again */ 316 ret = regmap_write(icst->map, icst->lockreg_off, 0); 317 if (ret) 318 return ret; 319 return 0; 320 } 321 322 if (parent_rate) 323 icst->params->ref = parent_rate; 324 vco = icst_hz_to_vco(icst->params, rate); 325 icst->rate = icst_hz(icst->params, vco); 326 return vco_set(icst, vco); 327} 328 329static const struct clk_ops icst_ops = { 330 .recalc_rate = icst_recalc_rate, 331 .round_rate = icst_round_rate, 332 .set_rate = icst_set_rate, 333}; 334 335struct clk *icst_clk_setup(struct device *dev, 336 const struct clk_icst_desc *desc, 337 const char *name, 338 const char *parent_name, 339 struct regmap *map, 340 enum icst_control_type ctype) 341{ 342 struct clk *clk; 343 struct clk_icst *icst; 344 struct clk_init_data init; 345 struct icst_params *pclone; 346 347 icst = kzalloc(sizeof(*icst), GFP_KERNEL); 348 if (!icst) 349 return ERR_PTR(-ENOMEM); 350 351 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL); 352 if (!pclone) { 353 kfree(icst); 354 return ERR_PTR(-ENOMEM); 355 } 356 357 init.name = name; 358 init.ops = &icst_ops; 359 init.flags = 0; 360 init.parent_names = (parent_name ? &parent_name : NULL); 361 init.num_parents = (parent_name ? 1 : 0); 362 icst->map = map; 363 icst->hw.init = &init; 364 icst->params = pclone; 365 icst->vcoreg_off = desc->vco_offset; 366 icst->lockreg_off = desc->lock_offset; 367 icst->ctype = ctype; 368 369 clk = clk_register(dev, &icst->hw); 370 if (IS_ERR(clk)) { 371 kfree(pclone); 372 kfree(icst); 373 } 374 375 return clk; 376} 377EXPORT_SYMBOL_GPL(icst_clk_setup); 378 379struct clk *icst_clk_register(struct device *dev, 380 const struct clk_icst_desc *desc, 381 const char *name, 382 const char *parent_name, 383 void __iomem *base) 384{ 385 struct regmap_config icst_regmap_conf = { 386 .reg_bits = 32, 387 .val_bits = 32, 388 .reg_stride = 4, 389 }; 390 struct regmap *map; 391 392 map = regmap_init_mmio(dev, base, &icst_regmap_conf); 393 if (IS_ERR(map)) { 394 pr_err("could not initialize ICST regmap\n"); 395 return ERR_CAST(map); 396 } 397 return icst_clk_setup(dev, desc, name, parent_name, map, 398 ICST_VERSATILE); 399} 400EXPORT_SYMBOL_GPL(icst_clk_register); 401 402#ifdef CONFIG_OF 403/* 404 * In a device tree, an memory-mapped ICST clock appear as a child 405 * of a syscon node. Assume this and probe it only as a child of a 406 * syscon. 407 */ 408 409static const struct icst_params icst525_params = { 410 .vco_max = ICST525_VCO_MAX_5V, 411 .vco_min = ICST525_VCO_MIN, 412 .vd_min = 8, 413 .vd_max = 263, 414 .rd_min = 3, 415 .rd_max = 65, 416 .s2div = icst525_s2div, 417 .idx2s = icst525_idx2s, 418}; 419 420static const struct icst_params icst307_params = { 421 .vco_max = ICST307_VCO_MAX, 422 .vco_min = ICST307_VCO_MIN, 423 .vd_min = 4 + 8, 424 .vd_max = 511 + 8, 425 .rd_min = 1 + 2, 426 .rd_max = 127 + 2, 427 .s2div = icst307_s2div, 428 .idx2s = icst307_idx2s, 429}; 430 431/** 432 * The core modules on the Integrator/AP and Integrator/CP have 433 * especially crippled ICST525 control. 434 */ 435static const struct icst_params icst525_apcp_cm_params = { 436 .vco_max = ICST525_VCO_MAX_5V, 437 .vco_min = ICST525_VCO_MIN, 438 /* Minimum 12 MHz, VDW = 4 */ 439 .vd_min = 12, 440 /* 441 * Maximum 160 MHz, VDW = 152 for all core modules, but 442 * CM926EJ-S, CM1026EJ-S and CM1136JF-S can actually 443 * go to 200 MHz (max VDW = 192). 444 */ 445 .vd_max = 192, 446 /* r is hardcoded to 22 and this is the actual divisor, +2 */ 447 .rd_min = 24, 448 .rd_max = 24, 449 .s2div = icst525_s2div, 450 .idx2s = icst525_idx2s, 451}; 452 453static const struct icst_params icst525_ap_sys_params = { 454 .vco_max = ICST525_VCO_MAX_5V, 455 .vco_min = ICST525_VCO_MIN, 456 /* Minimum 3 MHz, VDW = 4 */ 457 .vd_min = 3, 458 /* Maximum 50 MHz, VDW = 192 */ 459 .vd_max = 50, 460 /* r is hardcoded to 46 and this is the actual divisor, +2 */ 461 .rd_min = 48, 462 .rd_max = 48, 463 .s2div = icst525_s2div, 464 .idx2s = icst525_idx2s, 465}; 466 467static const struct icst_params icst525_ap_pci_params = { 468 .vco_max = ICST525_VCO_MAX_5V, 469 .vco_min = ICST525_VCO_MIN, 470 /* Minimum 25 MHz */ 471 .vd_min = 25, 472 /* Maximum 33 MHz */ 473 .vd_max = 33, 474 /* r is hardcoded to 14 or 22 and this is the actual divisors +2 */ 475 .rd_min = 16, 476 .rd_max = 24, 477 .s2div = icst525_s2div, 478 .idx2s = icst525_idx2s, 479}; 480 481static void __init of_syscon_icst_setup(struct device_node *np) 482{ 483 struct device_node *parent; 484 struct regmap *map; 485 struct clk_icst_desc icst_desc; 486 const char *name = np->name; 487 const char *parent_name; 488 struct clk *regclk; 489 enum icst_control_type ctype; 490 491 /* We do not release this reference, we are using it perpetually */ 492 parent = of_get_parent(np); 493 if (!parent) { 494 pr_err("no parent node for syscon ICST clock\n"); 495 return; 496 } 497 map = syscon_node_to_regmap(parent); 498 if (IS_ERR(map)) { 499 pr_err("no regmap for syscon ICST clock parent\n"); 500 return; 501 } 502 503 if (of_property_read_u32(np, "vco-offset", &icst_desc.vco_offset)) { 504 pr_err("no VCO register offset for ICST clock\n"); 505 return; 506 } 507 if (of_property_read_u32(np, "lock-offset", &icst_desc.lock_offset)) { 508 pr_err("no lock register offset for ICST clock\n"); 509 return; 510 } 511 512 if (of_device_is_compatible(np, "arm,syscon-icst525")) { 513 icst_desc.params = &icst525_params; 514 ctype = ICST_VERSATILE; 515 } else if (of_device_is_compatible(np, "arm,syscon-icst307")) { 516 icst_desc.params = &icst307_params; 517 ctype = ICST_VERSATILE; 518 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-cm")) { 519 icst_desc.params = &icst525_apcp_cm_params; 520 ctype = ICST_INTEGRATOR_AP_CM; 521 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-sys")) { 522 icst_desc.params = &icst525_ap_sys_params; 523 ctype = ICST_INTEGRATOR_AP_SYS; 524 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorap-pci")) { 525 icst_desc.params = &icst525_ap_pci_params; 526 ctype = ICST_INTEGRATOR_AP_PCI; 527 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-core")) { 528 icst_desc.params = &icst525_apcp_cm_params; 529 ctype = ICST_INTEGRATOR_CP_CM_CORE; 530 } else if (of_device_is_compatible(np, "arm,syscon-icst525-integratorcp-cm-mem")) { 531 icst_desc.params = &icst525_apcp_cm_params; 532 ctype = ICST_INTEGRATOR_CP_CM_MEM; 533 } else { 534 pr_err("unknown ICST clock %s\n", name); 535 return; 536 } 537 538 /* Parent clock name is not the same as node parent */ 539 parent_name = of_clk_get_parent_name(np, 0); 540 541 regclk = icst_clk_setup(NULL, &icst_desc, name, parent_name, map, ctype); 542 if (IS_ERR(regclk)) { 543 pr_err("error setting up syscon ICST clock %s\n", name); 544 return; 545 } 546 of_clk_add_provider(np, of_clk_src_simple_get, regclk); 547 pr_debug("registered syscon ICST clock %s\n", name); 548} 549 550CLK_OF_DECLARE(arm_syscon_icst525_clk, 551 "arm,syscon-icst525", of_syscon_icst_setup); 552CLK_OF_DECLARE(arm_syscon_icst307_clk, 553 "arm,syscon-icst307", of_syscon_icst_setup); 554CLK_OF_DECLARE(arm_syscon_integratorap_cm_clk, 555 "arm,syscon-icst525-integratorap-cm", of_syscon_icst_setup); 556CLK_OF_DECLARE(arm_syscon_integratorap_sys_clk, 557 "arm,syscon-icst525-integratorap-sys", of_syscon_icst_setup); 558CLK_OF_DECLARE(arm_syscon_integratorap_pci_clk, 559 "arm,syscon-icst525-integratorap-pci", of_syscon_icst_setup); 560CLK_OF_DECLARE(arm_syscon_integratorcp_cm_core_clk, 561 "arm,syscon-icst525-integratorcp-cm-core", of_syscon_icst_setup); 562CLK_OF_DECLARE(arm_syscon_integratorcp_cm_mem_clk, 563 "arm,syscon-icst525-integratorcp-cm-mem", of_syscon_icst_setup); 564#endif 565