1/* 2 * TI Clock driver internal definitions 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc 5 * Tero Kristo (t-kristo@ti.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16#ifndef __DRIVERS_CLK_TI_CLOCK__ 17#define __DRIVERS_CLK_TI_CLOCK__ 18 19struct clk_omap_divider { 20 struct clk_hw hw; 21 struct clk_omap_reg reg; 22 u8 shift; 23 u8 flags; 24 s8 latch; 25 u16 min; 26 u16 max; 27 u16 mask; 28 const struct clk_div_table *table; 29 u32 context; 30}; 31 32#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw) 33 34struct clk_omap_mux { 35 struct clk_hw hw; 36 struct clk_omap_reg reg; 37 u32 *table; 38 u32 mask; 39 u8 shift; 40 s8 latch; 41 u8 flags; 42 u8 saved_parent; 43}; 44 45#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw) 46 47enum { 48 TI_CLK_FIXED, 49 TI_CLK_MUX, 50 TI_CLK_DIVIDER, 51 TI_CLK_COMPOSITE, 52 TI_CLK_FIXED_FACTOR, 53 TI_CLK_GATE, 54 TI_CLK_DPLL, 55}; 56 57/* Global flags */ 58#define CLKF_INDEX_POWER_OF_TWO (1 << 0) 59#define CLKF_INDEX_STARTS_AT_ONE (1 << 1) 60#define CLKF_SET_RATE_PARENT (1 << 2) 61#define CLKF_OMAP3 (1 << 3) 62#define CLKF_AM35XX (1 << 4) 63 64/* Gate flags */ 65#define CLKF_SET_BIT_TO_DISABLE (1 << 5) 66#define CLKF_INTERFACE (1 << 6) 67#define CLKF_SSI (1 << 7) 68#define CLKF_DSS (1 << 8) 69#define CLKF_HSOTGUSB (1 << 9) 70#define CLKF_WAIT (1 << 10) 71#define CLKF_NO_WAIT (1 << 11) 72#define CLKF_HSDIV (1 << 12) 73#define CLKF_CLKDM (1 << 13) 74 75/* DPLL flags */ 76#define CLKF_LOW_POWER_STOP (1 << 5) 77#define CLKF_LOCK (1 << 6) 78#define CLKF_LOW_POWER_BYPASS (1 << 7) 79#define CLKF_PER (1 << 8) 80#define CLKF_CORE (1 << 9) 81#define CLKF_J_TYPE (1 << 10) 82 83/* CLKCTRL flags */ 84#define CLKF_SW_SUP BIT(5) 85#define CLKF_HW_SUP BIT(6) 86#define CLKF_NO_IDLEST BIT(7) 87 88#define CLKF_SOC_MASK GENMASK(11, 8) 89 90#define CLKF_SOC_NONSEC BIT(8) 91#define CLKF_SOC_DRA72 BIT(9) 92#define CLKF_SOC_DRA74 BIT(10) 93#define CLKF_SOC_DRA76 BIT(11) 94 95#define CLK(dev, con, ck) \ 96 { \ 97 .lk = { \ 98 .dev_id = dev, \ 99 .con_id = con, \ 100 }, \ 101 .clk = ck, \ 102 } 103 104struct ti_clk { 105 const char *name; 106 const char *clkdm_name; 107 int type; 108 void *data; 109 struct ti_clk *patch; 110 struct clk *clk; 111}; 112 113struct ti_clk_mux { 114 u8 bit_shift; 115 int num_parents; 116 u16 reg; 117 u8 module; 118 const char * const *parents; 119 u16 flags; 120}; 121 122struct ti_clk_divider { 123 const char *parent; 124 u8 bit_shift; 125 u16 max_div; 126 u16 reg; 127 u8 module; 128 int *dividers; 129 int num_dividers; 130 u16 flags; 131}; 132 133struct ti_clk_gate { 134 const char *parent; 135 u8 bit_shift; 136 u16 reg; 137 u8 module; 138 u16 flags; 139}; 140 141/* Composite clock component types */ 142enum { 143 CLK_COMPONENT_TYPE_GATE = 0, 144 CLK_COMPONENT_TYPE_DIVIDER, 145 CLK_COMPONENT_TYPE_MUX, 146 CLK_COMPONENT_TYPE_MAX, 147}; 148 149/** 150 * struct ti_dt_clk - OMAP DT clock alias declarations 151 * @lk: clock lookup definition 152 * @node_name: clock DT node to map to 153 */ 154struct ti_dt_clk { 155 struct clk_lookup lk; 156 char *node_name; 157}; 158 159#define DT_CLK(dev, con, name) \ 160 { \ 161 .lk = { \ 162 .dev_id = dev, \ 163 .con_id = con, \ 164 }, \ 165 .node_name = name, \ 166 } 167 168/* CLKCTRL type definitions */ 169struct omap_clkctrl_div_data { 170 const int *dividers; 171 int max_div; 172 u32 flags; 173}; 174 175struct omap_clkctrl_bit_data { 176 u8 bit; 177 u8 type; 178 const char * const *parents; 179 const void *data; 180}; 181 182struct omap_clkctrl_reg_data { 183 u16 offset; 184 const struct omap_clkctrl_bit_data *bit_data; 185 u16 flags; 186 const char *parent; 187 const char *clkdm_name; 188}; 189 190struct omap_clkctrl_data { 191 u32 addr; 192 const struct omap_clkctrl_reg_data *regs; 193}; 194 195extern const struct omap_clkctrl_data omap4_clkctrl_data[]; 196extern const struct omap_clkctrl_data omap5_clkctrl_data[]; 197extern const struct omap_clkctrl_data dra7_clkctrl_data[]; 198extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[]; 199extern struct ti_dt_clk dra7xx_compat_clks[]; 200extern const struct omap_clkctrl_data am3_clkctrl_data[]; 201extern const struct omap_clkctrl_data am3_clkctrl_compat_data[]; 202extern struct ti_dt_clk am33xx_compat_clks[]; 203extern const struct omap_clkctrl_data am4_clkctrl_data[]; 204extern const struct omap_clkctrl_data am4_clkctrl_compat_data[]; 205extern struct ti_dt_clk am43xx_compat_clks[]; 206extern const struct omap_clkctrl_data am438x_clkctrl_data[]; 207extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[]; 208extern const struct omap_clkctrl_data dm814_clkctrl_data[]; 209extern const struct omap_clkctrl_data dm816_clkctrl_data[]; 210 211typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); 212 213struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw, 214 const char *con); 215struct clk *of_ti_clk_register_omap_hw(struct device_node *node, 216 struct clk_hw *hw, const char *con); 217const char *ti_dt_clk_name(struct device_node *np); 218int ti_clk_add_alias(struct clk *clk, const char *con); 219void ti_clk_add_aliases(void); 220 221void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); 222 223struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 224 225int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, 226 u8 flags, struct clk_omap_divider *div); 227 228int ti_clk_get_reg_addr(struct device_node *node, int index, 229 struct clk_omap_reg *reg); 230void ti_dt_clocks_register(struct ti_dt_clk *oclks); 231int ti_clk_retry_init(struct device_node *node, void *user, 232 ti_of_clk_init_cb_t func); 233int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type); 234 235int of_ti_clk_autoidle_setup(struct device_node *node); 236void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks); 237 238extern const struct clk_hw_omap_ops clkhwops_omap3_dpll; 239extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx; 240extern const struct clk_hw_omap_ops clkhwops_wait; 241extern const struct clk_hw_omap_ops clkhwops_iclk; 242extern const struct clk_hw_omap_ops clkhwops_iclk_wait; 243extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; 244extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait; 245extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait; 246extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait; 247extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait; 248extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait; 249extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait; 250 251extern const struct clk_ops ti_clk_divider_ops; 252extern const struct clk_ops ti_clk_mux_ops; 253extern const struct clk_ops omap_gate_clk_ops; 254 255extern struct ti_clk_features ti_clk_features; 256 257int omap2_init_clk_clkdm(struct clk_hw *hw); 258int omap2_clkops_enable_clkdm(struct clk_hw *hw); 259void omap2_clkops_disable_clkdm(struct clk_hw *hw); 260 261int omap2_dflt_clk_enable(struct clk_hw *hw); 262void omap2_dflt_clk_disable(struct clk_hw *hw); 263int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 264void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 265 struct clk_omap_reg *other_reg, 266 u8 *other_bit); 267void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 268 struct clk_omap_reg *idlest_reg, 269 u8 *idlest_bit, u8 *idlest_val); 270 271void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 272void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk); 273 274u8 omap2_init_dpll_parent(struct clk_hw *hw); 275int omap3_noncore_dpll_enable(struct clk_hw *hw); 276void omap3_noncore_dpll_disable(struct clk_hw *hw); 277int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index); 278int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, 279 unsigned long parent_rate); 280int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, 281 unsigned long rate, 282 unsigned long parent_rate, 283 u8 index); 284int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, 285 struct clk_rate_request *req); 286long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, 287 unsigned long *parent_rate); 288unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw, 289 unsigned long parent_rate); 290 291/* 292 * OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks 293 * that are sourced by DPLL5, and both of these require this clock 294 * to be at 120 MHz for proper operation. 295 */ 296#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000 297 298unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); 299int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate, 300 unsigned long parent_rate); 301int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, 302 unsigned long parent_rate, u8 index); 303int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate, 304 unsigned long parent_rate); 305void omap3_clk_lock_dpll5(void); 306 307unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, 308 unsigned long parent_rate); 309long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, 310 unsigned long target_rate, 311 unsigned long *parent_rate); 312int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, 313 struct clk_rate_request *req); 314int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw)); 315 316extern struct ti_clk_ll_ops *ti_clk_ll_ops; 317 318#endif 319