1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * OMAP5 Clock init 4 * 5 * Copyright (C) 2013 Texas Instruments, Inc. 6 * 7 * Tero Kristo (t-kristo@ti.com) 8 */ 9 10#include <linux/kernel.h> 11#include <linux/list.h> 12#include <linux/clk.h> 13#include <linux/clkdev.h> 14#include <linux/io.h> 15#include <linux/clk/ti.h> 16#include <dt-bindings/clock/omap5.h> 17 18#include "clock.h" 19 20#define OMAP5_DPLL_ABE_DEFFREQ 98304000 21 22/* 23 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings" 24 * states it must be at 960MHz 25 */ 26#define OMAP5_DPLL_USB_DEFFREQ 960000000 27 28static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = { 29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" }, 30 { 0 }, 31}; 32 33static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = { 34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" }, 35 { 0 }, 36}; 37 38static const char * const omap5_aess_fclk_parents[] __initconst = { 39 "abe_clk", 40 NULL, 41}; 42 43static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = { 44 .max_div = 2, 45}; 46 47static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = { 48 { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data }, 49 { 0 }, 50}; 51 52static const char * const omap5_dmic_gfclk_parents[] __initconst = { 53 "abe_cm:clk:0018:26", 54 "pad_clks_ck", 55 "slimbus_clk", 56 NULL, 57}; 58 59static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = { 60 "abe_24m_fclk", 61 "dss_syc_gfclk_div", 62 "func_24m_clk", 63 NULL, 64}; 65 66static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = { 67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL }, 68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 69 { 0 }, 70}; 71 72static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = { 73 "abe_cm:clk:0028:26", 74 "pad_clks_ck", 75 "slimbus_clk", 76 NULL, 77}; 78 79static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = { 80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL }, 81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 82 { 0 }, 83}; 84 85static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = { 86 "abe_cm:clk:0030:26", 87 "pad_clks_ck", 88 "slimbus_clk", 89 NULL, 90}; 91 92static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = { 93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL }, 94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 95 { 0 }, 96}; 97 98static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = { 99 "abe_cm:clk:0038:26", 100 "pad_clks_ck", 101 "slimbus_clk", 102 NULL, 103}; 104 105static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = { 106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL }, 107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL }, 108 { 0 }, 109}; 110 111static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = { 112 "dss_syc_gfclk_div", 113 "sys_32k_ck", 114 NULL, 115}; 116 117static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = { 118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 119 { 0 }, 120}; 121 122static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = { 123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 124 { 0 }, 125}; 126 127static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = { 128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 129 { 0 }, 130}; 131 132static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = { 133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL }, 134 { 0 }, 135}; 136 137static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = { 138 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" }, 139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" }, 140 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" }, 141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" }, 142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" }, 143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" }, 144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" }, 145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" }, 146 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" }, 147 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" }, 148 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" }, 149 { 0 }, 150}; 151 152static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = { 153 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" }, 154 { 0 }, 155}; 156 157static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = { 158 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" }, 159 { 0 }, 160}; 161 162static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = { 163 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" }, 164 { 0 }, 165}; 166 167static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = { 168 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 169 { 0 }, 170}; 171 172static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = { 173 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" }, 174 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 175 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" }, 176 { 0 }, 177}; 178 179static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = { 180 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 181 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 182 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 183 { 0 }, 184}; 185 186static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = { 187 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 188 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 189 { 0 }, 190}; 191 192static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = { 193 "sys_clkin", 194 "sys_32k_ck", 195 NULL, 196}; 197 198static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = { 199 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 200 { 0 }, 201}; 202 203static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = { 204 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 205 { 0 }, 206}; 207 208static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = { 209 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 210 { 0 }, 211}; 212 213static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = { 214 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 215 { 0 }, 216}; 217 218static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = { 219 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 220 { 0 }, 221}; 222 223static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = { 224 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 225 { 0 }, 226}; 227 228static const char * const omap5_gpio2_dbclk_parents[] __initconst = { 229 "sys_32k_ck", 230 NULL, 231}; 232 233static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = { 234 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 235 { 0 }, 236}; 237 238static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = { 239 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 240 { 0 }, 241}; 242 243static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = { 244 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 245 { 0 }, 246}; 247 248static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = { 249 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 250 { 0 }, 251}; 252 253static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = { 254 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 255 { 0 }, 256}; 257 258static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = { 259 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 260 { 0 }, 261}; 262 263static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = { 264 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 265 { 0 }, 266}; 267 268static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = { 269 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" }, 270 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" }, 271 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" }, 272 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" }, 273 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" }, 274 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" }, 275 { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 276 { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 277 { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 278 { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 279 { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 280 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 281 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 282 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 283 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 284 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" }, 285 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 286 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 287 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 288 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 289 { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 290 { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 291 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 292 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 293 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 294 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 295 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 296 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 297 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 298 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" }, 299 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 300 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" }, 301 { 0 }, 302}; 303 304static const struct 305omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = { 306 { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 307 { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 308 { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 309 { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" }, 310 { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" }, 311 { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" }, 312 { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" }, 313 { 0 }, 314}; 315 316static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = { 317 { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, 318 { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" }, 319 { 0 }, 320}; 321 322static const char * const omap5_dss_dss_clk_parents[] __initconst = { 323 "dpll_per_h12x2_ck", 324 NULL, 325}; 326 327static const char * const omap5_dss_48mhz_clk_parents[] __initconst = { 328 "func_48m_fclk", 329 NULL, 330}; 331 332static const char * const omap5_dss_sys_clk_parents[] __initconst = { 333 "dss_syc_gfclk_div", 334 NULL, 335}; 336 337static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = { 338 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL }, 339 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL }, 340 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL }, 341 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 342 { 0 }, 343}; 344 345static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = { 346 { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" }, 347 { 0 }, 348}; 349 350static const char * const omap5_gpu_core_mux_parents[] __initconst = { 351 "dpll_core_h14x2_ck", 352 "dpll_per_h14x2_ck", 353 NULL, 354}; 355 356static const char * const omap5_gpu_hyd_mux_parents[] __initconst = { 357 "dpll_core_h14x2_ck", 358 "dpll_per_h14x2_ck", 359 NULL, 360}; 361 362static const char * const omap5_gpu_sys_clk_parents[] __initconst = { 363 "sys_clkin", 364 NULL, 365}; 366 367static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = { 368 .max_div = 2, 369}; 370 371static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = { 372 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL }, 373 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL }, 374 { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data }, 375 { 0 }, 376}; 377 378static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = { 379 { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" }, 380 { 0 }, 381}; 382 383static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = { 384 "func_128m_clk", 385 "dpll_per_m2x2_ck", 386 NULL, 387}; 388 389static const char * const omap5_mmc1_fclk_parents[] __initconst = { 390 "l3init_cm:clk:0008:24", 391 NULL, 392}; 393 394static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = { 395 .max_div = 2, 396}; 397 398static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = { 399 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 400 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 401 { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data }, 402 { 0 }, 403}; 404 405static const char * const omap5_mmc2_fclk_parents[] __initconst = { 406 "l3init_cm:clk:0010:24", 407 NULL, 408}; 409 410static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = { 411 .max_div = 2, 412}; 413 414static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = { 415 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL }, 416 { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data }, 417 { 0 }, 418}; 419 420static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = { 421 "l3init_60m_fclk", 422 NULL, 423}; 424 425static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = { 426 "dpll_usb_m2_ck", 427 NULL, 428}; 429 430static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = { 431 "l3init_cm:clk:0038:24", 432 NULL, 433}; 434 435static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = { 436 "l3init_cm:clk:0038:25", 437 NULL, 438}; 439 440static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = { 441 "l3init_60m_fclk", 442 "xclk60mhsp1_ck", 443 NULL, 444}; 445 446static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = { 447 "l3init_60m_fclk", 448 "xclk60mhsp2_ck", 449 NULL, 450}; 451 452static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = { 453 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 454 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 455 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL }, 456 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL }, 457 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 458 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 459 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 460 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 461 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL }, 462 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL }, 463 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL }, 464 { 0 }, 465}; 466 467static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = { 468 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 469 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 470 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL }, 471 { 0 }, 472}; 473 474static const char * const omap5_sata_ref_clk_parents[] __initconst = { 475 "sys_clkin", 476 NULL, 477}; 478 479static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = { 480 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL }, 481 { 0 }, 482}; 483 484static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = { 485 "dpll_usb_clkdcoldo", 486 NULL, 487}; 488 489static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = { 490 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL }, 491 { 0 }, 492}; 493 494static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = { 495 { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" }, 496 { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" }, 497 { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" }, 498 { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" }, 499 { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" }, 500 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 501 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" }, 502 { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" }, 503 { 0 }, 504}; 505 506static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = { 507 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL }, 508 { 0 }, 509}; 510 511static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = { 512 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL }, 513 { 0 }, 514}; 515 516static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = { 517 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 518 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 519 { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" }, 520 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" }, 521 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" }, 522 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" }, 523 { 0 }, 524}; 525 526const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = { 527 { 0x4a004320, omap5_mpu_clkctrl_regs }, 528 { 0x4a004420, omap5_dsp_clkctrl_regs }, 529 { 0x4a004520, omap5_abe_clkctrl_regs }, 530 { 0x4a008720, omap5_l3main1_clkctrl_regs }, 531 { 0x4a008820, omap5_l3main2_clkctrl_regs }, 532 { 0x4a008920, omap5_ipu_clkctrl_regs }, 533 { 0x4a008a20, omap5_dma_clkctrl_regs }, 534 { 0x4a008b20, omap5_emif_clkctrl_regs }, 535 { 0x4a008d20, omap5_l4cfg_clkctrl_regs }, 536 { 0x4a008e20, omap5_l3instr_clkctrl_regs }, 537 { 0x4a009020, omap5_l4per_clkctrl_regs }, 538 { 0x4a0091a0, omap5_l4_secure_clkctrl_regs }, 539 { 0x4a009220, omap5_iva_clkctrl_regs }, 540 { 0x4a009420, omap5_dss_clkctrl_regs }, 541 { 0x4a009520, omap5_gpu_clkctrl_regs }, 542 { 0x4a009620, omap5_l3init_clkctrl_regs }, 543 { 0x4ae07920, omap5_wkupaon_clkctrl_regs }, 544 { 0 }, 545}; 546 547static struct ti_dt_clk omap54xx_clks[] = { 548 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 549 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"), 550 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"), 551 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), 552 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), 553 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), 554 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), 555 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"), 556 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), 557 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"), 558 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"), 559 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"), 560 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"), 561 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"), 562 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"), 563 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"), 564 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"), 565 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"), 566 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"), 567 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"), 568 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"), 569 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"), 570 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"), 571 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"), 572 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"), 573 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"), 574 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"), 575 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"), 576 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"), 577 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"), 578 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"), 579 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"), 580 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"), 581 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"), 582 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"), 583 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"), 584 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"), 585 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"), 586 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"), 587 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"), 588 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"), 589 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"), 590 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"), 591 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"), 592 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"), 593 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"), 594 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"), 595 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"), 596 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"), 597 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"), 598 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"), 599 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"), 600 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"), 601 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"), 602 { .node_name = NULL }, 603}; 604 605int __init omap5xxx_dt_clk_init(void) 606{ 607 int rc; 608 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 609 610 ti_dt_clocks_register(omap54xx_clks); 611 612 omap2_clk_disable_autoidle_all(); 613 614 ti_clk_add_aliases(); 615 616 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux"); 617 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 618 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 619 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 620 if (!rc) 621 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ); 622 if (rc) 623 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 624 625 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); 626 if (!rc) 627 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2); 628 if (rc) 629 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__); 630 631 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 632 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ); 633 if (rc) 634 pr_err("%s: failed to configure USB DPLL!\n", __func__); 635 636 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck"); 637 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2); 638 if (rc) 639 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__); 640 641 return 0; 642} 643