1/* 2 * OMAP APLL clock support 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * J Keerthy <j-keerthy@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/module.h> 21#include <linux/slab.h> 22#include <linux/io.h> 23#include <linux/err.h> 24#include <linux/string.h> 25#include <linux/log2.h> 26#include <linux/of.h> 27#include <linux/of_address.h> 28#include <linux/clk/ti.h> 29#include <linux/delay.h> 30 31#include "clock.h" 32 33#define APLL_FORCE_LOCK 0x1 34#define APLL_AUTO_IDLE 0x2 35#define MAX_APLL_WAIT_TRIES 1000000 36 37#undef pr_fmt 38#define pr_fmt(fmt) "%s: " fmt, __func__ 39 40static int dra7_apll_enable(struct clk_hw *hw) 41{ 42 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 43 int r = 0, i = 0; 44 struct dpll_data *ad; 45 const char *clk_name; 46 u8 state = 1; 47 u32 v; 48 49 ad = clk->dpll_data; 50 if (!ad) 51 return -EINVAL; 52 53 clk_name = clk_hw_get_name(&clk->hw); 54 55 state <<= __ffs(ad->idlest_mask); 56 57 /* Check is already locked */ 58 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); 59 60 if ((v & ad->idlest_mask) == state) 61 return r; 62 63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 64 v &= ~ad->enable_mask; 65 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); 66 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 67 68 state <<= __ffs(ad->idlest_mask); 69 70 while (1) { 71 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); 72 if ((v & ad->idlest_mask) == state) 73 break; 74 if (i > MAX_APLL_WAIT_TRIES) 75 break; 76 i++; 77 udelay(1); 78 } 79 80 if (i == MAX_APLL_WAIT_TRIES) { 81 pr_warn("clock: %s failed transition to '%s'\n", 82 clk_name, (state) ? "locked" : "bypassed"); 83 r = -EBUSY; 84 } else 85 pr_debug("clock: %s transition to '%s' in %d loops\n", 86 clk_name, (state) ? "locked" : "bypassed", i); 87 88 return r; 89} 90 91static void dra7_apll_disable(struct clk_hw *hw) 92{ 93 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 94 struct dpll_data *ad; 95 u8 state = 1; 96 u32 v; 97 98 ad = clk->dpll_data; 99 100 state <<= __ffs(ad->idlest_mask); 101 102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 103 v &= ~ad->enable_mask; 104 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); 105 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 106} 107 108static int dra7_apll_is_enabled(struct clk_hw *hw) 109{ 110 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 111 struct dpll_data *ad; 112 u32 v; 113 114 ad = clk->dpll_data; 115 116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 117 v &= ad->enable_mask; 118 119 v >>= __ffs(ad->enable_mask); 120 121 return v == APLL_AUTO_IDLE ? 0 : 1; 122} 123 124static u8 dra7_init_apll_parent(struct clk_hw *hw) 125{ 126 return 0; 127} 128 129static const struct clk_ops apll_ck_ops = { 130 .enable = &dra7_apll_enable, 131 .disable = &dra7_apll_disable, 132 .is_enabled = &dra7_apll_is_enabled, 133 .get_parent = &dra7_init_apll_parent, 134}; 135 136static void __init omap_clk_register_apll(void *user, 137 struct device_node *node) 138{ 139 struct clk_hw *hw = user; 140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 141 struct dpll_data *ad = clk_hw->dpll_data; 142 const char *name; 143 struct clk *clk; 144 const struct clk_init_data *init = clk_hw->hw.init; 145 146 clk = of_clk_get(node, 0); 147 if (IS_ERR(clk)) { 148 pr_debug("clk-ref for %pOFn not ready, retry\n", 149 node); 150 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) 151 return; 152 153 goto cleanup; 154 } 155 156 ad->clk_ref = __clk_get_hw(clk); 157 158 clk = of_clk_get(node, 1); 159 if (IS_ERR(clk)) { 160 pr_debug("clk-bypass for %pOFn not ready, retry\n", 161 node); 162 if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) 163 return; 164 165 goto cleanup; 166 } 167 168 ad->clk_bypass = __clk_get_hw(clk); 169 170 name = ti_dt_clk_name(node); 171 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); 172 if (!IS_ERR(clk)) { 173 of_clk_add_provider(node, of_clk_src_simple_get, clk); 174 kfree(init->parent_names); 175 kfree(init); 176 return; 177 } 178 179cleanup: 180 kfree(clk_hw->dpll_data); 181 kfree(init->parent_names); 182 kfree(init); 183 kfree(clk_hw); 184} 185 186static void __init of_dra7_apll_setup(struct device_node *node) 187{ 188 struct dpll_data *ad = NULL; 189 struct clk_hw_omap *clk_hw = NULL; 190 struct clk_init_data *init = NULL; 191 const char **parent_names = NULL; 192 int ret; 193 194 ad = kzalloc(sizeof(*ad), GFP_KERNEL); 195 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 196 init = kzalloc(sizeof(*init), GFP_KERNEL); 197 if (!ad || !clk_hw || !init) 198 goto cleanup; 199 200 clk_hw->dpll_data = ad; 201 clk_hw->hw.init = init; 202 203 init->name = ti_dt_clk_name(node); 204 init->ops = &apll_ck_ops; 205 206 init->num_parents = of_clk_get_parent_count(node); 207 if (init->num_parents < 1) { 208 pr_err("dra7 apll %pOFn must have parent(s)\n", node); 209 goto cleanup; 210 } 211 212 parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); 213 if (!parent_names) 214 goto cleanup; 215 216 of_clk_parent_fill(node, parent_names, init->num_parents); 217 218 init->parent_names = parent_names; 219 220 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); 221 ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg); 222 223 if (ret) 224 goto cleanup; 225 226 ad->idlest_mask = 0x1; 227 ad->enable_mask = 0x3; 228 229 omap_clk_register_apll(&clk_hw->hw, node); 230 return; 231 232cleanup: 233 kfree(parent_names); 234 kfree(ad); 235 kfree(clk_hw); 236 kfree(init); 237} 238CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); 239 240#define OMAP2_EN_APLL_LOCKED 0x3 241#define OMAP2_EN_APLL_STOPPED 0x0 242 243static int omap2_apll_is_enabled(struct clk_hw *hw) 244{ 245 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 246 struct dpll_data *ad = clk->dpll_data; 247 u32 v; 248 249 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 250 v &= ad->enable_mask; 251 252 v >>= __ffs(ad->enable_mask); 253 254 return v == OMAP2_EN_APLL_LOCKED ? 1 : 0; 255} 256 257static unsigned long omap2_apll_recalc(struct clk_hw *hw, 258 unsigned long parent_rate) 259{ 260 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 261 262 if (omap2_apll_is_enabled(hw)) 263 return clk->fixed_rate; 264 265 return 0; 266} 267 268static int omap2_apll_enable(struct clk_hw *hw) 269{ 270 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 271 struct dpll_data *ad = clk->dpll_data; 272 u32 v; 273 int i = 0; 274 275 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 276 v &= ~ad->enable_mask; 277 v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask); 278 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 279 280 while (1) { 281 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); 282 if (v & ad->idlest_mask) 283 break; 284 if (i > MAX_APLL_WAIT_TRIES) 285 break; 286 i++; 287 udelay(1); 288 } 289 290 if (i == MAX_APLL_WAIT_TRIES) { 291 pr_warn("%s failed to transition to locked\n", 292 clk_hw_get_name(&clk->hw)); 293 return -EBUSY; 294 } 295 296 return 0; 297} 298 299static void omap2_apll_disable(struct clk_hw *hw) 300{ 301 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 302 struct dpll_data *ad = clk->dpll_data; 303 u32 v; 304 305 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); 306 v &= ~ad->enable_mask; 307 v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask); 308 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 309} 310 311static const struct clk_ops omap2_apll_ops = { 312 .enable = &omap2_apll_enable, 313 .disable = &omap2_apll_disable, 314 .is_enabled = &omap2_apll_is_enabled, 315 .recalc_rate = &omap2_apll_recalc, 316}; 317 318static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) 319{ 320 struct dpll_data *ad = clk->dpll_data; 321 u32 v; 322 323 v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); 324 v &= ~ad->autoidle_mask; 325 v |= val << __ffs(ad->autoidle_mask); 326 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); 327} 328 329#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 330#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0 331 332static void omap2_apll_allow_idle(struct clk_hw_omap *clk) 333{ 334 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP); 335} 336 337static void omap2_apll_deny_idle(struct clk_hw_omap *clk) 338{ 339 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); 340} 341 342static const struct clk_hw_omap_ops omap2_apll_hwops = { 343 .allow_idle = &omap2_apll_allow_idle, 344 .deny_idle = &omap2_apll_deny_idle, 345}; 346 347static void __init of_omap2_apll_setup(struct device_node *node) 348{ 349 struct dpll_data *ad = NULL; 350 struct clk_hw_omap *clk_hw = NULL; 351 struct clk_init_data *init = NULL; 352 const char *name; 353 struct clk *clk; 354 const char *parent_name; 355 u32 val; 356 int ret; 357 358 ad = kzalloc(sizeof(*ad), GFP_KERNEL); 359 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 360 init = kzalloc(sizeof(*init), GFP_KERNEL); 361 362 if (!ad || !clk_hw || !init) 363 goto cleanup; 364 365 clk_hw->dpll_data = ad; 366 clk_hw->hw.init = init; 367 init->ops = &omap2_apll_ops; 368 name = ti_dt_clk_name(node); 369 init->name = name; 370 clk_hw->ops = &omap2_apll_hwops; 371 372 init->num_parents = of_clk_get_parent_count(node); 373 if (init->num_parents != 1) { 374 pr_err("%pOFn must have one parent\n", node); 375 goto cleanup; 376 } 377 378 parent_name = of_clk_get_parent_name(node, 0); 379 init->parent_names = &parent_name; 380 381 if (of_property_read_u32(node, "ti,clock-frequency", &val)) { 382 pr_err("%pOFn missing clock-frequency\n", node); 383 goto cleanup; 384 } 385 clk_hw->fixed_rate = val; 386 387 if (of_property_read_u32(node, "ti,bit-shift", &val)) { 388 pr_err("%pOFn missing bit-shift\n", node); 389 goto cleanup; 390 } 391 392 clk_hw->enable_bit = val; 393 ad->enable_mask = 0x3 << val; 394 ad->autoidle_mask = 0x3 << val; 395 396 if (of_property_read_u32(node, "ti,idlest-shift", &val)) { 397 pr_err("%pOFn missing idlest-shift\n", node); 398 goto cleanup; 399 } 400 401 ad->idlest_mask = 1 << val; 402 403 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); 404 ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg); 405 ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg); 406 407 if (ret) 408 goto cleanup; 409 410 name = ti_dt_clk_name(node); 411 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name); 412 if (!IS_ERR(clk)) { 413 of_clk_add_provider(node, of_clk_src_simple_get, clk); 414 kfree(init); 415 return; 416 } 417cleanup: 418 kfree(ad); 419 kfree(clk_hw); 420 kfree(init); 421} 422CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock", 423 of_omap2_apll_setup); 424