1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/io.h> 7#include <linux/delay.h> 8#include <linux/clk-provider.h> 9#include <linux/clkdev.h> 10#include <linux/of.h> 11#include <linux/of_address.h> 12#include <linux/clk/tegra.h> 13 14#include <soc/tegra/pmc.h> 15 16#include <dt-bindings/clock/tegra30-car.h> 17 18#include "clk.h" 19#include "clk-id.h" 20 21#define OSC_CTRL 0x50 22#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 23#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 24#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 25#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 26#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 27#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 28#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 29#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 30#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 31 32#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 33#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 34#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 35#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 36 37#define OSC_FREQ_DET 0x58 38#define OSC_FREQ_DET_TRIG BIT(31) 39 40#define OSC_FREQ_DET_STATUS 0x5c 41#define OSC_FREQ_DET_BUSY BIT(31) 42#define OSC_FREQ_DET_CNT_MASK 0xffff 43 44#define CCLKG_BURST_POLICY 0x368 45#define SUPER_CCLKG_DIVIDER 0x36c 46#define CCLKLP_BURST_POLICY 0x370 47#define SUPER_CCLKLP_DIVIDER 0x374 48#define SCLK_BURST_POLICY 0x028 49#define SUPER_SCLK_DIVIDER 0x02c 50 51#define SYSTEM_CLK_RATE 0x030 52 53#define TEGRA30_CLK_PERIPH_BANKS 5 54 55#define PLLC_BASE 0x80 56#define PLLC_MISC 0x8c 57#define PLLM_BASE 0x90 58#define PLLM_MISC 0x9c 59#define PLLP_BASE 0xa0 60#define PLLP_MISC 0xac 61#define PLLX_BASE 0xe0 62#define PLLX_MISC 0xe4 63#define PLLD_BASE 0xd0 64#define PLLD_MISC 0xdc 65#define PLLD2_BASE 0x4b8 66#define PLLD2_MISC 0x4bc 67#define PLLE_BASE 0xe8 68#define PLLE_MISC 0xec 69#define PLLA_BASE 0xb0 70#define PLLA_MISC 0xbc 71#define PLLU_BASE 0xc0 72#define PLLU_MISC 0xcc 73 74#define PLL_MISC_LOCK_ENABLE 18 75#define PLLDU_MISC_LOCK_ENABLE 22 76#define PLLE_MISC_LOCK_ENABLE 9 77 78#define PLL_BASE_LOCK BIT(27) 79#define PLLE_MISC_LOCK BIT(11) 80 81#define PLLE_AUX 0x48c 82#define PLLC_OUT 0x84 83#define PLLM_OUT 0x94 84#define PLLP_OUTA 0xa4 85#define PLLP_OUTB 0xa8 86#define PLLA_OUT 0xb4 87 88#define AUDIO_SYNC_CLK_I2S0 0x4a0 89#define AUDIO_SYNC_CLK_I2S1 0x4a4 90#define AUDIO_SYNC_CLK_I2S2 0x4a8 91#define AUDIO_SYNC_CLK_I2S3 0x4ac 92#define AUDIO_SYNC_CLK_I2S4 0x4b0 93#define AUDIO_SYNC_CLK_SPDIF 0x4b4 94 95#define CLK_SOURCE_SPDIF_OUT 0x108 96#define CLK_SOURCE_PWM 0x110 97#define CLK_SOURCE_D_AUDIO 0x3d0 98#define CLK_SOURCE_DAM0 0x3d8 99#define CLK_SOURCE_DAM1 0x3dc 100#define CLK_SOURCE_DAM2 0x3e0 101#define CLK_SOURCE_3D2 0x3b0 102#define CLK_SOURCE_2D 0x15c 103#define CLK_SOURCE_HDMI 0x18c 104#define CLK_SOURCE_DSIB 0xd0 105#define CLK_SOURCE_SE 0x42c 106#define CLK_SOURCE_EMC 0x19c 107 108#define AUDIO_SYNC_DOUBLER 0x49c 109 110/* Tegra CPU clock and reset control regs */ 111#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 112#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 113#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 114#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 115#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 116 117#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 118#define CPU_RESET(cpu) (0x1111ul << (cpu)) 119 120#define CLK_RESET_CCLK_BURST 0x20 121#define CLK_RESET_CCLK_DIVIDER 0x24 122#define CLK_RESET_PLLX_BASE 0xe0 123#define CLK_RESET_PLLX_MISC 0xe4 124 125#define CLK_RESET_SOURCE_CSITE 0x1d4 126 127#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 128#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 129#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 130#define CLK_RESET_CCLK_IDLE_POLICY 1 131#define CLK_RESET_CCLK_RUN_POLICY 2 132#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 133 134/* PLLM override registers */ 135#define PMC_PLLM_WB0_OVERRIDE 0x1dc 136 137#ifdef CONFIG_PM_SLEEP 138static struct cpu_clk_suspend_context { 139 u32 pllx_misc; 140 u32 pllx_base; 141 142 u32 cpu_burst; 143 u32 clk_csite_src; 144 u32 cclk_divider; 145} tegra30_cpu_clk_sctx; 146#endif 147 148static void __iomem *clk_base; 149static void __iomem *pmc_base; 150static unsigned long input_freq; 151 152static DEFINE_SPINLOCK(cml_lock); 153static DEFINE_SPINLOCK(pll_d_lock); 154 155#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ 156 _clk_num, _gate_flags, _clk_id) \ 157 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 158 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 159 _clk_num, _gate_flags, _clk_id) 160 161#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ 162 _clk_num, _gate_flags, _clk_id) \ 163 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 164 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 165 _clk_num, _gate_flags, _clk_id) 166 167#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ 168 _clk_num, _gate_flags, _clk_id) \ 169 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 170 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 171 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 172 _gate_flags, _clk_id) 173 174#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ 175 _mux_shift, _mux_width, _clk_num, \ 176 _gate_flags, _clk_id) \ 177 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \ 178 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\ 179 _clk_num, _gate_flags, \ 180 _clk_id) 181 182static struct clk **clks; 183 184static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 185 { 12000000, 1040000000, 520, 6, 1, 8 }, 186 { 13000000, 1040000000, 480, 6, 1, 8 }, 187 { 16800000, 1040000000, 495, 8, 1, 8 }, /* actual: 1039.5 MHz */ 188 { 19200000, 1040000000, 325, 6, 1, 6 }, 189 { 26000000, 1040000000, 520, 13, 1, 8 }, 190 { 12000000, 832000000, 416, 6, 1, 8 }, 191 { 13000000, 832000000, 832, 13, 1, 8 }, 192 { 16800000, 832000000, 396, 8, 1, 8 }, /* actual: 831.6 MHz */ 193 { 19200000, 832000000, 260, 6, 1, 8 }, 194 { 26000000, 832000000, 416, 13, 1, 8 }, 195 { 12000000, 624000000, 624, 12, 1, 8 }, 196 { 13000000, 624000000, 624, 13, 1, 8 }, 197 { 16800000, 600000000, 520, 14, 1, 8 }, 198 { 19200000, 624000000, 520, 16, 1, 8 }, 199 { 26000000, 624000000, 624, 26, 1, 8 }, 200 { 12000000, 600000000, 600, 12, 1, 8 }, 201 { 13000000, 600000000, 600, 13, 1, 8 }, 202 { 16800000, 600000000, 500, 14, 1, 8 }, 203 { 19200000, 600000000, 375, 12, 1, 6 }, 204 { 26000000, 600000000, 600, 26, 1, 8 }, 205 { 12000000, 520000000, 520, 12, 1, 8 }, 206 { 13000000, 520000000, 520, 13, 1, 8 }, 207 { 16800000, 520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */ 208 { 19200000, 520000000, 325, 12, 1, 6 }, 209 { 26000000, 520000000, 520, 26, 1, 8 }, 210 { 12000000, 416000000, 416, 12, 1, 8 }, 211 { 13000000, 416000000, 416, 13, 1, 8 }, 212 { 16800000, 416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */ 213 { 19200000, 416000000, 260, 12, 1, 6 }, 214 { 26000000, 416000000, 416, 26, 1, 8 }, 215 { 0, 0, 0, 0, 0, 0 }, 216}; 217 218static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 219 { 12000000, 666000000, 666, 12, 1, 8 }, 220 { 13000000, 666000000, 666, 13, 1, 8 }, 221 { 16800000, 666000000, 555, 14, 1, 8 }, 222 { 19200000, 666000000, 555, 16, 1, 8 }, 223 { 26000000, 666000000, 666, 26, 1, 8 }, 224 { 12000000, 600000000, 600, 12, 1, 8 }, 225 { 13000000, 600000000, 600, 13, 1, 8 }, 226 { 16800000, 600000000, 500, 14, 1, 8 }, 227 { 19200000, 600000000, 375, 12, 1, 6 }, 228 { 26000000, 600000000, 600, 26, 1, 8 }, 229 { 0, 0, 0, 0, 0, 0 }, 230}; 231 232static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 233 { 12000000, 216000000, 432, 12, 2, 8 }, 234 { 13000000, 216000000, 432, 13, 2, 8 }, 235 { 16800000, 216000000, 360, 14, 2, 8 }, 236 { 19200000, 216000000, 360, 16, 2, 8 }, 237 { 26000000, 216000000, 432, 26, 2, 8 }, 238 { 0, 0, 0, 0, 0, 0 }, 239}; 240 241static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 242 { 9600000, 564480000, 294, 5, 1, 4 }, 243 { 9600000, 552960000, 288, 5, 1, 4 }, 244 { 9600000, 24000000, 5, 2, 1, 1 }, 245 { 28800000, 56448000, 49, 25, 1, 1 }, 246 { 28800000, 73728000, 64, 25, 1, 1 }, 247 { 28800000, 24000000, 5, 6, 1, 1 }, 248 { 0, 0, 0, 0, 0, 0 }, 249}; 250 251static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 252 { 12000000, 216000000, 216, 12, 1, 4 }, 253 { 13000000, 216000000, 216, 13, 1, 4 }, 254 { 16800000, 216000000, 180, 14, 1, 4 }, 255 { 19200000, 216000000, 180, 16, 1, 4 }, 256 { 26000000, 216000000, 216, 26, 1, 4 }, 257 { 12000000, 594000000, 594, 12, 1, 8 }, 258 { 13000000, 594000000, 594, 13, 1, 8 }, 259 { 16800000, 594000000, 495, 14, 1, 8 }, 260 { 19200000, 594000000, 495, 16, 1, 8 }, 261 { 26000000, 594000000, 594, 26, 1, 8 }, 262 { 12000000, 1000000000, 1000, 12, 1, 12 }, 263 { 13000000, 1000000000, 1000, 13, 1, 12 }, 264 { 19200000, 1000000000, 625, 12, 1, 8 }, 265 { 26000000, 1000000000, 1000, 26, 1, 12 }, 266 { 0, 0, 0, 0, 0, 0 }, 267}; 268 269static const struct pdiv_map pllu_p[] = { 270 { .pdiv = 1, .hw_val = 1 }, 271 { .pdiv = 2, .hw_val = 0 }, 272 { .pdiv = 0, .hw_val = 0 }, 273}; 274 275static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 276 { 12000000, 480000000, 960, 12, 2, 12 }, 277 { 13000000, 480000000, 960, 13, 2, 12 }, 278 { 16800000, 480000000, 400, 7, 2, 5 }, 279 { 19200000, 480000000, 200, 4, 2, 3 }, 280 { 26000000, 480000000, 960, 26, 2, 12 }, 281 { 0, 0, 0, 0, 0, 0 }, 282}; 283 284static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 285 /* 1.7 GHz */ 286 { 12000000, 1700000000, 850, 6, 1, 8 }, 287 { 13000000, 1700000000, 915, 7, 1, 8 }, /* actual: 1699.2 MHz */ 288 { 16800000, 1700000000, 708, 7, 1, 8 }, /* actual: 1699.2 MHz */ 289 { 19200000, 1700000000, 885, 10, 1, 8 }, /* actual: 1699.2 MHz */ 290 { 26000000, 1700000000, 850, 13, 1, 8 }, 291 /* 1.6 GHz */ 292 { 12000000, 1600000000, 800, 6, 1, 8 }, 293 { 13000000, 1600000000, 738, 6, 1, 8 }, /* actual: 1599.0 MHz */ 294 { 16800000, 1600000000, 857, 9, 1, 8 }, /* actual: 1599.7 MHz */ 295 { 19200000, 1600000000, 500, 6, 1, 8 }, 296 { 26000000, 1600000000, 800, 13, 1, 8 }, 297 /* 1.5 GHz */ 298 { 12000000, 1500000000, 750, 6, 1, 8 }, 299 { 13000000, 1500000000, 923, 8, 1, 8 }, /* actual: 1499.8 MHz */ 300 { 16800000, 1500000000, 625, 7, 1, 8 }, 301 { 19200000, 1500000000, 625, 8, 1, 8 }, 302 { 26000000, 1500000000, 750, 13, 1, 8 }, 303 /* 1.4 GHz */ 304 { 12000000, 1400000000, 700, 6, 1, 8 }, 305 { 13000000, 1400000000, 969, 9, 1, 8 }, /* actual: 1399.7 MHz */ 306 { 16800000, 1400000000, 1000, 12, 1, 8 }, 307 { 19200000, 1400000000, 875, 12, 1, 8 }, 308 { 26000000, 1400000000, 700, 13, 1, 8 }, 309 /* 1.3 GHz */ 310 { 12000000, 1300000000, 975, 9, 1, 8 }, 311 { 13000000, 1300000000, 1000, 10, 1, 8 }, 312 { 16800000, 1300000000, 928, 12, 1, 8 }, /* actual: 1299.2 MHz */ 313 { 19200000, 1300000000, 812, 12, 1, 8 }, /* actual: 1299.2 MHz */ 314 { 26000000, 1300000000, 650, 13, 1, 8 }, 315 /* 1.2 GHz */ 316 { 12000000, 1200000000, 1000, 10, 1, 8 }, 317 { 13000000, 1200000000, 923, 10, 1, 8 }, /* actual: 1199.9 MHz */ 318 { 16800000, 1200000000, 1000, 14, 1, 8 }, 319 { 19200000, 1200000000, 1000, 16, 1, 8 }, 320 { 26000000, 1200000000, 600, 13, 1, 8 }, 321 /* 1.1 GHz */ 322 { 12000000, 1100000000, 825, 9, 1, 8 }, 323 { 13000000, 1100000000, 846, 10, 1, 8 }, /* actual: 1099.8 MHz */ 324 { 16800000, 1100000000, 982, 15, 1, 8 }, /* actual: 1099.8 MHz */ 325 { 19200000, 1100000000, 859, 15, 1, 8 }, /* actual: 1099.5 MHz */ 326 { 26000000, 1100000000, 550, 13, 1, 8 }, 327 /* 1 GHz */ 328 { 12000000, 1000000000, 1000, 12, 1, 8 }, 329 { 13000000, 1000000000, 1000, 13, 1, 8 }, 330 { 16800000, 1000000000, 833, 14, 1, 8 }, /* actual: 999.6 MHz */ 331 { 19200000, 1000000000, 625, 12, 1, 8 }, 332 { 26000000, 1000000000, 1000, 26, 1, 8 }, 333 { 0, 0, 0, 0, 0, 0 }, 334}; 335 336static const struct pdiv_map plle_p[] = { 337 { .pdiv = 18, .hw_val = 18 }, 338 { .pdiv = 24, .hw_val = 24 }, 339 { .pdiv = 0, .hw_val = 0 }, 340}; 341 342static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 343 /* PLLE special case: use cpcon field to store cml divider value */ 344 { 12000000, 100000000, 150, 1, 18, 11 }, 345 { 216000000, 100000000, 200, 18, 24, 13 }, 346 { 0, 0, 0, 0, 0, 0 }, 347}; 348 349/* PLL parameters */ 350static struct tegra_clk_pll_params pll_c_params __ro_after_init = { 351 .input_min = 2000000, 352 .input_max = 31000000, 353 .cf_min = 1000000, 354 .cf_max = 6000000, 355 .vco_min = 20000000, 356 .vco_max = 1400000000, 357 .base_reg = PLLC_BASE, 358 .misc_reg = PLLC_MISC, 359 .lock_mask = PLL_BASE_LOCK, 360 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 361 .lock_delay = 300, 362 .freq_table = pll_c_freq_table, 363 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 364 TEGRA_PLL_HAS_LOCK_ENABLE, 365}; 366 367static struct div_nmp pllm_nmp = { 368 .divn_shift = 8, 369 .divn_width = 10, 370 .override_divn_shift = 5, 371 .divm_shift = 0, 372 .divm_width = 5, 373 .override_divm_shift = 0, 374 .divp_shift = 20, 375 .divp_width = 3, 376 .override_divp_shift = 15, 377}; 378 379static struct tegra_clk_pll_params pll_m_params __ro_after_init = { 380 .input_min = 2000000, 381 .input_max = 31000000, 382 .cf_min = 1000000, 383 .cf_max = 6000000, 384 .vco_min = 20000000, 385 .vco_max = 1200000000, 386 .base_reg = PLLM_BASE, 387 .misc_reg = PLLM_MISC, 388 .lock_mask = PLL_BASE_LOCK, 389 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 390 .lock_delay = 300, 391 .div_nmp = &pllm_nmp, 392 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 393 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 394 .freq_table = pll_m_freq_table, 395 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 396 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | 397 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED, 398}; 399 400static struct tegra_clk_pll_params pll_p_params __ro_after_init = { 401 .input_min = 2000000, 402 .input_max = 31000000, 403 .cf_min = 1000000, 404 .cf_max = 6000000, 405 .vco_min = 20000000, 406 .vco_max = 1400000000, 407 .base_reg = PLLP_BASE, 408 .misc_reg = PLLP_MISC, 409 .lock_mask = PLL_BASE_LOCK, 410 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 411 .lock_delay = 300, 412 .freq_table = pll_p_freq_table, 413 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 414 TEGRA_PLL_HAS_LOCK_ENABLE, 415 .fixed_rate = 408000000, 416}; 417 418static struct tegra_clk_pll_params pll_a_params = { 419 .input_min = 2000000, 420 .input_max = 31000000, 421 .cf_min = 1000000, 422 .cf_max = 6000000, 423 .vco_min = 20000000, 424 .vco_max = 1400000000, 425 .base_reg = PLLA_BASE, 426 .misc_reg = PLLA_MISC, 427 .lock_mask = PLL_BASE_LOCK, 428 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 429 .lock_delay = 300, 430 .freq_table = pll_a_freq_table, 431 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK | 432 TEGRA_PLL_HAS_LOCK_ENABLE, 433}; 434 435static struct tegra_clk_pll_params pll_d_params __ro_after_init = { 436 .input_min = 2000000, 437 .input_max = 40000000, 438 .cf_min = 1000000, 439 .cf_max = 6000000, 440 .vco_min = 40000000, 441 .vco_max = 1000000000, 442 .base_reg = PLLD_BASE, 443 .misc_reg = PLLD_MISC, 444 .lock_mask = PLL_BASE_LOCK, 445 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 446 .lock_delay = 1000, 447 .freq_table = pll_d_freq_table, 448 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 449 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 450}; 451 452static struct tegra_clk_pll_params pll_d2_params __ro_after_init = { 453 .input_min = 2000000, 454 .input_max = 40000000, 455 .cf_min = 1000000, 456 .cf_max = 6000000, 457 .vco_min = 40000000, 458 .vco_max = 1000000000, 459 .base_reg = PLLD2_BASE, 460 .misc_reg = PLLD2_MISC, 461 .lock_mask = PLL_BASE_LOCK, 462 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 463 .lock_delay = 1000, 464 .freq_table = pll_d_freq_table, 465 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 466 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 467}; 468 469static struct tegra_clk_pll_params pll_u_params __ro_after_init = { 470 .input_min = 2000000, 471 .input_max = 40000000, 472 .cf_min = 1000000, 473 .cf_max = 6000000, 474 .vco_min = 48000000, 475 .vco_max = 960000000, 476 .base_reg = PLLU_BASE, 477 .misc_reg = PLLU_MISC, 478 .lock_mask = PLL_BASE_LOCK, 479 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 480 .lock_delay = 1000, 481 .pdiv_tohw = pllu_p, 482 .freq_table = pll_u_freq_table, 483 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 484 TEGRA_PLL_HAS_LOCK_ENABLE, 485}; 486 487static struct tegra_clk_pll_params pll_x_params __ro_after_init = { 488 .input_min = 2000000, 489 .input_max = 31000000, 490 .cf_min = 1000000, 491 .cf_max = 6000000, 492 .vco_min = 20000000, 493 .vco_max = 1700000000, 494 .base_reg = PLLX_BASE, 495 .misc_reg = PLLX_MISC, 496 .lock_mask = PLL_BASE_LOCK, 497 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 498 .lock_delay = 300, 499 .freq_table = pll_x_freq_table, 500 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | 501 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 502 .pre_rate_change = tegra_cclk_pre_pllx_rate_change, 503 .post_rate_change = tegra_cclk_post_pllx_rate_change, 504}; 505 506static struct tegra_clk_pll_params pll_e_params __ro_after_init = { 507 .input_min = 12000000, 508 .input_max = 216000000, 509 .cf_min = 12000000, 510 .cf_max = 12000000, 511 .vco_min = 1200000000, 512 .vco_max = 2400000000U, 513 .base_reg = PLLE_BASE, 514 .misc_reg = PLLE_MISC, 515 .lock_mask = PLLE_MISC_LOCK, 516 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 517 .lock_delay = 300, 518 .pdiv_tohw = plle_p, 519 .freq_table = pll_e_freq_table, 520 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED | 521 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC, 522 .fixed_rate = 100000000, 523}; 524 525static unsigned long tegra30_input_freq[] = { 526 [ 0] = 13000000, 527 [ 1] = 16800000, 528 [ 4] = 19200000, 529 [ 5] = 38400000, 530 [ 8] = 12000000, 531 [ 9] = 48000000, 532 [12] = 26000000, 533}; 534 535static struct tegra_devclk devclks[] __initdata = { 536 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C }, 537 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 }, 538 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P }, 539 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 }, 540 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 }, 541 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 }, 542 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 }, 543 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M }, 544 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 }, 545 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X }, 546 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 }, 547 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U }, 548 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D }, 549 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 }, 550 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 }, 551 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 }, 552 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A }, 553 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 }, 554 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E }, 555 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC }, 556 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC }, 557 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC }, 558 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC }, 559 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC }, 560 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC }, 561 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC }, 562 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 }, 563 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 }, 564 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 }, 565 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 }, 566 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 }, 567 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF }, 568 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X }, 569 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X }, 570 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X }, 571 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X }, 572 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X }, 573 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X }, 574 { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 }, 575 { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 }, 576 { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 }, 577 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G }, 578 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP }, 579 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK }, 580 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK }, 581 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK }, 582 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD }, 583 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC }, 584 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, 585 { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC }, 586 { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 }, 587 { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 }, 588 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 }, 589 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 }, 590 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M }, 591 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF }, 592 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS }, 593 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP }, 594 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA }, 595 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV }, 596 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA }, 597 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI }, 598 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP }, 599 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE }, 600 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI }, 601 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE }, 602 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN }, 603 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF }, 604 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI }, 605 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA }, 606 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC }, 607 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER }, 608 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC }, 609 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD }, 610 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 }, 611 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 }, 612 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE }, 613 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD }, 614 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV }, 615 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 }, 616 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 }, 617 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 }, 618 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 }, 619 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 }, 620 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT }, 621 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN }, 622 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO }, 623 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 }, 624 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 }, 625 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 }, 626 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA }, 627 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X }, 628 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 }, 629 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 }, 630 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 }, 631 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 }, 632 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 }, 633 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 }, 634 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB }, 635 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA }, 636 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH }, 637 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED }, 638 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR }, 639 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE }, 640 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA }, 641 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR }, 642 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI }, 643 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR }, 644 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW }, 645 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE }, 646 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI }, 647 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP }, 648 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE }, 649 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X }, 650 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D }, 651 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 }, 652 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D }, 653 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE }, 654 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT }, 655 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR }, 656 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 }, 657 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 }, 658 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 }, 659 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 }, 660 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE }, 661 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO }, 662 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC }, 663 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON }, 664 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR }, 665 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 }, 666 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 }, 667 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 }, 668 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 }, 669 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 }, 670 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA }, 671 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB }, 672 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC }, 673 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD }, 674 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE }, 675 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI }, 676 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 }, 677 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 }, 678 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 }, 679 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM }, 680 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 }, 681 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 }, 682 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB }, 683}; 684 685static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { 686 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true }, 687 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, 688 [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true }, 689 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true }, 690 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true }, 691 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true }, 692 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true }, 693 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true }, 694 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true }, 695 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true }, 696 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true }, 697 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true }, 698 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true }, 699 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true }, 700 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true }, 701 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true }, 702 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true }, 703 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true }, 704 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true }, 705 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true }, 706 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true }, 707 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true }, 708 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true }, 709 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true }, 710 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true }, 711 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true }, 712 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true }, 713 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true }, 714 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true }, 715 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true }, 716 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true }, 717 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true }, 718 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true }, 719 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true }, 720 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true }, 721 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true }, 722 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true }, 723 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true }, 724 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true }, 725 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true }, 726 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true }, 727 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true }, 728 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true }, 729 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true }, 730 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true }, 731 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true }, 732 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true }, 733 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true }, 734 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true }, 735 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true }, 736 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true }, 737 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true }, 738 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true }, 739 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true }, 740 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true }, 741 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true }, 742 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true }, 743 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true }, 744 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true }, 745 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true }, 746 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true }, 747 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true }, 748 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true }, 749 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true }, 750 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true }, 751 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true }, 752 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true }, 753 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true }, 754 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true }, 755 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true }, 756 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true }, 757 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true }, 758 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true }, 759 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true }, 760 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true }, 761 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true }, 762 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true }, 763 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true }, 764 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true }, 765 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true }, 766 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true }, 767 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true }, 768 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true }, 769 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true }, 770 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true }, 771 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true }, 772 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, 773 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, 774 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, 775 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true }, 776 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, 777 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, 778 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true }, 779 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true }, 780 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true }, 781 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true }, 782 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true }, 783 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true }, 784 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true }, 785 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true }, 786 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true }, 787 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true }, 788 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true }, 789 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true }, 790 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true }, 791 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true }, 792 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true }, 793 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true }, 794 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true }, 795 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true }, 796 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true }, 797 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true }, 798 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true }, 799 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true }, 800 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true }, 801 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true }, 802 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true }, 803 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, 804 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 805 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true }, 806 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false }, 807}; 808 809static const char *pll_e_parents[] = { "pll_ref", "pll_p" }; 810 811static void __init tegra30_pll_init(void) 812{ 813 struct clk *clk; 814 815 /* PLLC */ 816 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 817 &pll_c_params, NULL); 818 clks[TEGRA30_CLK_PLL_C] = clk; 819 820 /* PLLC_OUT1 */ 821 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 822 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 823 8, 8, 1, NULL); 824 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 825 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 826 0, NULL); 827 clks[TEGRA30_CLK_PLL_C_OUT1] = clk; 828 829 /* PLLM */ 830 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 831 CLK_SET_RATE_GATE, &pll_m_params, NULL); 832 clks[TEGRA30_CLK_PLL_M] = clk; 833 834 /* PLLM_OUT1 */ 835 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 836 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 837 8, 8, 1, NULL); 838 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 839 clk_base + PLLM_OUT, 1, 0, 840 CLK_SET_RATE_PARENT, 0, NULL); 841 clks[TEGRA30_CLK_PLL_M_OUT1] = clk; 842 843 /* PLLX */ 844 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 845 &pll_x_params, NULL); 846 clks[TEGRA30_CLK_PLL_X] = clk; 847 848 /* PLLX_OUT0 */ 849 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 850 CLK_SET_RATE_PARENT, 1, 2); 851 clks[TEGRA30_CLK_PLL_X_OUT0] = clk; 852 853 /* PLLU */ 854 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, 855 &pll_u_params, NULL); 856 clks[TEGRA30_CLK_PLL_U] = clk; 857 858 /* PLLD */ 859 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 860 &pll_d_params, &pll_d_lock); 861 clks[TEGRA30_CLK_PLL_D] = clk; 862 863 /* PLLD_OUT0 */ 864 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 865 CLK_SET_RATE_PARENT, 1, 2); 866 clks[TEGRA30_CLK_PLL_D_OUT0] = clk; 867 868 /* PLLD2 */ 869 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 870 &pll_d2_params, NULL); 871 clks[TEGRA30_CLK_PLL_D2] = clk; 872 873 /* PLLD2_OUT0 */ 874 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 875 CLK_SET_RATE_PARENT, 1, 2); 876 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk; 877 878 /* PLLE */ 879 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 880 ARRAY_SIZE(pll_e_parents), 881 CLK_SET_RATE_NO_REPARENT, 882 clk_base + PLLE_AUX, 2, 1, 0, NULL); 883 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 884 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); 885 clks[TEGRA30_CLK_PLL_E] = clk; 886} 887 888static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 889 "pll_p_cclkg", "pll_p_out4_cclkg", 890 "pll_p_out3_cclkg", "unused", "pll_x" }; 891static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 892 "pll_p_cclklp", "pll_p_out4_cclklp", 893 "pll_p_out3_cclklp", "unused", "pll_x", 894 "pll_x_out0" }; 895static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 896 "pll_p_out3", "pll_p_out2", "unused", 897 "clk_32k", "pll_m_out1" }; 898 899static void __init tegra30_super_clk_init(void) 900{ 901 struct clk *clk; 902 903 /* 904 * Clock input to cclk_g divided from pll_p using 905 * U71 divider of cclk_g. 906 */ 907 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 908 clk_base + SUPER_CCLKG_DIVIDER, 0, 909 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 910 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 911 912 /* 913 * Clock input to cclk_g divided from pll_p_out3 using 914 * U71 divider of cclk_g. 915 */ 916 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 917 clk_base + SUPER_CCLKG_DIVIDER, 0, 918 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 919 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 920 921 /* 922 * Clock input to cclk_g divided from pll_p_out4 using 923 * U71 divider of cclk_g. 924 */ 925 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 926 clk_base + SUPER_CCLKG_DIVIDER, 0, 927 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 928 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 929 930 /* CCLKG */ 931 clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents, 932 ARRAY_SIZE(cclk_g_parents), 933 CLK_SET_RATE_PARENT, 934 clk_base + CCLKG_BURST_POLICY, 935 0, NULL); 936 clks[TEGRA30_CLK_CCLK_G] = clk; 937 938 /* 939 * Clock input to cclk_lp divided from pll_p using 940 * U71 divider of cclk_lp. 941 */ 942 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 943 clk_base + SUPER_CCLKLP_DIVIDER, 0, 944 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 945 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 946 947 /* 948 * Clock input to cclk_lp divided from pll_p_out3 using 949 * U71 divider of cclk_lp. 950 */ 951 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 952 clk_base + SUPER_CCLKLP_DIVIDER, 0, 953 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 954 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 955 956 /* 957 * Clock input to cclk_lp divided from pll_p_out4 using 958 * U71 divider of cclk_lp. 959 */ 960 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 961 clk_base + SUPER_CCLKLP_DIVIDER, 0, 962 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 963 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 964 965 /* CCLKLP */ 966 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 967 ARRAY_SIZE(cclk_lp_parents), 968 CLK_SET_RATE_PARENT, 969 clk_base + CCLKLP_BURST_POLICY, 970 TEGRA_DIVIDER_2, 4, 8, 9, 971 NULL); 972 clks[TEGRA30_CLK_CCLK_LP] = clk; 973 974 /* SCLK */ 975 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 976 ARRAY_SIZE(sclk_parents), 977 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 978 clk_base + SCLK_BURST_POLICY, 979 0, 4, 0, 0, NULL); 980 clks[TEGRA30_CLK_SCLK] = clk; 981 982 /* twd */ 983 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 984 CLK_SET_RATE_PARENT, 1, 2); 985 clks[TEGRA30_CLK_TWD] = clk; 986 987 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL); 988} 989 990static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 991 "clk_m" }; 992static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 993static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 994 "clk_m" }; 995static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 996static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 997 "pll_a_out0", "pll_c", 998 "pll_d2_out0", "clk_m" }; 999static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1000 "pll_d2_out0" }; 1001static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" }; 1002 1003static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1004 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT), 1005 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO), 1006 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0), 1007 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1), 1008 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2), 1009 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2), 1010 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE), 1011 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI), 1012 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM), 1013}; 1014 1015static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1016 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB), 1017}; 1018 1019static void __init tegra30_periph_clk_init(void) 1020{ 1021 struct tegra_periph_init_data *data; 1022 struct clk *clk; 1023 unsigned int i; 1024 1025 /* dsia */ 1026 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1027 0, 48, periph_clk_enb_refcnt); 1028 clks[TEGRA30_CLK_DSIA] = clk; 1029 1030 /* pcie */ 1031 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1032 70, periph_clk_enb_refcnt); 1033 clks[TEGRA30_CLK_PCIE] = clk; 1034 1035 /* afi */ 1036 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1037 periph_clk_enb_refcnt); 1038 clks[TEGRA30_CLK_AFI] = clk; 1039 1040 /* emc */ 1041 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true); 1042 1043 clks[TEGRA30_CLK_EMC] = clk; 1044 1045 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, 1046 NULL); 1047 clks[TEGRA30_CLK_MC] = clk; 1048 1049 /* cml0 */ 1050 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1051 0, 0, &cml_lock); 1052 clks[TEGRA30_CLK_CML0] = clk; 1053 1054 /* cml1 */ 1055 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1056 1, 0, &cml_lock); 1057 clks[TEGRA30_CLK_CML1] = clk; 1058 1059 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1060 data = &tegra_periph_clk_list[i]; 1061 clk = tegra_clk_register_periph_data(clk_base, data); 1062 clks[data->clk_id] = clk; 1063 } 1064 1065 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1066 data = &tegra_periph_nodiv_clk_list[i]; 1067 clk = tegra_clk_register_periph_nodiv(data->name, 1068 data->p.parent_names, 1069 data->num_parents, &data->periph, 1070 clk_base, data->offset); 1071 clks[data->clk_id] = clk; 1072 } 1073 1074 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params); 1075} 1076 1077/* Tegra30 CPU clock and reset control functions */ 1078static void tegra30_wait_cpu_in_reset(u32 cpu) 1079{ 1080 unsigned int reg; 1081 1082 do { 1083 reg = readl(clk_base + 1084 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1085 cpu_relax(); 1086 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1087 1088 return; 1089} 1090 1091static void tegra30_put_cpu_in_reset(u32 cpu) 1092{ 1093 writel(CPU_RESET(cpu), 1094 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1095 dmb(); 1096} 1097 1098static void tegra30_cpu_out_of_reset(u32 cpu) 1099{ 1100 writel(CPU_RESET(cpu), 1101 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1102 wmb(); 1103} 1104 1105static void tegra30_enable_cpu_clock(u32 cpu) 1106{ 1107 unsigned int reg; 1108 1109 writel(CPU_CLOCK(cpu), 1110 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1111 reg = readl(clk_base + 1112 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1113} 1114 1115static void tegra30_disable_cpu_clock(u32 cpu) 1116{ 1117 unsigned int reg; 1118 1119 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1120 writel(reg | CPU_CLOCK(cpu), 1121 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1122} 1123 1124#ifdef CONFIG_PM_SLEEP 1125static bool tegra30_cpu_rail_off_ready(void) 1126{ 1127 unsigned int cpu_rst_status; 1128 int cpu_pwr_status; 1129 1130 cpu_rst_status = readl(clk_base + 1131 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1132 cpu_pwr_status = tegra_pmc_cpu_is_powered(1) || 1133 tegra_pmc_cpu_is_powered(2) || 1134 tegra_pmc_cpu_is_powered(3); 1135 1136 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1137 return false; 1138 1139 return true; 1140} 1141 1142static void tegra30_cpu_clock_suspend(void) 1143{ 1144 /* switch coresite to clk_m, save off original source */ 1145 tegra30_cpu_clk_sctx.clk_csite_src = 1146 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1147 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE); 1148 1149 tegra30_cpu_clk_sctx.cpu_burst = 1150 readl(clk_base + CLK_RESET_CCLK_BURST); 1151 tegra30_cpu_clk_sctx.pllx_base = 1152 readl(clk_base + CLK_RESET_PLLX_BASE); 1153 tegra30_cpu_clk_sctx.pllx_misc = 1154 readl(clk_base + CLK_RESET_PLLX_MISC); 1155 tegra30_cpu_clk_sctx.cclk_divider = 1156 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1157} 1158 1159static void tegra30_cpu_clock_resume(void) 1160{ 1161 unsigned int reg, policy; 1162 u32 misc, base; 1163 1164 /* Is CPU complex already running on PLLX? */ 1165 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1166 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1167 1168 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1169 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1170 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1171 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1172 else 1173 BUG(); 1174 1175 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1176 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC); 1177 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE); 1178 1179 if (misc != tegra30_cpu_clk_sctx.pllx_misc || 1180 base != tegra30_cpu_clk_sctx.pllx_base) { 1181 /* restore PLLX settings if CPU is on different PLL */ 1182 writel(tegra30_cpu_clk_sctx.pllx_misc, 1183 clk_base + CLK_RESET_PLLX_MISC); 1184 writel(tegra30_cpu_clk_sctx.pllx_base, 1185 clk_base + CLK_RESET_PLLX_BASE); 1186 1187 /* wait for PLL stabilization if PLLX was enabled */ 1188 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1189 udelay(300); 1190 } 1191 } 1192 1193 /* 1194 * Restore original burst policy setting for calls resulting from CPU 1195 * LP2 in idle or system suspend. 1196 */ 1197 writel(tegra30_cpu_clk_sctx.cclk_divider, 1198 clk_base + CLK_RESET_CCLK_DIVIDER); 1199 writel(tegra30_cpu_clk_sctx.cpu_burst, 1200 clk_base + CLK_RESET_CCLK_BURST); 1201 1202 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1203 clk_base + CLK_RESET_SOURCE_CSITE); 1204} 1205#endif 1206 1207static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1208 .wait_for_reset = tegra30_wait_cpu_in_reset, 1209 .put_in_reset = tegra30_put_cpu_in_reset, 1210 .out_of_reset = tegra30_cpu_out_of_reset, 1211 .enable_clock = tegra30_enable_cpu_clock, 1212 .disable_clock = tegra30_disable_cpu_clock, 1213#ifdef CONFIG_PM_SLEEP 1214 .rail_off_ready = tegra30_cpu_rail_off_ready, 1215 .suspend = tegra30_cpu_clock_suspend, 1216 .resume = tegra30_cpu_clock_resume, 1217#endif 1218}; 1219 1220static struct tegra_clk_init_table init_table[] __initdata = { 1221 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1222 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1223 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1224 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1225 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, 1226 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 }, 1227 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 }, 1228 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1229 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1230 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1231 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1232 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 }, 1233 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1234 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1235 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1236 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1237 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1238 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1239 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1240 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1241 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1242 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1243 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, 1244 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, 1245 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, 1246 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, 1247 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1248 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1249 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1250 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, 1251 { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, 1252 { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1253 { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1254 { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1255 { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1256 { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1257 { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1258 { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, 1259 { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, 1260 { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, 1261 /* must be the last entry */ 1262 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, 1263}; 1264 1265static void __init tegra30_clock_apply_init_table(void) 1266{ 1267 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX); 1268} 1269 1270/* 1271 * Some clocks may be used by different drivers depending on the board 1272 * configuration. List those here to register them twice in the clock lookup 1273 * table under two names. 1274 */ 1275static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1276 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL), 1277 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL), 1278 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL), 1279 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"), 1280 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"), 1281 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"), 1282 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"), 1283 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"), 1284 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL), 1285 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"), 1286 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"), 1287 /* must be the last entry */ 1288 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), 1289}; 1290 1291static const struct of_device_id pmc_match[] __initconst = { 1292 { .compatible = "nvidia,tegra30-pmc" }, 1293 { }, 1294}; 1295 1296static struct tegra_audio_clk_info tegra30_audio_plls[] = { 1297 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, 1298}; 1299 1300static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec, 1301 void *data) 1302{ 1303 struct clk_hw *hw; 1304 struct clk *clk; 1305 1306 clk = of_clk_src_onecell_get(clkspec, data); 1307 if (IS_ERR(clk)) 1308 return clk; 1309 1310 hw = __clk_get_hw(clk); 1311 1312 if (clkspec->args[0] == TEGRA30_CLK_EMC) { 1313 if (!tegra20_clk_emc_driver_available(hw)) 1314 return ERR_PTR(-EPROBE_DEFER); 1315 } 1316 1317 return clk; 1318} 1319 1320static void __init tegra30_clock_init(struct device_node *np) 1321{ 1322 struct device_node *node; 1323 1324 clk_base = of_iomap(np, 0); 1325 if (!clk_base) { 1326 pr_err("ioremap tegra30 CAR failed\n"); 1327 return; 1328 } 1329 1330 node = of_find_matching_node(NULL, pmc_match); 1331 if (!node) { 1332 pr_err("Failed to find pmc node\n"); 1333 BUG(); 1334 } 1335 1336 pmc_base = of_iomap(node, 0); 1337 if (!pmc_base) { 1338 pr_err("Can't map pmc registers\n"); 1339 BUG(); 1340 } 1341 1342 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX, 1343 TEGRA30_CLK_PERIPH_BANKS); 1344 if (!clks) 1345 return; 1346 1347 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, 1348 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq, 1349 NULL) < 0) 1350 return; 1351 1352 tegra_fixed_clk_init(tegra30_clks); 1353 tegra30_pll_init(); 1354 tegra30_super_clk_init(); 1355 tegra30_periph_clk_init(); 1356 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, 1357 tegra30_audio_plls, 1358 ARRAY_SIZE(tegra30_audio_plls), 24000000); 1359 1360 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX); 1361 1362 tegra_add_of_provider(np, tegra30_clk_src_onecell_get); 1363 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1364 1365 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1366 1367 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 1368} 1369CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 1370